1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OMAP4 boot 4 * 5 * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/omap_common.h> 11 #include <asm/arch/sys_proto.h> 12 #include <spl.h> 13 14 static u32 boot_devices[] = { 15 BOOT_DEVICE_MMC2, 16 BOOT_DEVICE_XIP, 17 BOOT_DEVICE_XIPWAIT, 18 BOOT_DEVICE_NAND, 19 BOOT_DEVICE_XIPWAIT, 20 BOOT_DEVICE_MMC1, 21 BOOT_DEVICE_ONENAND, 22 BOOT_DEVICE_ONENAND, 23 BOOT_DEVICE_MMC2, 24 BOOT_DEVICE_ONENAND, 25 BOOT_DEVICE_XIPWAIT, 26 BOOT_DEVICE_NAND, 27 BOOT_DEVICE_NAND, 28 BOOT_DEVICE_MMC1, 29 BOOT_DEVICE_ONENAND, 30 BOOT_DEVICE_MMC2, 31 BOOT_DEVICE_XIP, 32 BOOT_DEVICE_XIPWAIT, 33 BOOT_DEVICE_NAND, 34 BOOT_DEVICE_MMC1, 35 BOOT_DEVICE_MMC1, 36 BOOT_DEVICE_ONENAND, 37 BOOT_DEVICE_MMC2, 38 BOOT_DEVICE_XIP, 39 BOOT_DEVICE_MMC2_2, 40 BOOT_DEVICE_NAND, 41 BOOT_DEVICE_MMC2_2, 42 BOOT_DEVICE_MMC1, 43 BOOT_DEVICE_MMC2_2, 44 BOOT_DEVICE_MMC2_2, 45 BOOT_DEVICE_NONE, 46 BOOT_DEVICE_XIPWAIT, 47 }; 48 49 u32 omap_sys_boot_device(void) 50 { 51 u32 sys_boot; 52 53 /* Grab the first 5 bits of the status register for SYS_BOOT. */ 54 sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1); 55 56 if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) 57 return BOOT_DEVICE_NONE; 58 59 return boot_devices[sys_boot]; 60 } 61 62 int omap_reboot_mode(char *mode, unsigned int length) 63 { 64 unsigned int limit; 65 unsigned int i; 66 67 if (length < 2) 68 return -1; 69 70 if (!warm_reset()) 71 return -1; 72 73 limit = (length < OMAP_REBOOT_REASON_SIZE) ? length : 74 OMAP_REBOOT_REASON_SIZE; 75 76 for (i = 0; i < (limit - 1); i++) 77 mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE + 78 OMAP_REBOOT_REASON_OFFSET + i)); 79 80 mode[i] = '\0'; 81 82 return 0; 83 } 84 85 int omap_reboot_mode_clear(void) 86 { 87 writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); 88 89 return 0; 90 } 91 92 int omap_reboot_mode_store(char *mode) 93 { 94 unsigned int i; 95 96 for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++) 97 writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + 98 OMAP_REBOOT_REASON_OFFSET + i)); 99 100 writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + 101 OMAP_REBOOT_REASON_OFFSET + i)); 102 103 return 0; 104 } 105