1 /* 2 * Functions related to OMAP3 SDRC. 3 * 4 * This file has been created after exctracting and consolidating 5 * the SDRC related content from mem.c and board.c, also created 6 * generic init function (mem_init). 7 * 8 * Copyright (C) 2004-2010 9 * Texas Instruments Incorporated - http://www.ti.com/ 10 * 11 * Copyright (C) 2011 12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> 13 * 14 * Author : 15 * Vaibhav Hiremath <hvaibhav@ti.com> 16 * 17 * Original implementation by (mem.c, board.c) : 18 * Sunil Kumar <sunilsaini05@gmail.com> 19 * Shashi Ranjan <shashiranjanmca05@gmail.com> 20 * Manikandan Pillai <mani.pillai@ti.com> 21 * 22 * SPDX-License-Identifier: GPL-2.0+ 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/mem.h> 28 #include <asm/arch/sys_proto.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 extern omap3_sysinfo sysinfo; 32 33 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; 34 35 /* 36 * is_mem_sdr - 37 * - Return 1 if mem type in use is SDR 38 */ 39 u32 is_mem_sdr(void) 40 { 41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) 42 return 1; 43 return 0; 44 } 45 46 /* 47 * make_cs1_contiguous - 48 * - When we have CS1 populated we want to have it mapped after cs0 to allow 49 * command line mem=xyz use all memory with out discontinuous support 50 * compiled in. We could do it in the ATAG, but there really is two banks... 51 */ 52 void make_cs1_contiguous(void) 53 { 54 u32 size, a_add_low, a_add_high; 55 56 size = get_sdr_cs_size(CS0); 57 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ 58 a_add_high = (size & 3) << 8; /* set up low field */ 59 a_add_low = (size & 0x3C) >> 2; /* set up high field */ 60 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); 61 62 } 63 64 65 /* 66 * get_sdr_cs_size - 67 * - Get size of chip select 0/1 68 */ 69 u32 get_sdr_cs_size(u32 cs) 70 { 71 u32 size; 72 73 /* get ram size field */ 74 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; 75 size &= 0x3FF; /* remove unwanted bits */ 76 size <<= 21; /* multiply by 2 MiB to find size in MB */ 77 return size; 78 } 79 80 /* 81 * get_sdr_cs_offset - 82 * - Get offset of cs from cs0 start 83 */ 84 u32 get_sdr_cs_offset(u32 cs) 85 { 86 u32 offset; 87 88 if (!cs) 89 return 0; 90 91 offset = readl(&sdrc_base->cs_cfg); 92 offset = (offset & 15) << 27 | (offset & 0x300) << 17; 93 94 return offset; 95 } 96 97 /* 98 * write_sdrc_timings - 99 * - Takes CS and associated timings and initalize SDRAM 100 * - Test CS to make sure it's OK for use 101 */ 102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, 103 struct board_sdrc_timings *timings) 104 { 105 /* Setup timings we got from the board. */ 106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); 107 writel(timings->ctrla, &sdrc_actim_base->ctrla); 108 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); 109 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); 110 writel(CMD_NOP, &sdrc_base->cs[cs].manual); 111 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); 112 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); 113 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); 114 writel(timings->mr, &sdrc_base->cs[cs].mr); 115 116 /* 117 * Test ram in this bank 118 * Disable if bad or not present 119 */ 120 if (!mem_ok(cs)) 121 writel(0, &sdrc_base->cs[cs].mcfg); 122 } 123 124 /* 125 * do_sdrc_init - 126 * - Code called once in C-Stack only context for CS0 and with early being 127 * true and a possible 2nd time depending on memory configuration from 128 * stack+global context. 129 */ 130 void do_sdrc_init(u32 cs, u32 early) 131 { 132 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; 133 struct board_sdrc_timings timings; 134 135 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; 136 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; 137 138 /* set some default timings */ 139 timings.sharing = SDRC_SHARING; 140 141 /* 142 * When called in the early context this may be SPL and we will 143 * need to set all of the timings. This ends up being board 144 * specific so we call a helper function to take care of this 145 * for us. Otherwise, to be safe, we need to copy the settings 146 * from the first bank to the second. We will setup CS0, 147 * then set cs_cfg to the appropriate value then try and 148 * setup CS1. 149 */ 150 #ifdef CONFIG_SPL_BUILD 151 /* set/modify board-specific timings */ 152 get_board_mem_timings(&timings); 153 #endif 154 if (early) { 155 /* reset sdrc controller */ 156 writel(SOFTRESET, &sdrc_base->sysconfig); 157 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, 158 12000000); 159 writel(0, &sdrc_base->sysconfig); 160 161 /* setup sdrc to ball mux */ 162 writel(timings.sharing, &sdrc_base->sharing); 163 164 /* Disable Power Down of CKE because of 1 CKE on combo part */ 165 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, 166 &sdrc_base->power); 167 168 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); 169 sdelay(0x20000); 170 #ifdef CONFIG_SPL_BUILD 171 write_sdrc_timings(CS0, sdrc_actim_base0, &timings); 172 make_cs1_contiguous(); 173 write_sdrc_timings(CS1, sdrc_actim_base1, &timings); 174 #endif 175 176 } 177 178 /* 179 * If we aren't using SPL we have been loaded by some 180 * other means which may not have correctly initialized 181 * both CS0 and CS1 (such as some older versions of x-loader) 182 * so we may be asked now to setup CS1. 183 */ 184 if (cs == CS1) { 185 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), 186 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); 187 timings.ctrla = readl(&sdrc_actim_base0->ctrla); 188 timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); 189 timings.mr = readl(&sdrc_base->cs[CS0].mr); 190 write_sdrc_timings(cs, sdrc_actim_base1, &timings); 191 } 192 } 193 194 /* 195 * dram_init - 196 * - Sets uboots idea of sdram size 197 */ 198 int dram_init(void) 199 { 200 unsigned int size0 = 0, size1 = 0; 201 202 size0 = get_sdr_cs_size(CS0); 203 /* 204 * We always need to have cs_cfg point at where the second 205 * bank would be, if present. Failure to do so can lead to 206 * strange situations where memory isn't detected and 207 * configured correctly. CS0 will already have been setup 208 * at this point. 209 */ 210 make_cs1_contiguous(); 211 do_sdrc_init(CS1, NOT_EARLY); 212 size1 = get_sdr_cs_size(CS1); 213 214 gd->ram_size = size0 + size1; 215 216 return 0; 217 } 218 219 int dram_init_banksize(void) 220 { 221 unsigned int size0 = 0, size1 = 0; 222 223 size0 = get_sdr_cs_size(CS0); 224 size1 = get_sdr_cs_size(CS1); 225 226 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 227 gd->bd->bi_dram[0].size = size0; 228 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); 229 gd->bd->bi_dram[1].size = size1; 230 231 return 0; 232 } 233 234 /* 235 * mem_init - 236 * - Init the sdrc chip, 237 * - Selects CS0 and CS1, 238 */ 239 void mem_init(void) 240 { 241 /* only init up first bank here */ 242 do_sdrc_init(CS0, EARLY_INIT); 243 } 244