1/* 2 * Board specific setup info 3 * 4 * (C) Copyright 2008 5 * Texas Instruments, <www.ti.com> 6 * 7 * Initial Code by: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Syed Mohammed Khasim <khasim@ti.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#include <config.h> 15#include <asm/arch/mem.h> 16#include <asm/arch/clocks_omap3.h> 17#include <linux/linkage.h> 18 19/* 20 * Funtion for making PPA HAL API calls in secure devices 21 * Input: 22 * R0 - Service ID 23 * R1 - paramer list 24 */ 25ENTRY(do_omap3_emu_romcode_call) 26 PUSH {r4-r12, lr} @ Save all registers from ROM code! 27 MOV r12, r0 @ Copy the Secure Service ID in R12 28 MOV r3, r1 @ Copy the pointer to va_list in R3 29 MOV r1, #0 @ Process ID - 0 30 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer 31 @ to va_list in R3 32 MOV r6, #0xFF @ Indicate new Task call 33 mcr p15, 0, r0, c7, c10, 4 @ DSB 34 mcr p15, 0, r0, c7, c10, 5 @ DMB 35 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled 36 @ because we use -march=armv5 37 POP {r4-r12, pc} 38ENDPROC(do_omap3_emu_romcode_call) 39 40#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) 41/************************************************************************** 42 * cpy_clk_code: relocates clock code into SRAM where its safer to execute 43 * R1 = SRAM destination address. 44 *************************************************************************/ 45ENTRY(cpy_clk_code) 46 /* Copy DPLL code into SRAM */ 47 adr r0, go_to_speed /* copy from start of go_to_speed... */ 48 adr r2, lowlevel_init /* ... up to start of low_level_init */ 49next2: 50 ldmia r0!, {r3 - r10} /* copy from source address [r0] */ 51 stmia r1!, {r3 - r10} /* copy to target address [r1] */ 52 cmp r0, r2 /* until source end address [r2] */ 53 blo next2 54 mov pc, lr /* back to caller */ 55ENDPROC(cpy_clk_code) 56 57/* *************************************************************************** 58 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed 59 * -executed from SRAM. 60 * R0 = CM_CLKEN_PLL-bypass value 61 * R1 = CM_CLKSEL1_PLL-m, n, and divider values 62 * R2 = CM_CLKSEL_CORE-divider values 63 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait 64 * 65 * Note: If core unlocks/relocks and SDRAM is running fast already it gets 66 * confused. A reset of the controller gets it back. Taking away its 67 * L3 when its not in self refresh seems bad for it. Normally, this 68 * code runs from flash before SDR is init so that should be ok. 69 ****************************************************************************/ 70ENTRY(go_to_speed) 71 stmfd sp!, {r4 - r6} 72 73 /* move into fast relock bypass */ 74 ldr r4, pll_ctl_add 75 str r0, [r4] 76wait1: 77 ldr r5, [r3] /* get status */ 78 and r5, r5, #0x1 /* isolate core status */ 79 cmp r5, #0x1 /* still locked? */ 80 beq wait1 /* if lock, loop */ 81 82 /* set new dpll dividers _after_ in bypass */ 83 ldr r5, pll_div_add1 84 str r1, [r5] /* set m, n, m2 */ 85 ldr r5, pll_div_add2 86 str r2, [r5] /* set l3/l4/.. dividers*/ 87 ldr r5, pll_div_add3 /* wkup */ 88 ldr r2, pll_div_val3 /* rsm val */ 89 str r2, [r5] 90 ldr r5, pll_div_add4 /* gfx */ 91 ldr r2, pll_div_val4 92 str r2, [r5] 93 ldr r5, pll_div_add5 /* emu */ 94 ldr r2, pll_div_val5 95 str r2, [r5] 96 97 /* now prepare GPMC (flash) for new dpll speed */ 98 /* flash needs to be stable when we jump back to it */ 99 ldr r5, flash_cfg3_addr 100 ldr r2, flash_cfg3_val 101 str r2, [r5] 102 ldr r5, flash_cfg4_addr 103 ldr r2, flash_cfg4_val 104 str r2, [r5] 105 ldr r5, flash_cfg5_addr 106 ldr r2, flash_cfg5_val 107 str r2, [r5] 108 ldr r5, flash_cfg1_addr 109 ldr r2, [r5] 110 orr r2, r2, #0x3 /* up gpmc divider */ 111 str r2, [r5] 112 113 /* lock DPLL3 and wait a bit */ 114 orr r0, r0, #0x7 /* set up for lock mode */ 115 str r0, [r4] /* lock */ 116 nop /* ARM slow at this point working at sys_clk */ 117 nop 118 nop 119 nop 120wait2: 121 ldr r5, [r3] /* get status */ 122 and r5, r5, #0x1 /* isolate core status */ 123 cmp r5, #0x1 /* still locked? */ 124 bne wait2 /* if lock, loop */ 125 nop 126 nop 127 nop 128 nop 129 ldmfd sp!, {r4 - r6} 130 mov pc, lr /* back to caller, locked */ 131ENDPROC(go_to_speed) 132 133_go_to_speed: .word go_to_speed 134 135/* these constants need to be close for PIC code */ 136/* The Nor has to be in the Flash Base CS0 for this condition to happen */ 137flash_cfg1_addr: 138 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) 139flash_cfg3_addr: 140 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) 141flash_cfg3_val: 142 .word STNOR_GPMC_CONFIG3 143flash_cfg4_addr: 144 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) 145flash_cfg4_val: 146 .word STNOR_GPMC_CONFIG4 147flash_cfg5_val: 148 .word STNOR_GPMC_CONFIG5 149flash_cfg5_addr: 150 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) 151pll_ctl_add: 152 .word CM_CLKEN_PLL 153pll_div_add1: 154 .word CM_CLKSEL1_PLL 155pll_div_add2: 156 .word CM_CLKSEL_CORE 157pll_div_add3: 158 .word CM_CLKSEL_WKUP 159pll_div_val3: 160 .word (WKUP_RSM << 1) 161pll_div_add4: 162 .word CM_CLKSEL_GFX 163pll_div_val4: 164 .word (GFX_DIV << 0) 165pll_div_add5: 166 .word CM_CLKSEL1_EMU 167pll_div_val5: 168 .word CLSEL1_EMU_VAL 169 170#endif 171 172ENTRY(lowlevel_init) 173 ldr sp, SRAM_STACK 174 str ip, [sp] /* stash ip register */ 175 mov ip, lr /* save link reg across call */ 176#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 177/* 178 * No need to copy/exec the clock code - DPLL adjust already done 179 * in NAND/oneNAND Boot. 180 */ 181 ldr r1, =SRAM_CLK_CODE 182 bl cpy_clk_code 183#endif /* NAND Boot */ 184 mov lr, ip /* restore link reg */ 185 ldr ip, [sp] /* restore save ip */ 186 /* tail-call s_init to setup pll, mux, memory */ 187 b s_init 188 189ENDPROC(lowlevel_init) 190 191 /* the literal pools origin */ 192 .ltorg 193 194REG_CONTROL_STATUS: 195 .word CONTROL_STATUS 196SRAM_STACK: 197 .word LOW_LEVEL_SRAM_STACK 198 199/* DPLL(1-4) PARAM TABLES */ 200 201/* 202 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal 203 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). 204 * The values are defined for all possible sysclk and for ES1 and ES2. 205 */ 206 207mpu_dpll_param: 208/* 12MHz */ 209/* ES1 */ 210.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 211/* ES2 */ 212.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 213/* 3410 */ 214.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 215 216/* 13MHz */ 217/* ES1 */ 218.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 219/* ES2 */ 220.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 221/* 3410 */ 222.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 223 224/* 19.2MHz */ 225/* ES1 */ 226.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 227/* ES2 */ 228.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 229/* 3410 */ 230.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 231 232/* 26MHz */ 233/* ES1 */ 234.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 235/* ES2 */ 236.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 237/* 3410 */ 238.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 239 240/* 38.4MHz */ 241/* ES1 */ 242.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 243/* ES2 */ 244.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 245/* 3410 */ 246.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 247 248 249.globl get_mpu_dpll_param 250get_mpu_dpll_param: 251 adr r0, mpu_dpll_param 252 mov pc, lr 253 254iva_dpll_param: 255/* 12MHz */ 256/* ES1 */ 257.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 258/* ES2 */ 259.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 260/* 3410 */ 261.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 262 263/* 13MHz */ 264/* ES1 */ 265.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 266/* ES2 */ 267.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 268/* 3410 */ 269.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 270 271/* 19.2MHz */ 272/* ES1 */ 273.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 274/* ES2 */ 275.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 276/* 3410 */ 277.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 278 279/* 26MHz */ 280/* ES1 */ 281.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 282/* ES2 */ 283.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 284/* 3410 */ 285.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 286 287/* 38.4MHz */ 288/* ES1 */ 289.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 290/* ES2 */ 291.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 292/* 3410 */ 293.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 294 295 296.globl get_iva_dpll_param 297get_iva_dpll_param: 298 adr r0, iva_dpll_param 299 mov pc, lr 300 301/* Core DPLL targets for L3 at 166 & L133 */ 302core_dpll_param: 303/* 12MHz */ 304/* ES1 */ 305.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 306/* ES2 */ 307.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 308/* 3410 */ 309.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 310 311/* 13MHz */ 312/* ES1 */ 313.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 314/* ES2 */ 315.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 316/* 3410 */ 317.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 318 319/* 19.2MHz */ 320/* ES1 */ 321.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 322/* ES2 */ 323.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 324/* 3410 */ 325.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 326 327/* 26MHz */ 328/* ES1 */ 329.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 330/* ES2 */ 331.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 332/* 3410 */ 333.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 334 335/* 38.4MHz */ 336/* ES1 */ 337.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 338/* ES2 */ 339.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 340/* 3410 */ 341.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 342 343.globl get_core_dpll_param 344get_core_dpll_param: 345 adr r0, core_dpll_param 346 mov pc, lr 347 348/* PER DPLL values are same for both ES1 and ES2 */ 349per_dpll_param: 350/* 12MHz */ 351.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 352 353/* 13MHz */ 354.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 355 356/* 19.2MHz */ 357.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 358 359/* 26MHz */ 360.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 361 362/* 38.4MHz */ 363.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 364 365.globl get_per_dpll_param 366get_per_dpll_param: 367 adr r0, per_dpll_param 368 mov pc, lr 369 370/* PER2 DPLL values */ 371per2_dpll_param: 372/* 12MHz */ 373.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 374 375/* 13MHz */ 376.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 377 378/* 19.2MHz */ 379.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 380 381/* 26MHz */ 382.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 383 384/* 38.4MHz */ 385.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 386 387.globl get_per2_dpll_param 388get_per2_dpll_param: 389 adr r0, per2_dpll_param 390 mov pc, lr 391 392/* 393 * Tables for 36XX/37XX devices 394 * 395 */ 396mpu_36x_dpll_param: 397/* 12MHz */ 398.word 50, 0, 0, 1 399/* 13MHz */ 400.word 600, 12, 0, 1 401/* 19.2MHz */ 402.word 125, 3, 0, 1 403/* 26MHz */ 404.word 300, 12, 0, 1 405/* 38.4MHz */ 406.word 125, 7, 0, 1 407 408iva_36x_dpll_param: 409/* 12MHz */ 410.word 130, 2, 0, 1 411/* 13MHz */ 412.word 20, 0, 0, 1 413/* 19.2MHz */ 414.word 325, 11, 0, 1 415/* 26MHz */ 416.word 10, 0, 0, 1 417/* 38.4MHz */ 418.word 325, 23, 0, 1 419 420core_36x_dpll_param: 421/* 12MHz */ 422.word 100, 2, 0, 1 423/* 13MHz */ 424.word 400, 12, 0, 1 425/* 19.2MHz */ 426.word 375, 17, 0, 1 427/* 26MHz */ 428.word 200, 12, 0, 1 429/* 38.4MHz */ 430.word 375, 35, 0, 1 431 432per_36x_dpll_param: 433/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ 434.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 435.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 436.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 437.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 438.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 439 440per2_36x_dpll_param: 441/* 12MHz */ 442.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 443/* 13MHz */ 444.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 445/* 19.2MHz */ 446.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 447/* 26MHz */ 448.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 449/* 38.4MHz */ 450.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 451 452 453ENTRY(get_36x_mpu_dpll_param) 454 adr r0, mpu_36x_dpll_param 455 mov pc, lr 456ENDPROC(get_36x_mpu_dpll_param) 457 458ENTRY(get_36x_iva_dpll_param) 459 adr r0, iva_36x_dpll_param 460 mov pc, lr 461ENDPROC(get_36x_iva_dpll_param) 462 463ENTRY(get_36x_core_dpll_param) 464 adr r0, core_36x_dpll_param 465 mov pc, lr 466ENDPROC(get_36x_core_dpll_param) 467 468ENTRY(get_36x_per_dpll_param) 469 adr r0, per_36x_dpll_param 470 mov pc, lr 471ENDPROC(get_36x_per_dpll_param) 472 473ENTRY(get_36x_per2_dpll_param) 474 adr r0, per2_36x_dpll_param 475 mov pc, lr 476ENDPROC(get_36x_per2_dpll_param) 477