1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Author : 4 * Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on mem.c and sdrc.c 7 * 8 * Copyright (C) 2010 9 * Texas Instruments Incorporated - http://www.ti.com/ 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/arch/mem.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/emif4.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 extern omap3_sysinfo sysinfo; 20 21 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; 22 23 /* 24 * is_mem_sdr - 25 * - Return 1 if mem type in use is SDR 26 */ 27 u32 is_mem_sdr(void) 28 { 29 return 0; 30 } 31 32 /* 33 * get_sdr_cs_size - 34 * - Get size of chip select 0/1 35 */ 36 u32 get_sdr_cs_size(u32 cs) 37 { 38 u32 size = 0; 39 40 /* TODO: Calculate the size based on EMIF4 configuration */ 41 if (cs == CS0) 42 size = CONFIG_SYS_CS0_SIZE; 43 44 return size; 45 } 46 47 /* 48 * get_sdr_cs_offset - 49 * - Get offset of cs from cs0 start 50 */ 51 u32 get_sdr_cs_offset(u32 cs) 52 { 53 u32 offset = 0; 54 55 return offset; 56 } 57 58 /* 59 * do_emif4_init - 60 * - Init the emif4 module for DDR access 61 * - Early init routines, called from flash or SRAM. 62 */ 63 static void do_emif4_init(void) 64 { 65 unsigned int regval; 66 /* Set the DDR PHY parameters in PHY ctrl registers */ 67 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | 68 EMIF4_DDR1_EXT_STRB_DIS); 69 writel(regval, &emif4_base->ddr_phyctrl1); 70 writel(regval, &emif4_base->ddr_phyctrl1_shdw); 71 writel(0, &emif4_base->ddr_phyctrl2); 72 73 /* Reset the DDR PHY and wait till completed */ 74 regval = readl(&emif4_base->sdram_iodft_tlgc); 75 regval |= (1<<10); 76 writel(regval, &emif4_base->sdram_iodft_tlgc); 77 /*Wait till that bit clears*/ 78 while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0); 79 /*Re-verify the DDR PHY status*/ 80 while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); 81 82 regval |= (1<<0); 83 writel(regval, &emif4_base->sdram_iodft_tlgc); 84 /* Set SDR timing registers */ 85 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | 86 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | 87 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | 88 EMIF4_TIM1_T_RP); 89 writel(regval, &emif4_base->sdram_time1); 90 writel(regval, &emif4_base->sdram_time1_shdw); 91 92 regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | 93 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | 94 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); 95 writel(regval, &emif4_base->sdram_time2); 96 writel(regval, &emif4_base->sdram_time2_shdw); 97 98 regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); 99 writel(regval, &emif4_base->sdram_time3); 100 writel(regval, &emif4_base->sdram_time3_shdw); 101 102 /* Set the PWR control register */ 103 regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | 104 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); 105 writel(regval, &emif4_base->sdram_pwr_mgmt); 106 writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); 107 108 /* Set the DDR refresh rate control register */ 109 regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); 110 writel(regval, &emif4_base->sdram_refresh_ctrl); 111 writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); 112 113 /* set the SDRAM configuration register */ 114 regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | 115 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | 116 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | 117 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | 118 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | 119 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); 120 writel(regval, &emif4_base->sdram_config); 121 } 122 123 /* 124 * dram_init - 125 * - Sets uboots idea of sdram size 126 */ 127 int dram_init(void) 128 { 129 unsigned int size0 = 0, size1 = 0; 130 131 size0 = get_sdr_cs_size(CS0); 132 /* 133 * If a second bank of DDR is attached to CS1 this is 134 * where it can be started. Early init code will init 135 * memory on CS0. 136 */ 137 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) 138 size1 = get_sdr_cs_size(CS1); 139 140 gd->ram_size = size0 + size1; 141 return 0; 142 } 143 144 int dram_init_banksize(void) 145 { 146 unsigned int size0 = 0, size1 = 0; 147 148 size0 = get_sdr_cs_size(CS0); 149 size1 = get_sdr_cs_size(CS1); 150 151 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 152 gd->bd->bi_dram[0].size = size0; 153 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); 154 gd->bd->bi_dram[1].size = size1; 155 156 return 0; 157 } 158 159 /* 160 * mem_init() - 161 * - Initialize memory subsystem 162 */ 163 void mem_init(void) 164 { 165 do_emif4_init(); 166 } 167