1 /* 2 * Author : 3 * Vaibhav Hiremath <hvaibhav@ti.com> 4 * 5 * Based on mem.c and sdrc.c 6 * 7 * Copyright (C) 2010 8 * Texas Instruments Incorporated - http://www.ti.com/ 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/mem.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/emif4.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 extern omap3_sysinfo sysinfo; 21 22 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; 23 24 /* 25 * is_mem_sdr - 26 * - Return 1 if mem type in use is SDR 27 */ 28 u32 is_mem_sdr(void) 29 { 30 return 0; 31 } 32 33 /* 34 * get_sdr_cs_size - 35 * - Get size of chip select 0/1 36 */ 37 u32 get_sdr_cs_size(u32 cs) 38 { 39 u32 size = 0; 40 41 /* TODO: Calculate the size based on EMIF4 configuration */ 42 if (cs == CS0) 43 size = CONFIG_SYS_CS0_SIZE; 44 45 return size; 46 } 47 48 /* 49 * get_sdr_cs_offset - 50 * - Get offset of cs from cs0 start 51 */ 52 u32 get_sdr_cs_offset(u32 cs) 53 { 54 u32 offset = 0; 55 56 return offset; 57 } 58 59 /* 60 * do_emif4_init - 61 * - Init the emif4 module for DDR access 62 * - Early init routines, called from flash or SRAM. 63 */ 64 static void do_emif4_init(void) 65 { 66 unsigned int regval; 67 /* Set the DDR PHY parameters in PHY ctrl registers */ 68 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | 69 EMIF4_DDR1_EXT_STRB_DIS); 70 writel(regval, &emif4_base->ddr_phyctrl1); 71 writel(regval, &emif4_base->ddr_phyctrl1_shdw); 72 writel(0, &emif4_base->ddr_phyctrl2); 73 74 /* Reset the DDR PHY and wait till completed */ 75 regval = readl(&emif4_base->sdram_iodft_tlgc); 76 regval |= (1<<10); 77 writel(regval, &emif4_base->sdram_iodft_tlgc); 78 /*Wait till that bit clears*/ 79 while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0); 80 /*Re-verify the DDR PHY status*/ 81 while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); 82 83 regval |= (1<<0); 84 writel(regval, &emif4_base->sdram_iodft_tlgc); 85 /* Set SDR timing registers */ 86 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | 87 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | 88 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | 89 EMIF4_TIM1_T_RP); 90 writel(regval, &emif4_base->sdram_time1); 91 writel(regval, &emif4_base->sdram_time1_shdw); 92 93 regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | 94 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | 95 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); 96 writel(regval, &emif4_base->sdram_time2); 97 writel(regval, &emif4_base->sdram_time2_shdw); 98 99 regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); 100 writel(regval, &emif4_base->sdram_time3); 101 writel(regval, &emif4_base->sdram_time3_shdw); 102 103 /* Set the PWR control register */ 104 regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | 105 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); 106 writel(regval, &emif4_base->sdram_pwr_mgmt); 107 writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); 108 109 /* Set the DDR refresh rate control register */ 110 regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); 111 writel(regval, &emif4_base->sdram_refresh_ctrl); 112 writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); 113 114 /* set the SDRAM configuration register */ 115 regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | 116 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | 117 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | 118 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | 119 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | 120 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); 121 writel(regval, &emif4_base->sdram_config); 122 } 123 124 /* 125 * dram_init - 126 * - Sets uboots idea of sdram size 127 */ 128 int dram_init(void) 129 { 130 unsigned int size0 = 0, size1 = 0; 131 132 size0 = get_sdr_cs_size(CS0); 133 /* 134 * If a second bank of DDR is attached to CS1 this is 135 * where it can be started. Early init code will init 136 * memory on CS0. 137 */ 138 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) 139 size1 = get_sdr_cs_size(CS1); 140 141 gd->ram_size = size0 + size1; 142 return 0; 143 } 144 145 int dram_init_banksize(void) 146 { 147 unsigned int size0 = 0, size1 = 0; 148 149 size0 = get_sdr_cs_size(CS0); 150 size1 = get_sdr_cs_size(CS1); 151 152 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 153 gd->bd->bi_dram[0].size = size0; 154 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); 155 gd->bd->bi_dram[1].size = size1; 156 157 return 0; 158 } 159 160 /* 161 * mem_init() - 162 * - Initialize memory subsystem 163 */ 164 void mem_init(void) 165 { 166 do_emif4_init(); 167 } 168