xref: /openbmc/u-boot/arch/arm/mach-omap2/omap3/clock.c (revision ecab65e4)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2008
4  * Texas Instruments, <www.ti.com>
5  *
6  * Author :
7  *      Manikandan Pillai <mani.pillai@ti.com>
8  *
9  * Derived from Beagle Board and OMAP3 SDP code by
10  *      Richard Woodruff <r-woodruff2@ti.com>
11  *      Syed Mohammed Khasim <khasim@ti.com>
12  */
13 
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/clocks_omap3.h>
18 #include <asm/arch/mem.h>
19 #include <asm/arch/sys_proto.h>
20 #include <environment.h>
21 #include <command.h>
22 
23 /******************************************************************************
24  * get_sys_clk_speed() - determine reference oscillator speed
25  *                       based on known 32kHz clock and gptimer.
26  *****************************************************************************/
27 u32 get_osc_clk_speed(void)
28 {
29 	u32 start, cstart, cend, cdiff, cdiv, val;
30 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
31 	struct prm *prm_base = (struct prm *)PRM_BASE;
32 	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
33 	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
34 
35 	val = readl(&prm_base->clksrc_ctrl);
36 
37 	if (val & SYSCLKDIV_2)
38 		cdiv = 2;
39 	else
40 		cdiv = 1;
41 
42 	/* enable timer2 */
43 	val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
44 
45 	/* select sys_clk for GPT1 */
46 	writel(val, &prcm_base->clksel_wkup);
47 
48 	/* Enable I and F Clocks for GPT1 */
49 	val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
50 	writel(val, &prcm_base->iclken_wkup);
51 
52 	val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
53 	writel(val, &prcm_base->fclken_wkup);
54 
55 	writel(0, &gpt1_base->tldr);		/* start counting at 0 */
56 	writel(GPT_EN, &gpt1_base->tclr);	/* enable clock */
57 
58 	/* enable 32kHz source, determine sys_clk via gauging */
59 
60 	/* start time in 20 cycles */
61 	start = 20 + readl(&s32k_base->s32k_cr);
62 
63 	/* dead loop till start time */
64 	while (readl(&s32k_base->s32k_cr) < start);
65 
66 	/* get start sys_clk count */
67 	cstart = readl(&gpt1_base->tcrr);
68 
69 	/* wait for 40 cycles */
70 	while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
71 	cend = readl(&gpt1_base->tcrr);		/* get end sys_clk count */
72 	cdiff = cend - cstart;			/* get elapsed ticks */
73 	cdiff *= cdiv;
74 
75 	/* based on number of ticks assign speed */
76 	if (cdiff > 19000)
77 		return S38_4M;
78 	else if (cdiff > 15200)
79 		return S26M;
80 	else if (cdiff > 13000)
81 		return S24M;
82 	else if (cdiff > 9000)
83 		return S19_2M;
84 	else if (cdiff > 7600)
85 		return S13M;
86 	else
87 		return S12M;
88 }
89 
90 /******************************************************************************
91  * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
92  *                       input oscillator clock frequency.
93  *****************************************************************************/
94 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
95 {
96 	switch(osc_clk) {
97 	case S38_4M:
98 		*sys_clkin_sel = 4;
99 		break;
100 	case S26M:
101 		*sys_clkin_sel = 3;
102 		break;
103 	case S19_2M:
104 		*sys_clkin_sel = 2;
105 		break;
106 	case S13M:
107 		*sys_clkin_sel = 1;
108 		break;
109 	case S12M:
110 	default:
111 		*sys_clkin_sel = 0;
112 	}
113 }
114 
115 /*
116  * OMAP34XX/35XX specific functions
117  */
118 
119 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
120 {
121 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
122 	dpll_param *ptr = (dpll_param *) get_core_dpll_param();
123 	void (*f_lock_pll) (u32, u32, u32, u32);
124 	int xip_safe, p0, p1, p2, p3;
125 
126 	xip_safe = is_running_in_sram();
127 
128 	/* Moving to the right sysclk and ES rev base */
129 	ptr = ptr + (3 * clk_index) + sil_index;
130 
131 	if (xip_safe) {
132 		/*
133 		 * CORE DPLL
134 		 */
135 		clrsetbits_le32(&prcm_base->clken_pll,
136 				0x00000007, PLL_FAST_RELOCK_BYPASS);
137 		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
138 				LDELAY);
139 
140 		/*
141 		 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
142 		 * work. write another value and then default value.
143 		 */
144 
145 		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
146 		clrsetbits_le32(&prcm_base->clksel1_emu,
147 				0x001F0000, (CORE_M3X2 + 1) << 16) ;
148 		clrsetbits_le32(&prcm_base->clksel1_emu,
149 				0x001F0000, CORE_M3X2 << 16);
150 
151 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
152 		clrsetbits_le32(&prcm_base->clksel1_pll,
153 				0xF8000000, ptr->m2 << 27);
154 
155 		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
156 		clrsetbits_le32(&prcm_base->clksel1_pll,
157 				0x07FF0000, ptr->m << 16);
158 
159 		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
160 		clrsetbits_le32(&prcm_base->clksel1_pll,
161 				0x00007F00, ptr->n << 8);
162 
163 		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
164 		clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
165 
166 		/* SSI */
167 		clrsetbits_le32(&prcm_base->clksel_core,
168 				0x00000F00, CORE_SSI_DIV << 8);
169 		/* FSUSB */
170 		clrsetbits_le32(&prcm_base->clksel_core,
171 				0x00000030, CORE_FUSB_DIV << 4);
172 		/* L4 */
173 		clrsetbits_le32(&prcm_base->clksel_core,
174 				0x0000000C, CORE_L4_DIV << 2);
175 		/* L3 */
176 		clrsetbits_le32(&prcm_base->clksel_core,
177 				0x00000003, CORE_L3_DIV);
178 		/* GFX */
179 		clrsetbits_le32(&prcm_base->clksel_gfx,
180 				0x00000007, GFX_DIV);
181 		/* RESET MGR */
182 		clrsetbits_le32(&prcm_base->clksel_wkup,
183 				0x00000006, WKUP_RSM << 1);
184 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
185 		clrsetbits_le32(&prcm_base->clken_pll,
186 				0x000000F0, ptr->fsel << 4);
187 		/* LOCK MODE */
188 		clrsetbits_le32(&prcm_base->clken_pll,
189 				0x00000007, PLL_LOCK);
190 
191 		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
192 				LDELAY);
193 	} else if (is_running_in_flash()) {
194 		/*
195 		 * if running from flash, jump to small relocated code
196 		 * area in SRAM.
197 		 */
198 		f_lock_pll = (void *) (SRAM_CLK_CODE);
199 
200 		p0 = readl(&prcm_base->clken_pll);
201 		clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
202 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
203 		clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
204 
205 		p1 = readl(&prcm_base->clksel1_pll);
206 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
207 		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
208 		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
209 		clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
210 		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
211 		clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
212 		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
213 		clrbits_le32(&p1, 0x00000040);
214 
215 		p2 = readl(&prcm_base->clksel_core);
216 		/* SSI */
217 		clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
218 		/* FSUSB */
219 		clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
220 		/* L4 */
221 		clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
222 		/* L3 */
223 		clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
224 
225 		p3 = (u32)&prcm_base->idlest_ckgen;
226 
227 		(*f_lock_pll) (p0, p1, p2, p3);
228 	}
229 }
230 
231 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
232 {
233 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
234 	dpll_param *ptr = (dpll_param *) get_per_dpll_param();
235 
236 	/* Moving it to the right sysclk base */
237 	ptr = ptr + clk_index;
238 
239 	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
240 	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
241 	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
242 
243 	/*
244 	 * Errata 1.50 Workaround for OMAP3 ES1.0 only
245 	 * If using default divisors, write default divisor + 1
246 	 * and then the actual divisor value
247 	 */
248 	/* M6 */
249 	clrsetbits_le32(&prcm_base->clksel1_emu,
250 			0x1F000000, (PER_M6X2 + 1) << 24);
251 	clrsetbits_le32(&prcm_base->clksel1_emu,
252 			0x1F000000, PER_M6X2 << 24);
253 	/* M5 */
254 	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
255 	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
256 	/* M4 */
257 	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
258 	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
259 	/* M3 */
260 	clrsetbits_le32(&prcm_base->clksel_dss,
261 			0x00001F00, (PER_M3X2 + 1) << 8);
262 	clrsetbits_le32(&prcm_base->clksel_dss,
263 			0x00001F00, PER_M3X2 << 8);
264 	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
265 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
266 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
267 	/* Workaround end */
268 
269 	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
270 	clrsetbits_le32(&prcm_base->clksel2_pll,
271 			0x0007FF00, ptr->m << 8);
272 
273 	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
274 	clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
275 
276 	/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
277 	clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
278 
279 	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
280 	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
281 	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
282 }
283 
284 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
285 {
286 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
287 	dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
288 
289 	/* Moving it to the right sysclk base */
290 	ptr = ptr + clk_index;
291 
292 	/* PER2 DPLL (DPLL5) */
293 	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
294 	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
295 	/* set M2 (usbtll_fck) */
296 	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
297 	/* set m (11-bit multiplier) */
298 	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
299 	/* set n (7-bit divider)*/
300 	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
301 	/* FREQSEL */
302 	clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
303 	/* lock mode */
304 	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
305 	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
306 }
307 
308 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
309 {
310 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
311 	dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
312 
313 	/* Moving to the right sysclk and ES rev base */
314 	ptr = ptr + (3 * clk_index) + sil_index;
315 
316 	/* MPU DPLL (unlocked already) */
317 
318 	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
319 	clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
320 			0x0000001F, ptr->m2);
321 
322 	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
323 	clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
324 			0x0007FF00, ptr->m << 8);
325 
326 	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
327 	clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
328 			0x0000007F, ptr->n);
329 
330 	/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
331 	clrsetbits_le32(&prcm_base->clken_pll_mpu,
332 			0x000000F0, ptr->fsel << 4);
333 }
334 
335 static void iva_init_34xx(u32 sil_index, u32 clk_index)
336 {
337 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
338 	dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
339 
340 	/* Moving to the right sysclk and ES rev base */
341 	ptr = ptr + (3 * clk_index) + sil_index;
342 
343 	/* IVA DPLL */
344 	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
345 	clrsetbits_le32(&prcm_base->clken_pll_iva2,
346 			0x00000007, PLL_STOP);
347 	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
348 
349 	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
350 	clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
351 			0x0000001F, ptr->m2);
352 
353 	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
354 	clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
355 			0x0007FF00, ptr->m << 8);
356 
357 	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
358 	clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
359 			0x0000007F, ptr->n);
360 
361 	/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
362 	clrsetbits_le32(&prcm_base->clken_pll_iva2,
363 			0x000000F0, ptr->fsel << 4);
364 
365 	/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
366 	clrsetbits_le32(&prcm_base->clken_pll_iva2,
367 			0x00000007, PLL_LOCK);
368 
369 	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
370 }
371 
372 /*
373  * OMAP3630 specific functions
374  */
375 
376 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
377 {
378 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
379 	dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
380 	void (*f_lock_pll) (u32, u32, u32, u32);
381 	int xip_safe, p0, p1, p2, p3;
382 
383 	xip_safe = is_running_in_sram();
384 
385 	/* Moving it to the right sysclk base */
386 	ptr += clk_index;
387 
388 	if (xip_safe) {
389 		/* CORE DPLL */
390 
391 		/* Select relock bypass: CM_CLKEN_PLL[0:2] */
392 		clrsetbits_le32(&prcm_base->clken_pll,
393 				0x00000007, PLL_FAST_RELOCK_BYPASS);
394 		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
395 				LDELAY);
396 
397 		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
398 		clrsetbits_le32(&prcm_base->clksel1_emu,
399 				0x001F0000, CORE_M3X2 << 16);
400 
401 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
402 		clrsetbits_le32(&prcm_base->clksel1_pll,
403 				0xF8000000, ptr->m2 << 27);
404 
405 		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
406 		clrsetbits_le32(&prcm_base->clksel1_pll,
407 				0x07FF0000, ptr->m << 16);
408 
409 		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
410 		clrsetbits_le32(&prcm_base->clksel1_pll,
411 				0x00007F00, ptr->n << 8);
412 
413 		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
414 		clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
415 
416 		/* SSI */
417 		clrsetbits_le32(&prcm_base->clksel_core,
418 				0x00000F00, CORE_SSI_DIV << 8);
419 		/* FSUSB */
420 		clrsetbits_le32(&prcm_base->clksel_core,
421 				0x00000030, CORE_FUSB_DIV << 4);
422 		/* L4 */
423 		clrsetbits_le32(&prcm_base->clksel_core,
424 				0x0000000C, CORE_L4_DIV << 2);
425 		/* L3 */
426 		clrsetbits_le32(&prcm_base->clksel_core,
427 				0x00000003, CORE_L3_DIV);
428 		/* GFX */
429 		clrsetbits_le32(&prcm_base->clksel_gfx,
430 				0x00000007, GFX_DIV_36X);
431 		/* RESET MGR */
432 		clrsetbits_le32(&prcm_base->clksel_wkup,
433 				0x00000006, WKUP_RSM << 1);
434 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
435 		clrsetbits_le32(&prcm_base->clken_pll,
436 				0x000000F0, ptr->fsel << 4);
437 		/* LOCK MODE */
438 		clrsetbits_le32(&prcm_base->clken_pll,
439 				0x00000007, PLL_LOCK);
440 
441 		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
442 				LDELAY);
443 	} else if (is_running_in_flash()) {
444 		/*
445 		 * if running from flash, jump to small relocated code
446 		 * area in SRAM.
447 		 */
448 		f_lock_pll = (void *) (SRAM_CLK_CODE);
449 
450 		p0 = readl(&prcm_base->clken_pll);
451 		clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
452 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
453 		clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
454 
455 		p1 = readl(&prcm_base->clksel1_pll);
456 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
457 		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
458 		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
459 		clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
460 		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
461 		clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
462 		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
463 		clrbits_le32(&p1, 0x00000040);
464 
465 		p2 = readl(&prcm_base->clksel_core);
466 		/* SSI */
467 		clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
468 		/* FSUSB */
469 		clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
470 		/* L4 */
471 		clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
472 		/* L3 */
473 		clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
474 
475 		p3 = (u32)&prcm_base->idlest_ckgen;
476 
477 		(*f_lock_pll) (p0, p1, p2, p3);
478 	}
479 }
480 
481 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
482 {
483 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
484 	struct dpll_per_36x_param *ptr;
485 
486 	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
487 
488 	/* Moving it to the right sysclk base */
489 	ptr += clk_index;
490 
491 	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
492 	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
493 	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
494 
495 	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
496 	clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
497 
498 	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
499 	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
500 
501 	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
502 	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
503 
504 	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
505 	clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
506 
507 	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
508 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
509 
510 	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
511 	clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
512 
513 	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
514 	clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
515 
516 	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
517 	clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
518 
519 	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
520 	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
521 	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
522 }
523 
524 static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
525 {
526 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
527 	dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
528 
529 	/* Moving it to the right sysclk base */
530 	ptr = ptr + clk_index;
531 
532 	/* PER2 DPLL (DPLL5) */
533 	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
534 	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
535 	/* set M2 (usbtll_fck) */
536 	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
537 	/* set m (11-bit multiplier) */
538 	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
539 	/* set n (7-bit divider)*/
540 	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
541 	/* lock mode */
542 	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
543 	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
544 }
545 
546 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
547 {
548 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
549 	dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
550 
551 	/* Moving to the right sysclk */
552 	ptr += clk_index;
553 
554 	/* MPU DPLL (unlocked already */
555 
556 	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
557 	clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
558 
559 	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
560 	clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
561 
562 	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
563 	clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
564 }
565 
566 static void iva_init_36xx(u32 sil_index, u32 clk_index)
567 {
568 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
569 	dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
570 
571 	/* Moving to the right sysclk */
572 	ptr += clk_index;
573 
574 	/* IVA DPLL */
575 	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
576 	clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
577 	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
578 
579 	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
580 	clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
581 
582 	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
583 	clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
584 
585 	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
586 	clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
587 
588 	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
589 	clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
590 
591 	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
592 }
593 
594 /******************************************************************************
595  * prcm_init() - inits clocks for PRCM as defined in clocks.h
596  *               called from SRAM, or Flash (using temp SRAM stack).
597  *****************************************************************************/
598 void prcm_init(void)
599 {
600 	u32 osc_clk = 0, sys_clkin_sel;
601 	u32 clk_index, sil_index = 0;
602 	struct prm *prm_base = (struct prm *)PRM_BASE;
603 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
604 
605 	/*
606 	 * Gauge the input clock speed and find out the sys_clkin_sel
607 	 * value corresponding to the input clock.
608 	 */
609 	osc_clk = get_osc_clk_speed();
610 	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
611 
612 	/* set input crystal speed */
613 	clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
614 
615 	/* If the input clock is greater than 19.2M always divide/2 */
616 	if (sys_clkin_sel > 2) {
617 		/* input clock divider */
618 		clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
619 		clk_index = sys_clkin_sel / 2;
620 	} else {
621 		/* input clock divider */
622 		clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
623 		clk_index = sys_clkin_sel;
624 	}
625 
626 	if (get_cpu_family() == CPU_OMAP36XX) {
627 		/*
628 		 * In warm reset conditions on OMAP36xx/AM/DM37xx
629 		 * the rom code incorrectly sets the DPLL4 clock
630 		 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
631 		 * the AM/DM37x TRM explains that the /6.5 divider
632 		 * is used only when the input clock is 13MHz.
633 		 *
634 		 * If the part is in this cpu family *and* the input
635 		 * clock *is not* 13 MHz, then reset the DPLL4 clock
636 		 * input divider to /1 as it should never set to /6.5
637 		 * in this case.
638 		 */
639 		if (sys_clkin_sel != 1) {	/* 13 MHz */
640 			/* Bit 8: DPLL4_CLKINP_DIV */
641 			clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
642 		}
643 
644 		/* Unlock MPU DPLL (slows things down, and needed later) */
645 		clrsetbits_le32(&prcm_base->clken_pll_mpu,
646 				0x00000007, PLL_LOW_POWER_BYPASS);
647 		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
648 				LDELAY);
649 
650 		dpll3_init_36xx(0, clk_index);
651 		dpll4_init_36xx(0, clk_index);
652 		dpll5_init_36xx(0, clk_index);
653 		iva_init_36xx(0, clk_index);
654 		mpu_init_36xx(0, clk_index);
655 
656 		/* Lock MPU DPLL to set frequency */
657 		clrsetbits_le32(&prcm_base->clken_pll_mpu,
658 				0x00000007, PLL_LOCK);
659 		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
660 				LDELAY);
661 	} else {
662 		/*
663 		 * The DPLL tables are defined according to sysclk value and
664 		 * silicon revision. The clk_index value will be used to get
665 		 * the values for that input sysclk from the DPLL param table
666 		 * and sil_index will get the values for that SysClk for the
667 		 * appropriate silicon rev.
668 		 */
669 		if (((get_cpu_family() == CPU_OMAP34XX)
670 				&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
671 			(get_cpu_family() == CPU_AM35XX))
672 			sil_index = 1;
673 
674 		/* Unlock MPU DPLL (slows things down, and needed later) */
675 		clrsetbits_le32(&prcm_base->clken_pll_mpu,
676 				0x00000007, PLL_LOW_POWER_BYPASS);
677 		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
678 				LDELAY);
679 
680 		dpll3_init_34xx(sil_index, clk_index);
681 		dpll4_init_34xx(sil_index, clk_index);
682 		dpll5_init_34xx(sil_index, clk_index);
683 		if (get_cpu_family() != CPU_AM35XX)
684 			iva_init_34xx(sil_index, clk_index);
685 
686 		mpu_init_34xx(sil_index, clk_index);
687 
688 		/* Lock MPU DPLL to set frequency */
689 		clrsetbits_le32(&prcm_base->clken_pll_mpu,
690 				0x00000007, PLL_LOCK);
691 		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
692 				LDELAY);
693 	}
694 
695 	/* Set up GPTimers to sys_clk source only */
696 	setbits_le32(&prcm_base->clksel_per, 0x000000FF);
697 	setbits_le32(&prcm_base->clksel_wkup, 1);
698 
699 	sdelay(5000);
700 }
701 
702 /*
703  * Enable usb ehci uhh, tll clocks
704  */
705 void ehci_clocks_enable(void)
706 {
707 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
708 
709 	/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
710 	setbits_le32(&prcm_base->iclken_usbhost, 1);
711 	/*
712 	 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
713 	 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
714 	 */
715 	setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
716 	/* Enable USBTTL_ICLK */
717 	setbits_le32(&prcm_base->iclken3_core, 0x00000004);
718 	/* Enable USBTTL_FCLK */
719 	setbits_le32(&prcm_base->fclken3_core, 0x00000004);
720 }
721 
722 /******************************************************************************
723  * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
724  *****************************************************************************/
725 void per_clocks_enable(void)
726 {
727 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
728 
729 	/* Enable GP2 timer. */
730 	setbits_le32(&prcm_base->clksel_per, 0x01);	/* GPT2 = sys clk */
731 	setbits_le32(&prcm_base->iclken_per, 0x08);	/* ICKen GPT2 */
732 	setbits_le32(&prcm_base->fclken_per, 0x08);	/* FCKen GPT2 */
733 
734 	/* Enable GP9 timer. */
735 	setbits_le32(&prcm_base->clksel_per, 0x80);	/* GPT9 = 32kHz clk */
736 	setbits_le32(&prcm_base->iclken_per, 0x400);	/* ICKen GPT9 */
737 	setbits_le32(&prcm_base->fclken_per, 0x400);	/* FCKen GPT9 */
738 
739 #ifdef CONFIG_SYS_NS16550
740 	/* Enable UART1 clocks */
741 	setbits_le32(&prcm_base->fclken1_core, 0x00002000);
742 	setbits_le32(&prcm_base->iclken1_core, 0x00002000);
743 
744 	/* Enable UART2 clocks */
745 	setbits_le32(&prcm_base->fclken1_core, 0x00004000);
746 	setbits_le32(&prcm_base->iclken1_core, 0x00004000);
747 
748 	/* UART 3 Clocks */
749 	setbits_le32(&prcm_base->fclken_per, 0x00000800);
750 	setbits_le32(&prcm_base->iclken_per, 0x00000800);
751 #endif
752 
753 #if defined(CONFIG_OMAP3_GPIO_2)
754 	setbits_le32(&prcm_base->fclken_per, 0x00002000);
755 	setbits_le32(&prcm_base->iclken_per, 0x00002000);
756 #endif
757 #if defined(CONFIG_OMAP3_GPIO_3)
758 	setbits_le32(&prcm_base->fclken_per, 0x00004000);
759 	setbits_le32(&prcm_base->iclken_per, 0x00004000);
760 #endif
761 #if defined(CONFIG_OMAP3_GPIO_4)
762 	setbits_le32(&prcm_base->fclken_per, 0x00008000);
763 	setbits_le32(&prcm_base->iclken_per, 0x00008000);
764 #endif
765 #if defined(CONFIG_OMAP3_GPIO_5)
766 	setbits_le32(&prcm_base->fclken_per, 0x00010000);
767 	setbits_le32(&prcm_base->iclken_per, 0x00010000);
768 #endif
769 #if defined(CONFIG_OMAP3_GPIO_6)
770 	setbits_le32(&prcm_base->fclken_per, 0x00020000);
771 	setbits_le32(&prcm_base->iclken_per, 0x00020000);
772 #endif
773 
774 #ifdef CONFIG_SYS_I2C_OMAP24XX
775 	/* Turn on all 3 I2C clocks */
776 	setbits_le32(&prcm_base->fclken1_core, 0x00038000);
777 	setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
778 #endif
779 	/* Enable the ICLK for 32K Sync Timer as its used in udelay */
780 	setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
781 
782 	if (get_cpu_family() != CPU_AM35XX)
783 		out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
784 
785 	out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
786 	out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
787 	out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
788 	out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
789 	out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
790 	out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
791 	out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
792 	if (get_cpu_family() != CPU_AM35XX) {
793 		out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
794 		out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
795 	}
796 
797 	sdelay(1000);
798 }
799