1 /* 2 * 3 * Common board functions for OMAP3 based boards. 4 * 5 * (C) Copyright 2004-2008 6 * Texas Instruments, <www.ti.com> 7 * 8 * Author : 9 * Sunil Kumar <sunilsaini05@gmail.com> 10 * Shashi Ranjan <shashiranjanmca05@gmail.com> 11 * 12 * Derived from Beagle Board and 3430 SDP code by 13 * Richard Woodruff <r-woodruff2@ti.com> 14 * Syed Mohammed Khasim <khasim@ti.com> 15 * 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 #include <common.h> 20 #include <dm.h> 21 #include <spl.h> 22 #include <asm/io.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/cache.h> 26 #include <asm/armv7.h> 27 #include <asm/gpio.h> 28 #include <asm/omap_common.h> 29 #include <linux/compiler.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* Declarations */ 34 extern omap3_sysinfo sysinfo; 35 #ifndef CONFIG_SYS_L2CACHE_OFF 36 static void omap3_invalidate_l2_cache_secure(void); 37 #endif 38 39 #ifdef CONFIG_DM_GPIO 40 static const struct omap_gpio_platdata omap34xx_gpio[] = { 41 { 0, OMAP34XX_GPIO1_BASE }, 42 { 1, OMAP34XX_GPIO2_BASE }, 43 { 2, OMAP34XX_GPIO3_BASE }, 44 { 3, OMAP34XX_GPIO4_BASE }, 45 { 4, OMAP34XX_GPIO5_BASE }, 46 { 5, OMAP34XX_GPIO6_BASE }, 47 }; 48 49 U_BOOT_DEVICES(omap34xx_gpios) = { 50 { "gpio_omap", &omap34xx_gpio[0] }, 51 { "gpio_omap", &omap34xx_gpio[1] }, 52 { "gpio_omap", &omap34xx_gpio[2] }, 53 { "gpio_omap", &omap34xx_gpio[3] }, 54 { "gpio_omap", &omap34xx_gpio[4] }, 55 { "gpio_omap", &omap34xx_gpio[5] }, 56 }; 57 58 #else 59 60 static const struct gpio_bank gpio_bank_34xx[6] = { 61 { (void *)OMAP34XX_GPIO1_BASE }, 62 { (void *)OMAP34XX_GPIO2_BASE }, 63 { (void *)OMAP34XX_GPIO3_BASE }, 64 { (void *)OMAP34XX_GPIO4_BASE }, 65 { (void *)OMAP34XX_GPIO5_BASE }, 66 { (void *)OMAP34XX_GPIO6_BASE }, 67 }; 68 69 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; 70 71 #endif 72 73 /****************************************************************************** 74 * Routine: secure_unlock 75 * Description: Setup security registers for access 76 * (GP Device only) 77 *****************************************************************************/ 78 void secure_unlock_mem(void) 79 { 80 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; 81 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; 82 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; 83 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; 84 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; 85 86 /* Protection Module Register Target APE (PM_RT) */ 87 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); 88 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); 89 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); 90 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); 91 92 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); 93 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); 94 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); 95 96 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); 97 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); 98 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); 99 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); 100 101 /* IVA Changes */ 102 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); 103 writel(UNLOCK_3, &pm_iva2_base->read_permission_0); 104 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); 105 106 /* SDRC region 0 public */ 107 writel(UNLOCK_1, &sms_base->rg_att0); 108 } 109 110 /****************************************************************************** 111 * Routine: secureworld_exit() 112 * Description: If chip is EMU and boot type is external 113 * configure secure registers and exit secure world 114 * general use. 115 *****************************************************************************/ 116 void secureworld_exit(void) 117 { 118 unsigned long i; 119 120 /* configure non-secure access control register */ 121 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); 122 /* enabling co-processor CP10 and CP11 accesses in NS world */ 123 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); 124 /* 125 * allow allocation of locked TLBs and L2 lines in NS world 126 * allow use of PLE registers in NS world also 127 */ 128 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); 129 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); 130 131 /* Enable ASA in ACR register */ 132 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); 133 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); 134 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); 135 136 /* Exiting secure world */ 137 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); 138 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); 139 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); 140 } 141 142 /****************************************************************************** 143 * Routine: try_unlock_sram() 144 * Description: If chip is GP/EMU(special) type, unlock the SRAM for 145 * general use. 146 *****************************************************************************/ 147 void try_unlock_memory(void) 148 { 149 int mode; 150 int in_sdram = is_running_in_sdram(); 151 152 /* 153 * if GP device unlock device SRAM for general use 154 * secure code breaks for Secure/Emulation device - HS/E/T 155 */ 156 mode = get_device_type(); 157 if (mode == GP_DEVICE) 158 secure_unlock_mem(); 159 160 /* 161 * If device is EMU and boot is XIP external booting 162 * Unlock firewalls and disable L2 and put chip 163 * out of secure world 164 * 165 * Assuming memories are unlocked by the demon who put us in SDRAM 166 */ 167 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) 168 && (!in_sdram)) { 169 secure_unlock_mem(); 170 secureworld_exit(); 171 } 172 173 return; 174 } 175 176 /****************************************************************************** 177 * Routine: s_init 178 * Description: Does early system init of muxing and clocks. 179 * - Called path is with SRAM stack. 180 *****************************************************************************/ 181 void s_init(void) 182 { 183 watchdog_init(); 184 185 try_unlock_memory(); 186 187 #ifndef CONFIG_SYS_L2CACHE_OFF 188 /* Invalidate L2-cache from secure mode */ 189 omap3_invalidate_l2_cache_secure(); 190 #endif 191 192 set_muxconf_regs(); 193 sdelay(100); 194 195 prcm_init(); 196 197 per_clocks_enable(); 198 199 #ifdef CONFIG_USB_EHCI_OMAP 200 ehci_clocks_enable(); 201 #endif 202 } 203 204 #ifdef CONFIG_SPL_BUILD 205 void board_init_f(ulong dummy) 206 { 207 mem_init(); 208 } 209 #endif 210 211 /* 212 * Routine: misc_init_r 213 * Description: A basic misc_init_r that just displays the die ID 214 */ 215 int __weak misc_init_r(void) 216 { 217 omap_die_id_display(); 218 219 return 0; 220 } 221 222 /****************************************************************************** 223 * Routine: wait_for_command_complete 224 * Description: Wait for posting to finish on watchdog 225 *****************************************************************************/ 226 static void wait_for_command_complete(struct watchdog *wd_base) 227 { 228 int pending = 1; 229 do { 230 pending = readl(&wd_base->wwps); 231 } while (pending); 232 } 233 234 /****************************************************************************** 235 * Routine: watchdog_init 236 * Description: Shut down watch dogs 237 *****************************************************************************/ 238 void watchdog_init(void) 239 { 240 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; 241 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 242 243 /* 244 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is 245 * either taken care of by ROM (HS/EMU) or not accessible (GP). 246 * We need to take care of WD2-MPU or take a PRCM reset. WD3 247 * should not be running and does not generate a PRCM reset. 248 */ 249 250 setbits_le32(&prcm_base->fclken_wkup, 0x20); 251 setbits_le32(&prcm_base->iclken_wkup, 0x20); 252 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); 253 254 writel(WD_UNLOCK1, &wd2_base->wspr); 255 wait_for_command_complete(wd2_base); 256 writel(WD_UNLOCK2, &wd2_base->wspr); 257 } 258 259 /****************************************************************************** 260 * Dummy function to handle errors for EABI incompatibility 261 *****************************************************************************/ 262 void abort(void) 263 { 264 } 265 266 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) 267 /****************************************************************************** 268 * OMAP3 specific command to switch between NAND HW and SW ecc 269 *****************************************************************************/ 270 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 271 { 272 int hw, strength = 1; 273 274 if (argc < 2 || argc > 3) 275 goto usage; 276 277 if (strncmp(argv[1], "hw", 2) == 0) { 278 hw = 1; 279 if (argc == 3) { 280 if (strncmp(argv[2], "bch8", 4) == 0) 281 strength = 8; 282 else if (strncmp(argv[2], "bch16", 5) == 0) 283 strength = 16; 284 else if (strncmp(argv[2], "hamming", 7) != 0) 285 goto usage; 286 } 287 } else if (strncmp(argv[1], "sw", 2) == 0) { 288 hw = 0; 289 if (argc == 3) { 290 if (strncmp(argv[2], "bch8", 4) == 0) 291 strength = 8; 292 else if (strncmp(argv[2], "hamming", 7) != 0) 293 goto usage; 294 } 295 } else { 296 goto usage; 297 } 298 299 return -omap_nand_switch_ecc(hw, strength); 300 301 usage: 302 printf ("Usage: nandecc %s\n", cmdtp->usage); 303 return 1; 304 } 305 306 U_BOOT_CMD( 307 nandecc, 3, 1, do_switch_ecc, 308 "switch OMAP3 NAND ECC calculation algorithm", 309 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming" 310 " and 8-bit/16-bit BCH\n" 311 " ecc calculation (second parameter may" 312 " be omitted).\n" 313 "nandecc sw - Switch to NAND software ecc algorithm." 314 ); 315 316 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ 317 318 #ifdef CONFIG_DISPLAY_BOARDINFO 319 /** 320 * Print board information 321 */ 322 int checkboard (void) 323 { 324 char *mem_s ; 325 326 if (is_mem_sdr()) 327 mem_s = "mSDR"; 328 else 329 mem_s = "LPDDR"; 330 331 printf("%s + %s/%s\n", sysinfo.board_string, mem_s, 332 sysinfo.nand_string); 333 334 return 0; 335 } 336 #endif /* CONFIG_DISPLAY_BOARDINFO */ 337 338 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) 339 { 340 u32 i, num_params = *parameters; 341 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; 342 343 /* 344 * copy the parameters to an un-cached area to avoid coherency 345 * issues 346 */ 347 for (i = 0; i < num_params; i++) { 348 __raw_writel(*parameters, sram_scratch_space); 349 parameters++; 350 sram_scratch_space++; 351 } 352 353 /* Now make the PPA call */ 354 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); 355 } 356 357 void __weak omap3_set_aux_cr_secure(u32 acr) 358 { 359 struct emu_hal_params emu_romcode_params; 360 361 emu_romcode_params.num_params = 1; 362 emu_romcode_params.param1 = acr; 363 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, 364 (u32 *)&emu_romcode_params); 365 } 366 367 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, 368 u32 cpu_rev_comb, u32 cpu_variant, 369 u32 cpu_rev) 370 { 371 if (get_device_type() == GP_DEVICE) 372 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl); 373 374 /* L2 Cache Auxiliary Control Register is not banked */ 375 } 376 377 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, 378 u32 cpu_variant, u32 cpu_rev) 379 { 380 /* Write ACR - affects secure banked bits */ 381 if (get_device_type() == GP_DEVICE) 382 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); 383 else 384 omap3_set_aux_cr_secure(acr); 385 386 /* Write ACR - affects non-secure banked bits - some erratas need it */ 387 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); 388 } 389 390 391 #ifndef CONFIG_SYS_L2CACHE_OFF 392 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) 393 { 394 u32 acr; 395 396 /* Read ACR */ 397 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 398 acr &= ~clear_bits; 399 acr |= set_bits; 400 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); 401 402 } 403 404 /* Invalidate the entire L2 cache from secure mode */ 405 static void omap3_invalidate_l2_cache_secure(void) 406 { 407 if (get_device_type() == GP_DEVICE) { 408 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); 409 } else { 410 struct emu_hal_params emu_romcode_params; 411 emu_romcode_params.num_params = 1; 412 emu_romcode_params.param1 = 0; 413 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, 414 (u32 *)&emu_romcode_params); 415 } 416 } 417 418 void v7_outer_cache_enable(void) 419 { 420 421 /* 422 * Set L2EN 423 * On some revisions L2EN bit is banked on some revisions it's not 424 * No harm in setting both banked bits(in fact this is required 425 * by an erratum) 426 */ 427 omap3_update_aux_cr(0x2, 0); 428 } 429 430 void omap3_outer_cache_disable(void) 431 { 432 /* 433 * Clear L2EN 434 * On some revisions L2EN bit is banked on some revisions it's not 435 * No harm in clearing both banked bits(in fact this is required 436 * by an erratum) 437 */ 438 omap3_update_aux_cr(0, 0x2); 439 } 440 #endif /* !CONFIG_SYS_L2CACHE_OFF */ 441