1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * This file configures the internal USB PHY in AM35X.
4  *
5  * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
6  *
7  * Based on omap_phy_internal.c code from Linux by
8  * Hema HK <hemahk@ti.com>
9  */
10 
11 #include <common.h>
12 #include <asm/io.h>
13 #include <asm/arch/am35x_def.h>
14 
15 void am35x_musb_reset(struct udevice *dev)
16 {
17 	/* Reset the musb interface */
18 	clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
19 			0, USBOTGSS_SW_RST);
20 	clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
21 			USBOTGSS_SW_RST, 0);
22 }
23 
24 void am35x_musb_phy_power(struct udevice *dev, u8 on)
25 {
26 	unsigned long start = get_timer(0);
27 
28 	if (on) {
29 		/*
30 		 * Start the on-chip PHY and its PLL.
31 		 */
32 		clrsetbits_le32(&am35x_scm_general_regs->devconf2,
33 				CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
34 				CONF2_PHY_PLLON);
35 
36 		debug("Waiting for PHY clock good...\n");
37 		while (!(readl(&am35x_scm_general_regs->devconf2)
38 				& CONF2_PHYCLKGD)) {
39 
40 			if (get_timer(start) > CONFIG_SYS_HZ / 10) {
41 				printf("musb PHY clock good timed out\n");
42 				break;
43 			}
44 		}
45 	} else {
46 		/*
47 		 * Power down the on-chip PHY.
48 		 */
49 		clrsetbits_le32(&am35x_scm_general_regs->devconf2,
50 				CONF2_PHY_PLLON,
51 				CONF2_PHYPWRDN | CONF2_OTGPWRDN);
52 	}
53 }
54 
55 void am35x_musb_clear_irq(struct udevice *dev)
56 {
57 	clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
58 			0, USBOTGSS_INT_CLR);
59 	readl(&am35x_scm_general_regs->lvl_intr_clr);
60 }
61