1983e3700STom Rini /* 2983e3700STom Rini * This file configures the internal USB PHY in AM35X. 3983e3700STom Rini * 4983e3700STom Rini * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com> 5983e3700STom Rini * 6983e3700STom Rini * Based on omap_phy_internal.c code from Linux by 7983e3700STom Rini * Hema HK <hemahk@ti.com> 8983e3700STom Rini * 9983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+ 10983e3700STom Rini */ 11983e3700STom Rini 12983e3700STom Rini #include <common.h> 13983e3700STom Rini #include <asm/io.h> 14983e3700STom Rini #include <asm/arch/am35x_def.h> 15983e3700STom Rini 16*1cac34ceSMugunthan V N void am35x_musb_reset(struct udevice *dev) 17983e3700STom Rini { 18983e3700STom Rini /* Reset the musb interface */ 19983e3700STom Rini clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, 20983e3700STom Rini 0, USBOTGSS_SW_RST); 21983e3700STom Rini clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, 22983e3700STom Rini USBOTGSS_SW_RST, 0); 23983e3700STom Rini } 24983e3700STom Rini 25*1cac34ceSMugunthan V N void am35x_musb_phy_power(struct udevice *dev, u8 on) 26983e3700STom Rini { 27983e3700STom Rini unsigned long start = get_timer(0); 28983e3700STom Rini 29983e3700STom Rini if (on) { 30983e3700STom Rini /* 31983e3700STom Rini * Start the on-chip PHY and its PLL. 32983e3700STom Rini */ 33983e3700STom Rini clrsetbits_le32(&am35x_scm_general_regs->devconf2, 34983e3700STom Rini CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, 35983e3700STom Rini CONF2_PHY_PLLON); 36983e3700STom Rini 37983e3700STom Rini debug("Waiting for PHY clock good...\n"); 38983e3700STom Rini while (!(readl(&am35x_scm_general_regs->devconf2) 39983e3700STom Rini & CONF2_PHYCLKGD)) { 40983e3700STom Rini 41983e3700STom Rini if (get_timer(start) > CONFIG_SYS_HZ / 10) { 42983e3700STom Rini printf("musb PHY clock good timed out\n"); 43983e3700STom Rini break; 44983e3700STom Rini } 45983e3700STom Rini } 46983e3700STom Rini } else { 47983e3700STom Rini /* 48983e3700STom Rini * Power down the on-chip PHY. 49983e3700STom Rini */ 50983e3700STom Rini clrsetbits_le32(&am35x_scm_general_regs->devconf2, 51983e3700STom Rini CONF2_PHY_PLLON, 52983e3700STom Rini CONF2_PHYPWRDN | CONF2_OTGPWRDN); 53983e3700STom Rini } 54983e3700STom Rini } 55983e3700STom Rini 56*1cac34ceSMugunthan V N void am35x_musb_clear_irq(struct udevice *dev) 57983e3700STom Rini { 58983e3700STom Rini clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, 59983e3700STom Rini 0, USBOTGSS_INT_CLR); 60983e3700STom Rini readl(&am35x_scm_general_regs->lvl_intr_clr); 61983e3700STom Rini } 62