1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Board specific setup info
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 *	Aneesh V	<aneesh@ti.com>
10 */
11
12#include <config.h>
13#include <asm/arch/omap.h>
14#include <asm/omap_common.h>
15#include <asm/arch/spl.h>
16#include <linux/linkage.h>
17
18.arch_extension sec
19
20#ifdef CONFIG_SPL
21ENTRY(save_boot_params)
22	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
23	str	r0, [r1]
24	b	save_boot_params_ret
25ENDPROC(save_boot_params)
26
27#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
28ENTRY(switch_to_hypervisor)
29
30/*
31 * Switch to hypervisor mode
32 */
33	adr	r0, save_sp
34	str	sp, [r0]
35	adr	r1, restore_from_hyp
36	ldr	r0, =0x102
37	b	omap_smc1
38restore_from_hyp:
39	adr	r0, save_sp
40	ldr	sp, [r0]
41	MRC p15, 4, R0, c1, c0, 0
42	ldr     r1, =0X1004	@Set cache enable bits for hypervisor mode
43	orr     r0, r0, r1
44	MCR p15, 4, R0, c1, c0, 0
45	b	switch_to_hypervisor_ret
46save_sp:
47	.word	0x0
48ENDPROC(switch_to_hypervisor)
49#endif
50#endif
51
52ENTRY(omap_smc1)
53	push	{r4-r12, lr}	@ save registers - ROM code may pollute
54				@ our registers
55	mov	r12, r0		@ Service
56	mov	r0, r1		@ Argument
57
58	dsb
59	dmb
60	smc	0		@ SMC #0 to enter monitor mode
61				@ call ROM Code API for the service requested
62	pop	{r4-r12, pc}
63ENDPROC(omap_smc1)
64
65ENTRY(omap_smc_sec)
66	push	{r4-r12, lr}	@ save registers - ROM code may pollute
67				@ our registers
68	mov	r6, #0xFF	@ Indicate new Task call
69	mov	r12, #0x00	@ Secure Service ID in R12
70
71	dsb
72	dmb
73	smc	0		@ SMC #0 to enter monitor mode
74
75	b	omap_smc_sec_end @ exit at end of the service execution
76	nop
77
78	@ In case of IRQ happening in Secure, then ARM will branch here.
79	@ At that moment, IRQ will be pending and ARM will jump to Non Secure
80	@ IRQ handler
81	mov	r12, #0xFE
82
83	dsb
84	dmb
85	smc	0		@ SMC #0 to enter monitor mode
86
87omap_smc_sec_end:
88	pop	{r4-r12, pc}
89ENDPROC(omap_smc_sec)
90