1 /* 2 * EMIF programming 3 * 4 * (C) Copyright 2010 5 * Texas Instruments, <www.ti.com> 6 * 7 * Aneesh V <aneesh@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/emif.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/omap_sec_common.h> 18 #include <asm/utils.h> 19 #include <linux/compiler.h> 20 21 static int emif1_enabled = -1, emif2_enabled = -1; 22 23 void set_lpmode_selfrefresh(u32 base) 24 { 25 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 26 u32 reg; 27 28 reg = readl(&emif->emif_pwr_mgmt_ctrl); 29 reg &= ~EMIF_REG_LP_MODE_MASK; 30 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; 31 reg &= ~EMIF_REG_SR_TIM_MASK; 32 writel(reg, &emif->emif_pwr_mgmt_ctrl); 33 34 /* dummy read for the new SR_TIM to be loaded */ 35 readl(&emif->emif_pwr_mgmt_ctrl); 36 } 37 38 void force_emif_self_refresh() 39 { 40 set_lpmode_selfrefresh(EMIF1_BASE); 41 if (!is_dra72x()) 42 set_lpmode_selfrefresh(EMIF2_BASE); 43 } 44 45 inline u32 emif_num(u32 base) 46 { 47 if (base == EMIF1_BASE) 48 return 1; 49 else if (base == EMIF2_BASE) 50 return 2; 51 else 52 return 0; 53 } 54 55 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) 56 { 57 u32 mr; 58 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 59 60 mr_addr |= cs << EMIF_REG_CS_SHIFT; 61 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); 62 if (omap_revision() == OMAP4430_ES2_0) 63 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); 64 else 65 mr = readl(&emif->emif_lpddr2_mode_reg_data); 66 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), 67 cs, mr_addr, mr); 68 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && 69 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && 70 ((mr & 0xff000000) >> 24) == (mr & 0xff)) 71 return mr & 0xff; 72 else 73 return mr; 74 } 75 76 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) 77 { 78 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 79 80 mr_addr |= cs << EMIF_REG_CS_SHIFT; 81 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); 82 writel(mr_val, &emif->emif_lpddr2_mode_reg_data); 83 } 84 85 void emif_reset_phy(u32 base) 86 { 87 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 88 u32 iodft; 89 90 iodft = readl(&emif->emif_iodft_tlgc); 91 iodft |= EMIF_REG_RESET_PHY_MASK; 92 writel(iodft, &emif->emif_iodft_tlgc); 93 } 94 95 static void do_lpddr2_init(u32 base, u32 cs) 96 { 97 u32 mr_addr; 98 const struct lpddr2_mr_regs *mr_regs; 99 100 get_lpddr2_mr_regs(&mr_regs); 101 /* Wait till device auto initialization is complete */ 102 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) 103 ; 104 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); 105 /* 106 * tZQINIT = 1 us 107 * Enough loops assuming a maximum of 2GHz 108 */ 109 110 sdelay(2000); 111 112 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); 113 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); 114 115 /* 116 * Enable refresh along with writing MR2 117 * Encoding of RL in MR2 is (RL - 2) 118 */ 119 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; 120 set_mr(base, cs, mr_addr, mr_regs->mr2); 121 122 if (mr_regs->mr3 > 0) 123 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); 124 } 125 126 static void lpddr2_init(u32 base, const struct emif_regs *regs) 127 { 128 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 129 130 /* Not NVM */ 131 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); 132 133 /* 134 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM 135 * when EMIF_SDRAM_CONFIG register is written 136 */ 137 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 138 139 /* 140 * Set the SDRAM_CONFIG and PHY_CTRL for the 141 * un-locked frequency & default RL 142 */ 143 writel(regs->sdram_config_init, &emif->emif_sdram_config); 144 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 145 146 do_ext_phy_settings(base, regs); 147 148 do_lpddr2_init(base, CS0); 149 if (regs->sdram_config & EMIF_REG_EBANK_MASK) 150 do_lpddr2_init(base, CS1); 151 152 writel(regs->sdram_config, &emif->emif_sdram_config); 153 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); 154 155 /* Enable refresh now */ 156 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 157 158 } 159 160 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) 161 { 162 } 163 164 void emif_update_timings(u32 base, const struct emif_regs *regs) 165 { 166 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 167 168 if (!is_dra7xx()) 169 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); 170 else 171 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); 172 173 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); 174 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); 175 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); 176 if (omap_revision() == OMAP4430_ES1_0) { 177 /* ES1 bug EMIF should be in force idle during freq_update */ 178 writel(0, &emif->emif_pwr_mgmt_ctrl); 179 } else { 180 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); 181 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); 182 } 183 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); 184 writel(regs->zq_config, &emif->emif_zq_config); 185 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); 186 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); 187 188 if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { 189 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, 190 &emif->emif_l3_config); 191 } else if (omap_revision() >= OMAP4460_ES1_0) { 192 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, 193 &emif->emif_l3_config); 194 } else { 195 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, 196 &emif->emif_l3_config); 197 } 198 } 199 200 #ifndef CONFIG_OMAP44XX 201 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) 202 { 203 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 204 205 /* keep sdram in self-refresh */ 206 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) 207 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); 208 __udelay(130); 209 210 /* 211 * Set invert_clkout (if activated)--DDR_PHYCTRL_1 212 * Invert clock adds an additional half cycle delay on the 213 * command interface. The additional half cycle, is usually 214 * meant to enable leveling in the situation that DQS is later 215 * than CK on the board.It also helps provide some additional 216 * margin for leveling. 217 */ 218 writel(regs->emif_ddr_phy_ctlr_1, 219 &emif->emif_ddr_phy_ctrl_1); 220 221 writel(regs->emif_ddr_phy_ctlr_1, 222 &emif->emif_ddr_phy_ctrl_1_shdw); 223 __udelay(130); 224 225 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) 226 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); 227 228 /* Launch Full leveling */ 229 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); 230 231 /* Wait till full leveling is complete */ 232 readl(&emif->emif_rd_wr_lvl_ctl); 233 __udelay(130); 234 235 /* Read data eye leveling no of samples */ 236 config_data_eye_leveling_samples(base); 237 238 /* 239 * Launch 8 incremental WR_LVL- to compensate for 240 * PHY limitation. 241 */ 242 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, 243 &emif->emif_rd_wr_lvl_ctl); 244 245 __udelay(130); 246 247 /* Launch Incremental leveling */ 248 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); 249 __udelay(130); 250 } 251 252 static void update_hwleveling_output(u32 base, const struct emif_regs *regs) 253 { 254 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 255 u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; 256 u32 reg, i, phy; 257 258 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; 259 phy = readl(&emif->emif_ddr_phy_ctrl_1); 260 261 /* Update PHY_REG_RDDQS_RATIO */ 262 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; 263 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) 264 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { 265 reg = readl(emif_phy_status++); 266 writel(reg, emif_ext_phy_ctrl_reg++); 267 writel(reg, emif_ext_phy_ctrl_reg++); 268 } 269 270 /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ 271 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; 272 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; 273 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) 274 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { 275 reg = readl(emif_phy_status++); 276 writel(reg, emif_ext_phy_ctrl_reg++); 277 writel(reg, emif_ext_phy_ctrl_reg++); 278 } 279 280 /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ 281 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; 282 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; 283 if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) 284 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { 285 reg = readl(emif_phy_status++); 286 writel(reg, emif_ext_phy_ctrl_reg++); 287 writel(reg, emif_ext_phy_ctrl_reg++); 288 } 289 290 /* Disable Leveling */ 291 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); 292 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); 293 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); 294 } 295 296 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) 297 { 298 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 299 300 /* Clear Error Status */ 301 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, 302 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, 303 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); 304 305 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, 306 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, 307 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); 308 309 /* Disable refreshed before leveling */ 310 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, 311 EMIF_REG_INITREF_DIS_MASK); 312 313 /* Start Full leveling */ 314 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); 315 316 __udelay(300); 317 318 /* Check for leveling timeout */ 319 if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { 320 printf("Leveling timeout on EMIF%d\n", emif_num(base)); 321 return; 322 } 323 324 /* Enable refreshes after leveling */ 325 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 326 327 debug("HW leveling success\n"); 328 /* 329 * Update slave ratios in EXT_PHY_CTRLx registers 330 * as per HW leveling output 331 */ 332 update_hwleveling_output(base, regs); 333 } 334 335 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) 336 { 337 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 338 339 if (warm_reset()) { 340 emif_reset_phy(base); 341 writel(0x0, &emif->emif_pwr_mgmt_ctrl); 342 } 343 do_ext_phy_settings(base, regs); 344 345 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, 346 &emif->emif_sdram_ref_ctrl); 347 /* Update timing registers */ 348 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); 349 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); 350 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); 351 352 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); 353 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); 354 writel(regs->zq_config, &emif->emif_zq_config); 355 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); 356 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); 357 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); 358 359 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 360 writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); 361 362 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); 363 364 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); 365 writel(regs->sdram_config_init, &emif->emif_sdram_config); 366 367 __udelay(1000); 368 369 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); 370 371 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) 372 dra7_ddr3_leveling(base, regs); 373 } 374 375 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) 376 { 377 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 378 379 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); 380 writel(regs->sdram_config_init, &emif->emif_sdram_config); 381 /* 382 * Set SDRAM_CONFIG and PHY control registers to locked frequency 383 * and RL =7. As the default values of the Mode Registers are not 384 * defined, contents of mode Registers must be fully initialized. 385 * H/W takes care of this initialization 386 */ 387 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 388 389 /* Update timing registers */ 390 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); 391 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); 392 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); 393 394 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); 395 396 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); 397 writel(regs->sdram_config_init, &emif->emif_sdram_config); 398 do_ext_phy_settings(base, regs); 399 400 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); 401 omap5_ddr3_leveling(base, regs); 402 } 403 404 static void ddr3_init(u32 base, const struct emif_regs *regs) 405 { 406 if (is_omap54xx()) 407 omap5_ddr3_init(base, regs); 408 else 409 dra7_ddr3_init(base, regs); 410 } 411 #endif 412 413 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 414 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) 415 416 /* 417 * Organization and refresh requirements for LPDDR2 devices of different 418 * types and densities. Derived from JESD209-2 section 2.4 419 */ 420 const struct lpddr2_addressing addressing_table[] = { 421 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ 422 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ 423 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ 424 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ 425 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ 426 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ 427 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ 428 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ 429 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ 430 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ 431 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ 432 }; 433 434 static const u32 lpddr2_density_2_size_in_mbytes[] = { 435 8, /* 64Mb */ 436 16, /* 128Mb */ 437 32, /* 256Mb */ 438 64, /* 512Mb */ 439 128, /* 1Gb */ 440 256, /* 2Gb */ 441 512, /* 4Gb */ 442 1024, /* 8Gb */ 443 2048, /* 16Gb */ 444 4096 /* 32Gb */ 445 }; 446 447 /* 448 * Calculate the period of DDR clock from frequency value and set the 449 * denominator and numerator in global variables for easy access later 450 */ 451 static void set_ddr_clk_period(u32 freq) 452 { 453 /* 454 * period = 1/freq 455 * period_in_ns = 10^9/freq 456 */ 457 *T_num = 1000000000; 458 *T_den = freq; 459 cancel_out(T_num, T_den, 200); 460 461 } 462 463 /* 464 * Convert time in nano seconds to number of cycles of DDR clock 465 */ 466 static inline u32 ns_2_cycles(u32 ns) 467 { 468 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); 469 } 470 471 /* 472 * ns_2_cycles with the difference that the time passed is 2 times the actual 473 * value(to avoid fractions). The cycles returned is for the original value of 474 * the timing parameter 475 */ 476 static inline u32 ns_x2_2_cycles(u32 ns) 477 { 478 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); 479 } 480 481 /* 482 * Find addressing table index based on the device's type(S2 or S4) and 483 * density 484 */ 485 s8 addressing_table_index(u8 type, u8 density, u8 width) 486 { 487 u8 index; 488 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) 489 return -1; 490 491 /* 492 * Look at the way ADDR_TABLE_INDEX* values have been defined 493 * in emif.h compared to LPDDR2_DENSITY_* values 494 * The table is layed out in the increasing order of density 495 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed 496 * at the end 497 */ 498 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) 499 index = ADDR_TABLE_INDEX1GS2; 500 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) 501 index = ADDR_TABLE_INDEX2GS2; 502 else 503 index = density; 504 505 debug("emif: addressing table index %d\n", index); 506 507 return index; 508 } 509 510 /* 511 * Find the the right timing table from the array of timing 512 * tables of the device using DDR clock frequency 513 */ 514 static const struct lpddr2_ac_timings *get_timings_table(const struct 515 lpddr2_ac_timings const *const *device_timings, 516 u32 freq) 517 { 518 u32 i, temp, freq_nearest; 519 const struct lpddr2_ac_timings *timings = 0; 520 521 emif_assert(freq <= MAX_LPDDR2_FREQ); 522 emif_assert(device_timings); 523 524 /* 525 * Start with the maximum allowed frequency - that is always safe 526 */ 527 freq_nearest = MAX_LPDDR2_FREQ; 528 /* 529 * Find the timings table that has the max frequency value: 530 * i. Above or equal to the DDR frequency - safe 531 * ii. The lowest that satisfies condition (i) - optimal 532 */ 533 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { 534 temp = device_timings[i]->max_freq; 535 if ((temp >= freq) && (temp <= freq_nearest)) { 536 freq_nearest = temp; 537 timings = device_timings[i]; 538 } 539 } 540 debug("emif: timings table: %d\n", freq_nearest); 541 return timings; 542 } 543 544 /* 545 * Finds the value of emif_sdram_config_reg 546 * All parameters are programmed based on the device on CS0. 547 * If there is a device on CS1, it will be same as that on CS0 or 548 * it will be NVM. We don't support NVM yet. 549 * If cs1_device pointer is NULL it is assumed that there is no device 550 * on CS1 551 */ 552 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, 553 const struct lpddr2_device_details *cs1_device, 554 const struct lpddr2_addressing *addressing, 555 u8 RL) 556 { 557 u32 config_reg = 0; 558 559 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; 560 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << 561 EMIF_REG_IBANK_POS_SHIFT; 562 563 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; 564 565 config_reg |= RL << EMIF_REG_CL_SHIFT; 566 567 config_reg |= addressing->row_sz[cs0_device->io_width] << 568 EMIF_REG_ROWSIZE_SHIFT; 569 570 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; 571 572 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << 573 EMIF_REG_EBANK_SHIFT; 574 575 config_reg |= addressing->col_sz[cs0_device->io_width] << 576 EMIF_REG_PAGESIZE_SHIFT; 577 578 return config_reg; 579 } 580 581 static u32 get_sdram_ref_ctrl(u32 freq, 582 const struct lpddr2_addressing *addressing) 583 { 584 u32 ref_ctrl = 0, val = 0, freq_khz; 585 freq_khz = freq / 1000; 586 /* 587 * refresh rate to be set is 'tREFI * freq in MHz 588 * division by 10000 to account for khz and x10 in t_REFI_us_x10 589 */ 590 val = addressing->t_REFI_us_x10 * freq_khz / 10000; 591 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; 592 593 return ref_ctrl; 594 } 595 596 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, 597 const struct lpddr2_min_tck *min_tck, 598 const struct lpddr2_addressing *addressing) 599 { 600 u32 tim1 = 0, val = 0; 601 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; 602 tim1 |= val << EMIF_REG_T_WTR_SHIFT; 603 604 if (addressing->num_banks == BANKS8) 605 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / 606 (4 * (*T_num)) - 1; 607 else 608 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; 609 610 tim1 |= val << EMIF_REG_T_RRD_SHIFT; 611 612 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; 613 tim1 |= val << EMIF_REG_T_RC_SHIFT; 614 615 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; 616 tim1 |= val << EMIF_REG_T_RAS_SHIFT; 617 618 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; 619 tim1 |= val << EMIF_REG_T_WR_SHIFT; 620 621 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; 622 tim1 |= val << EMIF_REG_T_RCD_SHIFT; 623 624 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; 625 tim1 |= val << EMIF_REG_T_RP_SHIFT; 626 627 return tim1; 628 } 629 630 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, 631 const struct lpddr2_min_tck *min_tck) 632 { 633 u32 tim2 = 0, val = 0; 634 val = max(min_tck->tCKE, timings->tCKE) - 1; 635 tim2 |= val << EMIF_REG_T_CKE_SHIFT; 636 637 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; 638 tim2 |= val << EMIF_REG_T_RTP_SHIFT; 639 640 /* 641 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the 642 * same value 643 */ 644 val = ns_2_cycles(timings->tXSR) - 1; 645 tim2 |= val << EMIF_REG_T_XSRD_SHIFT; 646 tim2 |= val << EMIF_REG_T_XSNR_SHIFT; 647 648 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; 649 tim2 |= val << EMIF_REG_T_XP_SHIFT; 650 651 return tim2; 652 } 653 654 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, 655 const struct lpddr2_min_tck *min_tck, 656 const struct lpddr2_addressing *addressing) 657 { 658 u32 tim3 = 0, val = 0; 659 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); 660 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; 661 662 val = ns_2_cycles(timings->tRFCab) - 1; 663 tim3 |= val << EMIF_REG_T_RFC_SHIFT; 664 665 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; 666 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; 667 668 val = ns_2_cycles(timings->tZQCS) - 1; 669 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; 670 671 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; 672 tim3 |= val << EMIF_REG_T_CKESR_SHIFT; 673 674 return tim3; 675 } 676 677 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, 678 const struct lpddr2_addressing *addressing, 679 u8 volt_ramp) 680 { 681 u32 zq = 0, val = 0; 682 if (volt_ramp) 683 val = 684 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / 685 addressing->t_REFI_us_x10; 686 else 687 val = 688 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / 689 addressing->t_REFI_us_x10; 690 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; 691 692 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; 693 694 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; 695 696 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; 697 698 /* 699 * Assuming that two chipselects have a single calibration resistor 700 * If there are indeed two calibration resistors, then this flag should 701 * be enabled to take advantage of dual calibration feature. 702 * This data should ideally come from board files. But considering 703 * that none of the boards today have calibration resistors per CS, 704 * it would be an unnecessary overhead. 705 */ 706 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; 707 708 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; 709 710 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; 711 712 return zq; 713 } 714 715 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, 716 const struct lpddr2_addressing *addressing, 717 u8 is_derated) 718 { 719 u32 alert = 0, interval; 720 interval = 721 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; 722 if (is_derated) 723 interval *= 4; 724 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; 725 726 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; 727 728 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; 729 730 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; 731 732 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; 733 734 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; 735 736 return alert; 737 } 738 739 static u32 get_read_idle_ctrl_reg(u8 volt_ramp) 740 { 741 u32 idle = 0, val = 0; 742 if (volt_ramp) 743 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; 744 else 745 /*Maximum value in normal conditions - suggested by hw team */ 746 val = 0x1FF; 747 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; 748 749 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; 750 751 return idle; 752 } 753 754 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) 755 { 756 u32 phy = 0, val = 0; 757 758 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; 759 760 if (freq <= 100000000) 761 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; 762 else if (freq <= 200000000) 763 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; 764 else 765 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; 766 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; 767 768 /* Other fields are constant magic values. Hardcode them together */ 769 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << 770 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; 771 772 return phy; 773 } 774 775 static u32 get_emif_mem_size(u32 base) 776 { 777 u32 size_mbytes = 0, temp; 778 struct emif_device_details dev_details; 779 struct lpddr2_device_details cs0_dev_details, cs1_dev_details; 780 u32 emif_nr = emif_num(base); 781 782 emif_reset_phy(base); 783 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, 784 &cs0_dev_details); 785 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, 786 &cs1_dev_details); 787 emif_reset_phy(base); 788 789 if (dev_details.cs0_device_details) { 790 temp = dev_details.cs0_device_details->density; 791 size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; 792 } 793 794 if (dev_details.cs1_device_details) { 795 temp = dev_details.cs1_device_details->density; 796 size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; 797 } 798 /* convert to bytes */ 799 return size_mbytes << 20; 800 } 801 802 /* Gets the encoding corresponding to a given DMM section size */ 803 u32 get_dmm_section_size_map(u32 section_size) 804 { 805 /* 806 * Section size mapping: 807 * 0x0: 16-MiB section 808 * 0x1: 32-MiB section 809 * 0x2: 64-MiB section 810 * 0x3: 128-MiB section 811 * 0x4: 256-MiB section 812 * 0x5: 512-MiB section 813 * 0x6: 1-GiB section 814 * 0x7: 2-GiB section 815 */ 816 section_size >>= 24; /* divide by 16 MB */ 817 return log_2_n_round_down(section_size); 818 } 819 820 static void emif_calculate_regs( 821 const struct emif_device_details *emif_dev_details, 822 u32 freq, struct emif_regs *regs) 823 { 824 u32 temp, sys_freq; 825 const struct lpddr2_addressing *addressing; 826 const struct lpddr2_ac_timings *timings; 827 const struct lpddr2_min_tck *min_tck; 828 const struct lpddr2_device_details *cs0_dev_details = 829 emif_dev_details->cs0_device_details; 830 const struct lpddr2_device_details *cs1_dev_details = 831 emif_dev_details->cs1_device_details; 832 const struct lpddr2_device_timings *cs0_dev_timings = 833 emif_dev_details->cs0_device_timings; 834 835 emif_assert(emif_dev_details); 836 emif_assert(regs); 837 /* 838 * You can not have a device on CS1 without one on CS0 839 * So configuring EMIF without a device on CS0 doesn't 840 * make sense 841 */ 842 emif_assert(cs0_dev_details); 843 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); 844 /* 845 * If there is a device on CS1 it should be same type as CS0 846 * (or NVM. But NVM is not supported in this driver yet) 847 */ 848 emif_assert((cs1_dev_details == NULL) || 849 (cs1_dev_details->type == LPDDR2_TYPE_NVM) || 850 (cs0_dev_details->type == cs1_dev_details->type)); 851 emif_assert(freq <= MAX_LPDDR2_FREQ); 852 853 set_ddr_clk_period(freq); 854 855 /* 856 * The device on CS0 is used for all timing calculations 857 * There is only one set of registers for timings per EMIF. So, if the 858 * second CS(CS1) has a device, it should have the same timings as the 859 * device on CS0 860 */ 861 timings = get_timings_table(cs0_dev_timings->ac_timings, freq); 862 emif_assert(timings); 863 min_tck = cs0_dev_timings->min_tck; 864 865 temp = addressing_table_index(cs0_dev_details->type, 866 cs0_dev_details->density, 867 cs0_dev_details->io_width); 868 869 emif_assert((temp >= 0)); 870 addressing = &(addressing_table[temp]); 871 emif_assert(addressing); 872 873 sys_freq = get_sys_clk_freq(); 874 875 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, 876 cs1_dev_details, 877 addressing, RL_BOOT); 878 879 regs->sdram_config = get_sdram_config_reg(cs0_dev_details, 880 cs1_dev_details, 881 addressing, RL_FINAL); 882 883 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); 884 885 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); 886 887 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); 888 889 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); 890 891 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); 892 893 regs->temp_alert_config = 894 get_temp_alert_config(cs1_dev_details, addressing, 0); 895 896 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, 897 LPDDR2_VOLTAGE_STABLE); 898 899 regs->emif_ddr_phy_ctlr_1_init = 900 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); 901 902 regs->emif_ddr_phy_ctlr_1 = 903 get_ddr_phy_ctrl_1(freq, RL_FINAL); 904 905 regs->freq = freq; 906 907 print_timing_reg(regs->sdram_config_init); 908 print_timing_reg(regs->sdram_config); 909 print_timing_reg(regs->ref_ctrl); 910 print_timing_reg(regs->sdram_tim1); 911 print_timing_reg(regs->sdram_tim2); 912 print_timing_reg(regs->sdram_tim3); 913 print_timing_reg(regs->read_idle_ctrl); 914 print_timing_reg(regs->temp_alert_config); 915 print_timing_reg(regs->zq_config); 916 print_timing_reg(regs->emif_ddr_phy_ctlr_1); 917 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); 918 } 919 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ 920 921 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 922 const char *get_lpddr2_type(u8 type_id) 923 { 924 switch (type_id) { 925 case LPDDR2_TYPE_S4: 926 return "LPDDR2-S4"; 927 case LPDDR2_TYPE_S2: 928 return "LPDDR2-S2"; 929 default: 930 return NULL; 931 } 932 } 933 934 const char *get_lpddr2_io_width(u8 width_id) 935 { 936 switch (width_id) { 937 case LPDDR2_IO_WIDTH_8: 938 return "x8"; 939 case LPDDR2_IO_WIDTH_16: 940 return "x16"; 941 case LPDDR2_IO_WIDTH_32: 942 return "x32"; 943 default: 944 return NULL; 945 } 946 } 947 948 const char *get_lpddr2_manufacturer(u32 manufacturer) 949 { 950 switch (manufacturer) { 951 case LPDDR2_MANUFACTURER_SAMSUNG: 952 return "Samsung"; 953 case LPDDR2_MANUFACTURER_QIMONDA: 954 return "Qimonda"; 955 case LPDDR2_MANUFACTURER_ELPIDA: 956 return "Elpida"; 957 case LPDDR2_MANUFACTURER_ETRON: 958 return "Etron"; 959 case LPDDR2_MANUFACTURER_NANYA: 960 return "Nanya"; 961 case LPDDR2_MANUFACTURER_HYNIX: 962 return "Hynix"; 963 case LPDDR2_MANUFACTURER_MOSEL: 964 return "Mosel"; 965 case LPDDR2_MANUFACTURER_WINBOND: 966 return "Winbond"; 967 case LPDDR2_MANUFACTURER_ESMT: 968 return "ESMT"; 969 case LPDDR2_MANUFACTURER_SPANSION: 970 return "Spansion"; 971 case LPDDR2_MANUFACTURER_SST: 972 return "SST"; 973 case LPDDR2_MANUFACTURER_ZMOS: 974 return "ZMOS"; 975 case LPDDR2_MANUFACTURER_INTEL: 976 return "Intel"; 977 case LPDDR2_MANUFACTURER_NUMONYX: 978 return "Numonyx"; 979 case LPDDR2_MANUFACTURER_MICRON: 980 return "Micron"; 981 default: 982 return NULL; 983 } 984 } 985 986 static void display_sdram_details(u32 emif_nr, u32 cs, 987 struct lpddr2_device_details *device) 988 { 989 const char *mfg_str; 990 const char *type_str; 991 char density_str[10]; 992 u32 density; 993 994 debug("EMIF%d CS%d\t", emif_nr, cs); 995 996 if (!device) { 997 debug("None\n"); 998 return; 999 } 1000 1001 mfg_str = get_lpddr2_manufacturer(device->manufacturer); 1002 type_str = get_lpddr2_type(device->type); 1003 1004 density = lpddr2_density_2_size_in_mbytes[device->density]; 1005 if ((density / 1024 * 1024) == density) { 1006 density /= 1024; 1007 sprintf(density_str, "%d GB", density); 1008 } else 1009 sprintf(density_str, "%d MB", density); 1010 if (mfg_str && type_str) 1011 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); 1012 } 1013 1014 static u8 is_lpddr2_sdram_present(u32 base, u32 cs, 1015 struct lpddr2_device_details *lpddr2_device) 1016 { 1017 u32 mr = 0, temp; 1018 1019 mr = get_mr(base, cs, LPDDR2_MR0); 1020 if (mr > 0xFF) { 1021 /* Mode register value bigger than 8 bit */ 1022 return 0; 1023 } 1024 1025 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; 1026 if (temp) { 1027 /* Not SDRAM */ 1028 return 0; 1029 } 1030 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; 1031 1032 if (temp) { 1033 /* DNV supported - But DNV is only supported for NVM */ 1034 return 0; 1035 } 1036 1037 mr = get_mr(base, cs, LPDDR2_MR4); 1038 if (mr > 0xFF) { 1039 /* Mode register value bigger than 8 bit */ 1040 return 0; 1041 } 1042 1043 mr = get_mr(base, cs, LPDDR2_MR5); 1044 if (mr > 0xFF) { 1045 /* Mode register value bigger than 8 bit */ 1046 return 0; 1047 } 1048 1049 if (!get_lpddr2_manufacturer(mr)) { 1050 /* Manufacturer not identified */ 1051 return 0; 1052 } 1053 lpddr2_device->manufacturer = mr; 1054 1055 mr = get_mr(base, cs, LPDDR2_MR6); 1056 if (mr >= 0xFF) { 1057 /* Mode register value bigger than 8 bit */ 1058 return 0; 1059 } 1060 1061 mr = get_mr(base, cs, LPDDR2_MR7); 1062 if (mr >= 0xFF) { 1063 /* Mode register value bigger than 8 bit */ 1064 return 0; 1065 } 1066 1067 mr = get_mr(base, cs, LPDDR2_MR8); 1068 if (mr >= 0xFF) { 1069 /* Mode register value bigger than 8 bit */ 1070 return 0; 1071 } 1072 1073 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; 1074 if (!get_lpddr2_type(temp)) { 1075 /* Not SDRAM */ 1076 return 0; 1077 } 1078 lpddr2_device->type = temp; 1079 1080 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; 1081 if (temp > LPDDR2_DENSITY_32Gb) { 1082 /* Density not supported */ 1083 return 0; 1084 } 1085 lpddr2_device->density = temp; 1086 1087 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; 1088 if (!get_lpddr2_io_width(temp)) { 1089 /* IO width unsupported value */ 1090 return 0; 1091 } 1092 lpddr2_device->io_width = temp; 1093 1094 /* 1095 * If all the above tests pass we should 1096 * have a device on this chip-select 1097 */ 1098 return 1; 1099 } 1100 1101 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, 1102 struct lpddr2_device_details *lpddr2_dev_details) 1103 { 1104 u32 phy; 1105 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; 1106 1107 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1108 1109 if (!lpddr2_dev_details) 1110 return NULL; 1111 1112 /* Do the minimum init for mode register accesses */ 1113 if (!(running_from_sdram() || warm_reset())) { 1114 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); 1115 writel(phy, &emif->emif_ddr_phy_ctrl_1); 1116 } 1117 1118 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) 1119 return NULL; 1120 1121 display_sdram_details(emif_num(base), cs, lpddr2_dev_details); 1122 1123 return lpddr2_dev_details; 1124 } 1125 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ 1126 1127 static void do_sdram_init(u32 base) 1128 { 1129 const struct emif_regs *regs; 1130 u32 in_sdram, emif_nr; 1131 1132 debug(">>do_sdram_init() %x\n", base); 1133 1134 in_sdram = running_from_sdram(); 1135 emif_nr = (base == EMIF1_BASE) ? 1 : 2; 1136 1137 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1138 emif_get_reg_dump(emif_nr, ®s); 1139 if (!regs) { 1140 debug("EMIF: reg dump not provided\n"); 1141 return; 1142 } 1143 #else 1144 /* 1145 * The user has not provided the register values. We need to 1146 * calculate it based on the timings and the DDR frequency 1147 */ 1148 struct emif_device_details dev_details; 1149 struct emif_regs calculated_regs; 1150 1151 /* 1152 * Get device details: 1153 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set 1154 * - Obtained from user otherwise 1155 */ 1156 struct lpddr2_device_details cs0_dev_details, cs1_dev_details; 1157 emif_reset_phy(base); 1158 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, 1159 &cs0_dev_details); 1160 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, 1161 &cs1_dev_details); 1162 emif_reset_phy(base); 1163 1164 /* Return if no devices on this EMIF */ 1165 if (!dev_details.cs0_device_details && 1166 !dev_details.cs1_device_details) { 1167 return; 1168 } 1169 1170 /* 1171 * Get device timings: 1172 * - Default timings specified by JESD209-2 if 1173 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set 1174 * - Obtained from user otherwise 1175 */ 1176 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, 1177 &dev_details.cs1_device_timings); 1178 1179 /* Calculate the register values */ 1180 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); 1181 regs = &calculated_regs; 1182 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ 1183 1184 /* 1185 * Initializing the DDR device can not happen from SDRAM. 1186 * Changing the timing registers in EMIF can happen(going from one 1187 * OPP to another) 1188 */ 1189 if (!in_sdram && (!warm_reset() || is_dra7xx())) { 1190 if (emif_sdram_type(regs->sdram_config) == 1191 EMIF_SDRAM_TYPE_LPDDR2) 1192 lpddr2_init(base, regs); 1193 #ifndef CONFIG_OMAP44XX 1194 else 1195 ddr3_init(base, regs); 1196 #endif 1197 } 1198 #ifdef CONFIG_OMAP54XX 1199 if (warm_reset() && (emif_sdram_type(regs->sdram_config) == 1200 EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { 1201 set_lpmode_selfrefresh(base); 1202 emif_reset_phy(base); 1203 omap5_ddr3_leveling(base, regs); 1204 } 1205 #endif 1206 1207 /* Write to the shadow registers */ 1208 emif_update_timings(base, regs); 1209 1210 debug("<<do_sdram_init() %x\n", base); 1211 } 1212 1213 void emif_post_init_config(u32 base) 1214 { 1215 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1216 u32 omap_rev = omap_revision(); 1217 1218 /* reset phy on ES2.0 */ 1219 if (omap_rev == OMAP4430_ES2_0) 1220 emif_reset_phy(base); 1221 1222 /* Put EMIF back in smart idle on ES1.0 */ 1223 if (omap_rev == OMAP4430_ES1_0) 1224 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); 1225 } 1226 1227 void dmm_init(u32 base) 1228 { 1229 const struct dmm_lisa_map_regs *lisa_map_regs; 1230 u32 i, section, valid; 1231 1232 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1233 emif_get_dmm_regs(&lisa_map_regs); 1234 #else 1235 u32 emif1_size, emif2_size, mapped_size, section_map = 0; 1236 u32 section_cnt, sys_addr; 1237 struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; 1238 1239 mapped_size = 0; 1240 section_cnt = 3; 1241 sys_addr = CONFIG_SYS_SDRAM_BASE; 1242 emif1_size = get_emif_mem_size(EMIF1_BASE); 1243 emif2_size = get_emif_mem_size(EMIF2_BASE); 1244 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); 1245 1246 if (!emif1_size && !emif2_size) 1247 return; 1248 1249 /* symmetric interleaved section */ 1250 if (emif1_size && emif2_size) { 1251 mapped_size = min(emif1_size, emif2_size); 1252 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; 1253 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; 1254 /* only MSB */ 1255 section_map |= (sys_addr >> 24) << 1256 EMIF_SYS_ADDR_SHIFT; 1257 section_map |= get_dmm_section_size_map(mapped_size * 2) 1258 << EMIF_SYS_SIZE_SHIFT; 1259 lis_map_regs_calculated.dmm_lisa_map_3 = section_map; 1260 emif1_size -= mapped_size; 1261 emif2_size -= mapped_size; 1262 sys_addr += (mapped_size * 2); 1263 section_cnt--; 1264 } 1265 1266 /* 1267 * Single EMIF section(we can have a maximum of 1 single EMIF 1268 * section- either EMIF1 or EMIF2 or none, but not both) 1269 */ 1270 if (emif1_size) { 1271 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; 1272 section_map |= get_dmm_section_size_map(emif1_size) 1273 << EMIF_SYS_SIZE_SHIFT; 1274 /* only MSB */ 1275 section_map |= (mapped_size >> 24) << 1276 EMIF_SDRC_ADDR_SHIFT; 1277 /* only MSB */ 1278 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; 1279 section_cnt--; 1280 } 1281 if (emif2_size) { 1282 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; 1283 section_map |= get_dmm_section_size_map(emif2_size) << 1284 EMIF_SYS_SIZE_SHIFT; 1285 /* only MSB */ 1286 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; 1287 /* only MSB */ 1288 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; 1289 section_cnt--; 1290 } 1291 1292 if (section_cnt == 2) { 1293 /* Only 1 section - either symmetric or single EMIF */ 1294 lis_map_regs_calculated.dmm_lisa_map_3 = section_map; 1295 lis_map_regs_calculated.dmm_lisa_map_2 = 0; 1296 lis_map_regs_calculated.dmm_lisa_map_1 = 0; 1297 } else { 1298 /* 2 sections - 1 symmetric, 1 single EMIF */ 1299 lis_map_regs_calculated.dmm_lisa_map_2 = section_map; 1300 lis_map_regs_calculated.dmm_lisa_map_1 = 0; 1301 } 1302 1303 /* TRAP for invalid TILER mappings in section 0 */ 1304 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; 1305 1306 if (omap_revision() >= OMAP4460_ES1_0) 1307 lis_map_regs_calculated.is_ma_present = 1; 1308 1309 lisa_map_regs = &lis_map_regs_calculated; 1310 #endif 1311 struct dmm_lisa_map_regs *hw_lisa_map_regs = 1312 (struct dmm_lisa_map_regs *)base; 1313 1314 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); 1315 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); 1316 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); 1317 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); 1318 1319 writel(lisa_map_regs->dmm_lisa_map_3, 1320 &hw_lisa_map_regs->dmm_lisa_map_3); 1321 writel(lisa_map_regs->dmm_lisa_map_2, 1322 &hw_lisa_map_regs->dmm_lisa_map_2); 1323 writel(lisa_map_regs->dmm_lisa_map_1, 1324 &hw_lisa_map_regs->dmm_lisa_map_1); 1325 writel(lisa_map_regs->dmm_lisa_map_0, 1326 &hw_lisa_map_regs->dmm_lisa_map_0); 1327 1328 if (lisa_map_regs->is_ma_present) { 1329 hw_lisa_map_regs = 1330 (struct dmm_lisa_map_regs *)MA_BASE; 1331 1332 writel(lisa_map_regs->dmm_lisa_map_3, 1333 &hw_lisa_map_regs->dmm_lisa_map_3); 1334 writel(lisa_map_regs->dmm_lisa_map_2, 1335 &hw_lisa_map_regs->dmm_lisa_map_2); 1336 writel(lisa_map_regs->dmm_lisa_map_1, 1337 &hw_lisa_map_regs->dmm_lisa_map_1); 1338 writel(lisa_map_regs->dmm_lisa_map_0, 1339 &hw_lisa_map_regs->dmm_lisa_map_0); 1340 1341 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); 1342 } 1343 1344 /* 1345 * EMIF should be configured only when 1346 * memory is mapped on it. Using emif1_enabled 1347 * and emif2_enabled variables for this. 1348 */ 1349 emif1_enabled = 0; 1350 emif2_enabled = 0; 1351 for (i = 0; i < 4; i++) { 1352 section = __raw_readl(DMM_BASE + i*4); 1353 valid = (section & EMIF_SDRC_MAP_MASK) >> 1354 (EMIF_SDRC_MAP_SHIFT); 1355 if (valid == 3) { 1356 emif1_enabled = 1; 1357 emif2_enabled = 1; 1358 break; 1359 } 1360 1361 if (valid == 1) 1362 emif1_enabled = 1; 1363 1364 if (valid == 2) 1365 emif2_enabled = 1; 1366 } 1367 } 1368 1369 static void do_bug0039_workaround(u32 base) 1370 { 1371 u32 val, i, clkctrl; 1372 struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; 1373 const struct read_write_regs *bug_00339_regs; 1374 u32 iterations; 1375 u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; 1376 u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; 1377 1378 if (is_dra7xx()) 1379 phy_status_base++; 1380 1381 bug_00339_regs = get_bug_regs(&iterations); 1382 1383 /* Put EMIF in to idle */ 1384 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); 1385 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); 1386 1387 /* Copy the phy status registers in to phy ctrl shadow registers */ 1388 for (i = 0; i < iterations; i++) { 1389 val = __raw_readl(phy_status_base + 1390 bug_00339_regs[i].read_reg - 1); 1391 1392 __raw_writel(val, phy_ctrl_base + 1393 ((bug_00339_regs[i].write_reg - 1) << 1)); 1394 1395 __raw_writel(val, phy_ctrl_base + 1396 (bug_00339_regs[i].write_reg << 1) - 1); 1397 } 1398 1399 /* Disable leveling */ 1400 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); 1401 1402 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); 1403 } 1404 1405 /* 1406 * SDRAM initialization: 1407 * SDRAM initialization has two parts: 1408 * 1. Configuring the SDRAM device 1409 * 2. Update the AC timings related parameters in the EMIF module 1410 * (1) should be done only once and should not be done while we are 1411 * running from SDRAM. 1412 * (2) can and should be done more than once if OPP changes. 1413 * Particularly, this may be needed when we boot without SPL and 1414 * and using Configuration Header(CH). ROM code supports only at 50% OPP 1415 * at boot (low power boot). So u-boot has to switch to OPP100 and update 1416 * the frequency. So, 1417 * Doing (1) and (2) makes sense - first time initialization 1418 * Doing (2) and not (1) makes sense - OPP change (when using CH) 1419 * Doing (1) and not (2) doen't make sense 1420 * See do_sdram_init() for the details 1421 */ 1422 void sdram_init(void) 1423 { 1424 u32 in_sdram, size_prog, size_detect; 1425 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; 1426 u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); 1427 1428 debug(">>sdram_init()\n"); 1429 1430 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1431 return; 1432 1433 in_sdram = running_from_sdram(); 1434 debug("in_sdram = %d\n", in_sdram); 1435 1436 if (!in_sdram) { 1437 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) 1438 bypass_dpll((*prcm)->cm_clkmode_dpll_core); 1439 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) 1440 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); 1441 } 1442 1443 if (!in_sdram) 1444 dmm_init(DMM_BASE); 1445 1446 if (emif1_enabled) 1447 do_sdram_init(EMIF1_BASE); 1448 1449 if (emif2_enabled) 1450 do_sdram_init(EMIF2_BASE); 1451 1452 if (!(in_sdram || warm_reset())) { 1453 if (emif1_enabled) 1454 emif_post_init_config(EMIF1_BASE); 1455 if (emif2_enabled) 1456 emif_post_init_config(EMIF2_BASE); 1457 } 1458 1459 /* for the shadow registers to take effect */ 1460 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) 1461 freq_update_core(); 1462 1463 /* Do some testing after the init */ 1464 if (!in_sdram) { 1465 size_prog = omap_sdram_size(); 1466 size_prog = log_2_n_round_down(size_prog); 1467 size_prog = (1 << size_prog); 1468 1469 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 1470 size_prog); 1471 /* Compare with the size programmed */ 1472 if (size_detect != size_prog) { 1473 printf("SDRAM: identified size not same as expected" 1474 " size identified: %x expected: %x\n", 1475 size_detect, 1476 size_prog); 1477 } else 1478 debug("get_ram_size() successful"); 1479 } 1480 1481 #if defined(CONFIG_TI_SECURE_DEVICE) 1482 /* 1483 * On HS devices, do static EMIF firewall configuration 1484 * but only do it if not already running in SDRAM 1485 */ 1486 if (!in_sdram) 1487 if (0 != secure_emif_reserve()) 1488 hang(); 1489 1490 /* On HS devices, ensure static EMIF firewall APIs are locked */ 1491 if (0 != secure_emif_firewall_lock()) 1492 hang(); 1493 #endif 1494 1495 if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && 1496 (!in_sdram && !warm_reset()) && (!is_dra7xx())) { 1497 if (emif1_enabled) 1498 do_bug0039_workaround(EMIF1_BASE); 1499 if (emif2_enabled) 1500 do_bug0039_workaround(EMIF2_BASE); 1501 } 1502 1503 debug("<<sdram_init()\n"); 1504 } 1505