1 /* 2 * EMIF programming 3 * 4 * (C) Copyright 2010 5 * Texas Instruments, <www.ti.com> 6 * 7 * Aneesh V <aneesh@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/emif.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/omap_sec_common.h> 18 #include <asm/utils.h> 19 #include <linux/compiler.h> 20 #include <asm/ti-common/ti-edma3.h> 21 22 static int emif1_enabled = -1, emif2_enabled = -1; 23 24 void set_lpmode_selfrefresh(u32 base) 25 { 26 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 27 u32 reg; 28 29 reg = readl(&emif->emif_pwr_mgmt_ctrl); 30 reg &= ~EMIF_REG_LP_MODE_MASK; 31 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; 32 reg &= ~EMIF_REG_SR_TIM_MASK; 33 writel(reg, &emif->emif_pwr_mgmt_ctrl); 34 35 /* dummy read for the new SR_TIM to be loaded */ 36 readl(&emif->emif_pwr_mgmt_ctrl); 37 } 38 39 void force_emif_self_refresh() 40 { 41 set_lpmode_selfrefresh(EMIF1_BASE); 42 if (!is_dra72x()) 43 set_lpmode_selfrefresh(EMIF2_BASE); 44 } 45 46 inline u32 emif_num(u32 base) 47 { 48 if (base == EMIF1_BASE) 49 return 1; 50 else if (base == EMIF2_BASE) 51 return 2; 52 else 53 return 0; 54 } 55 56 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) 57 { 58 u32 mr; 59 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 60 61 mr_addr |= cs << EMIF_REG_CS_SHIFT; 62 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); 63 if (omap_revision() == OMAP4430_ES2_0) 64 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); 65 else 66 mr = readl(&emif->emif_lpddr2_mode_reg_data); 67 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), 68 cs, mr_addr, mr); 69 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && 70 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && 71 ((mr & 0xff000000) >> 24) == (mr & 0xff)) 72 return mr & 0xff; 73 else 74 return mr; 75 } 76 77 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) 78 { 79 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 80 81 mr_addr |= cs << EMIF_REG_CS_SHIFT; 82 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); 83 writel(mr_val, &emif->emif_lpddr2_mode_reg_data); 84 } 85 86 void emif_reset_phy(u32 base) 87 { 88 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 89 u32 iodft; 90 91 iodft = readl(&emif->emif_iodft_tlgc); 92 iodft |= EMIF_REG_RESET_PHY_MASK; 93 writel(iodft, &emif->emif_iodft_tlgc); 94 } 95 96 static void do_lpddr2_init(u32 base, u32 cs) 97 { 98 u32 mr_addr; 99 const struct lpddr2_mr_regs *mr_regs; 100 101 get_lpddr2_mr_regs(&mr_regs); 102 /* Wait till device auto initialization is complete */ 103 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) 104 ; 105 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); 106 /* 107 * tZQINIT = 1 us 108 * Enough loops assuming a maximum of 2GHz 109 */ 110 111 sdelay(2000); 112 113 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); 114 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); 115 116 /* 117 * Enable refresh along with writing MR2 118 * Encoding of RL in MR2 is (RL - 2) 119 */ 120 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; 121 set_mr(base, cs, mr_addr, mr_regs->mr2); 122 123 if (mr_regs->mr3 > 0) 124 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); 125 } 126 127 static void lpddr2_init(u32 base, const struct emif_regs *regs) 128 { 129 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 130 131 /* Not NVM */ 132 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); 133 134 /* 135 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM 136 * when EMIF_SDRAM_CONFIG register is written 137 */ 138 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 139 140 /* 141 * Set the SDRAM_CONFIG and PHY_CTRL for the 142 * un-locked frequency & default RL 143 */ 144 writel(regs->sdram_config_init, &emif->emif_sdram_config); 145 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 146 147 do_ext_phy_settings(base, regs); 148 149 do_lpddr2_init(base, CS0); 150 if (regs->sdram_config & EMIF_REG_EBANK_MASK) 151 do_lpddr2_init(base, CS1); 152 153 writel(regs->sdram_config, &emif->emif_sdram_config); 154 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); 155 156 /* Enable refresh now */ 157 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 158 159 } 160 161 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) 162 { 163 } 164 165 void emif_update_timings(u32 base, const struct emif_regs *regs) 166 { 167 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 168 169 if (!is_dra7xx()) 170 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); 171 else 172 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); 173 174 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); 175 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); 176 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); 177 if (omap_revision() == OMAP4430_ES1_0) { 178 /* ES1 bug EMIF should be in force idle during freq_update */ 179 writel(0, &emif->emif_pwr_mgmt_ctrl); 180 } else { 181 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); 182 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); 183 } 184 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); 185 writel(regs->zq_config, &emif->emif_zq_config); 186 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); 187 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); 188 189 if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { 190 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, 191 &emif->emif_l3_config); 192 } else if (omap_revision() >= OMAP4460_ES1_0) { 193 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, 194 &emif->emif_l3_config); 195 } else { 196 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, 197 &emif->emif_l3_config); 198 } 199 } 200 201 #ifndef CONFIG_OMAP44XX 202 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) 203 { 204 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 205 206 /* keep sdram in self-refresh */ 207 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) 208 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); 209 __udelay(130); 210 211 /* 212 * Set invert_clkout (if activated)--DDR_PHYCTRL_1 213 * Invert clock adds an additional half cycle delay on the 214 * command interface. The additional half cycle, is usually 215 * meant to enable leveling in the situation that DQS is later 216 * than CK on the board.It also helps provide some additional 217 * margin for leveling. 218 */ 219 writel(regs->emif_ddr_phy_ctlr_1, 220 &emif->emif_ddr_phy_ctrl_1); 221 222 writel(regs->emif_ddr_phy_ctlr_1, 223 &emif->emif_ddr_phy_ctrl_1_shdw); 224 __udelay(130); 225 226 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) 227 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); 228 229 /* Launch Full leveling */ 230 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); 231 232 /* Wait till full leveling is complete */ 233 readl(&emif->emif_rd_wr_lvl_ctl); 234 __udelay(130); 235 236 /* Read data eye leveling no of samples */ 237 config_data_eye_leveling_samples(base); 238 239 /* 240 * Launch 8 incremental WR_LVL- to compensate for 241 * PHY limitation. 242 */ 243 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, 244 &emif->emif_rd_wr_lvl_ctl); 245 246 __udelay(130); 247 248 /* Launch Incremental leveling */ 249 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); 250 __udelay(130); 251 } 252 253 static void update_hwleveling_output(u32 base, const struct emif_regs *regs) 254 { 255 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 256 u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; 257 u32 reg, i, phy; 258 259 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; 260 phy = readl(&emif->emif_ddr_phy_ctrl_1); 261 262 /* Update PHY_REG_RDDQS_RATIO */ 263 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; 264 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) 265 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { 266 reg = readl(emif_phy_status++); 267 writel(reg, emif_ext_phy_ctrl_reg++); 268 writel(reg, emif_ext_phy_ctrl_reg++); 269 } 270 271 /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ 272 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; 273 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; 274 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) 275 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { 276 reg = readl(emif_phy_status++); 277 writel(reg, emif_ext_phy_ctrl_reg++); 278 writel(reg, emif_ext_phy_ctrl_reg++); 279 } 280 281 /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ 282 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; 283 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; 284 if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) 285 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { 286 reg = readl(emif_phy_status++); 287 writel(reg, emif_ext_phy_ctrl_reg++); 288 writel(reg, emif_ext_phy_ctrl_reg++); 289 } 290 291 /* Disable Leveling */ 292 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); 293 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); 294 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); 295 } 296 297 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) 298 { 299 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 300 301 /* Clear Error Status */ 302 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, 303 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, 304 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); 305 306 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, 307 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, 308 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); 309 310 /* Disable refreshed before leveling */ 311 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, 312 EMIF_REG_INITREF_DIS_MASK); 313 314 /* Start Full leveling */ 315 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); 316 317 __udelay(300); 318 319 /* Check for leveling timeout */ 320 if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { 321 printf("Leveling timeout on EMIF%d\n", emif_num(base)); 322 return; 323 } 324 325 /* Enable refreshes after leveling */ 326 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); 327 328 debug("HW leveling success\n"); 329 /* 330 * Update slave ratios in EXT_PHY_CTRLx registers 331 * as per HW leveling output 332 */ 333 update_hwleveling_output(base, regs); 334 } 335 336 static void dra7_reset_ddr_data(u32 base, u32 size) 337 { 338 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) 339 enable_edma3_clocks(); 340 341 edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size); 342 343 disable_edma3_clocks(); 344 #else 345 memset((void *)base, 0, size); 346 #endif 347 } 348 349 static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) 350 { 351 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 352 u32 rgn, size; 353 354 /* ECC available only on dra76x EMIF1 */ 355 if ((base != EMIF1_BASE) || !is_dra76x()) 356 return; 357 358 if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) { 359 writel(regs->emif_ecc_address_range_1, 360 &emif->emif_ecc_address_range_1); 361 writel(regs->emif_ecc_address_range_2, 362 &emif->emif_ecc_address_range_2); 363 writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); 364 365 /* Set region1 memory with 0 */ 366 rgn = ((regs->emif_ecc_address_range_1 & 367 EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + 368 CONFIG_SYS_SDRAM_BASE; 369 size = (regs->emif_ecc_address_range_1 & 370 EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; 371 372 if (regs->emif_ecc_ctrl_reg & 373 EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) 374 dra7_reset_ddr_data(rgn, size); 375 376 /* Set region2 memory with 0 */ 377 rgn = ((regs->emif_ecc_address_range_2 & 378 EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + 379 CONFIG_SYS_SDRAM_BASE; 380 size = (regs->emif_ecc_address_range_2 & 381 EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; 382 383 if (regs->emif_ecc_ctrl_reg & 384 EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) 385 dra7_reset_ddr_data(rgn, size); 386 387 #ifdef CONFIG_DRA7XX 388 /* Clear the status flags and other history */ 389 writel(readl(&emif->emif_1b_ecc_err_cnt), 390 &emif->emif_1b_ecc_err_cnt); 391 writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); 392 writel(0x1, &emif->emif_2b_ecc_err_addr_log); 393 writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | 394 EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | 395 EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, 396 &emif->emif_irqstatus_sys); 397 #endif 398 } 399 } 400 401 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) 402 { 403 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 404 405 if (warm_reset()) { 406 emif_reset_phy(base); 407 writel(0x0, &emif->emif_pwr_mgmt_ctrl); 408 } 409 do_ext_phy_settings(base, regs); 410 411 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, 412 &emif->emif_sdram_ref_ctrl); 413 /* Update timing registers */ 414 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); 415 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); 416 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); 417 418 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); 419 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); 420 writel(regs->zq_config, &emif->emif_zq_config); 421 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); 422 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); 423 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); 424 425 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 426 writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); 427 428 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); 429 430 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); 431 writel(regs->sdram_config_init, &emif->emif_sdram_config); 432 433 __udelay(1000); 434 435 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); 436 437 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) { 438 /* 439 * Perform Dummy ECC setup just to allow hardware 440 * leveling of ECC memories 441 */ 442 if (is_dra76x() && (base == EMIF1_BASE) && 443 (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) { 444 writel(0, &emif->emif_ecc_address_range_1); 445 writel(0, &emif->emif_ecc_address_range_2); 446 writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK | 447 EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK, 448 &emif->emif_ecc_ctrl_reg); 449 } 450 451 dra7_ddr3_leveling(base, regs); 452 453 /* Disable ECC */ 454 if (is_dra76x()) 455 writel(0, &emif->emif_ecc_ctrl_reg); 456 } 457 458 /* Enable ECC as necessary */ 459 dra7_enable_ecc(base, regs); 460 } 461 462 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) 463 { 464 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 465 466 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); 467 writel(regs->sdram_config_init, &emif->emif_sdram_config); 468 /* 469 * Set SDRAM_CONFIG and PHY control registers to locked frequency 470 * and RL =7. As the default values of the Mode Registers are not 471 * defined, contents of mode Registers must be fully initialized. 472 * H/W takes care of this initialization 473 */ 474 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); 475 476 /* Update timing registers */ 477 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); 478 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); 479 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); 480 481 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); 482 483 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); 484 writel(regs->sdram_config_init, &emif->emif_sdram_config); 485 do_ext_phy_settings(base, regs); 486 487 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); 488 omap5_ddr3_leveling(base, regs); 489 } 490 491 static void ddr3_init(u32 base, const struct emif_regs *regs) 492 { 493 if (is_omap54xx()) 494 omap5_ddr3_init(base, regs); 495 else 496 dra7_ddr3_init(base, regs); 497 } 498 #endif 499 500 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 501 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) 502 503 /* 504 * Organization and refresh requirements for LPDDR2 devices of different 505 * types and densities. Derived from JESD209-2 section 2.4 506 */ 507 const struct lpddr2_addressing addressing_table[] = { 508 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ 509 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ 510 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ 511 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ 512 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ 513 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ 514 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ 515 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ 516 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ 517 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ 518 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ 519 }; 520 521 static const u32 lpddr2_density_2_size_in_mbytes[] = { 522 8, /* 64Mb */ 523 16, /* 128Mb */ 524 32, /* 256Mb */ 525 64, /* 512Mb */ 526 128, /* 1Gb */ 527 256, /* 2Gb */ 528 512, /* 4Gb */ 529 1024, /* 8Gb */ 530 2048, /* 16Gb */ 531 4096 /* 32Gb */ 532 }; 533 534 /* 535 * Calculate the period of DDR clock from frequency value and set the 536 * denominator and numerator in global variables for easy access later 537 */ 538 static void set_ddr_clk_period(u32 freq) 539 { 540 /* 541 * period = 1/freq 542 * period_in_ns = 10^9/freq 543 */ 544 *T_num = 1000000000; 545 *T_den = freq; 546 cancel_out(T_num, T_den, 200); 547 548 } 549 550 /* 551 * Convert time in nano seconds to number of cycles of DDR clock 552 */ 553 static inline u32 ns_2_cycles(u32 ns) 554 { 555 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); 556 } 557 558 /* 559 * ns_2_cycles with the difference that the time passed is 2 times the actual 560 * value(to avoid fractions). The cycles returned is for the original value of 561 * the timing parameter 562 */ 563 static inline u32 ns_x2_2_cycles(u32 ns) 564 { 565 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); 566 } 567 568 /* 569 * Find addressing table index based on the device's type(S2 or S4) and 570 * density 571 */ 572 s8 addressing_table_index(u8 type, u8 density, u8 width) 573 { 574 u8 index; 575 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) 576 return -1; 577 578 /* 579 * Look at the way ADDR_TABLE_INDEX* values have been defined 580 * in emif.h compared to LPDDR2_DENSITY_* values 581 * The table is layed out in the increasing order of density 582 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed 583 * at the end 584 */ 585 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) 586 index = ADDR_TABLE_INDEX1GS2; 587 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) 588 index = ADDR_TABLE_INDEX2GS2; 589 else 590 index = density; 591 592 debug("emif: addressing table index %d\n", index); 593 594 return index; 595 } 596 597 /* 598 * Find the the right timing table from the array of timing 599 * tables of the device using DDR clock frequency 600 */ 601 static const struct lpddr2_ac_timings *get_timings_table(const struct 602 lpddr2_ac_timings const *const *device_timings, 603 u32 freq) 604 { 605 u32 i, temp, freq_nearest; 606 const struct lpddr2_ac_timings *timings = 0; 607 608 emif_assert(freq <= MAX_LPDDR2_FREQ); 609 emif_assert(device_timings); 610 611 /* 612 * Start with the maximum allowed frequency - that is always safe 613 */ 614 freq_nearest = MAX_LPDDR2_FREQ; 615 /* 616 * Find the timings table that has the max frequency value: 617 * i. Above or equal to the DDR frequency - safe 618 * ii. The lowest that satisfies condition (i) - optimal 619 */ 620 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { 621 temp = device_timings[i]->max_freq; 622 if ((temp >= freq) && (temp <= freq_nearest)) { 623 freq_nearest = temp; 624 timings = device_timings[i]; 625 } 626 } 627 debug("emif: timings table: %d\n", freq_nearest); 628 return timings; 629 } 630 631 /* 632 * Finds the value of emif_sdram_config_reg 633 * All parameters are programmed based on the device on CS0. 634 * If there is a device on CS1, it will be same as that on CS0 or 635 * it will be NVM. We don't support NVM yet. 636 * If cs1_device pointer is NULL it is assumed that there is no device 637 * on CS1 638 */ 639 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, 640 const struct lpddr2_device_details *cs1_device, 641 const struct lpddr2_addressing *addressing, 642 u8 RL) 643 { 644 u32 config_reg = 0; 645 646 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; 647 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << 648 EMIF_REG_IBANK_POS_SHIFT; 649 650 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; 651 652 config_reg |= RL << EMIF_REG_CL_SHIFT; 653 654 config_reg |= addressing->row_sz[cs0_device->io_width] << 655 EMIF_REG_ROWSIZE_SHIFT; 656 657 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; 658 659 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << 660 EMIF_REG_EBANK_SHIFT; 661 662 config_reg |= addressing->col_sz[cs0_device->io_width] << 663 EMIF_REG_PAGESIZE_SHIFT; 664 665 return config_reg; 666 } 667 668 static u32 get_sdram_ref_ctrl(u32 freq, 669 const struct lpddr2_addressing *addressing) 670 { 671 u32 ref_ctrl = 0, val = 0, freq_khz; 672 freq_khz = freq / 1000; 673 /* 674 * refresh rate to be set is 'tREFI * freq in MHz 675 * division by 10000 to account for khz and x10 in t_REFI_us_x10 676 */ 677 val = addressing->t_REFI_us_x10 * freq_khz / 10000; 678 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; 679 680 return ref_ctrl; 681 } 682 683 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, 684 const struct lpddr2_min_tck *min_tck, 685 const struct lpddr2_addressing *addressing) 686 { 687 u32 tim1 = 0, val = 0; 688 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; 689 tim1 |= val << EMIF_REG_T_WTR_SHIFT; 690 691 if (addressing->num_banks == BANKS8) 692 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / 693 (4 * (*T_num)) - 1; 694 else 695 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; 696 697 tim1 |= val << EMIF_REG_T_RRD_SHIFT; 698 699 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; 700 tim1 |= val << EMIF_REG_T_RC_SHIFT; 701 702 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; 703 tim1 |= val << EMIF_REG_T_RAS_SHIFT; 704 705 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; 706 tim1 |= val << EMIF_REG_T_WR_SHIFT; 707 708 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; 709 tim1 |= val << EMIF_REG_T_RCD_SHIFT; 710 711 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; 712 tim1 |= val << EMIF_REG_T_RP_SHIFT; 713 714 return tim1; 715 } 716 717 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, 718 const struct lpddr2_min_tck *min_tck) 719 { 720 u32 tim2 = 0, val = 0; 721 val = max(min_tck->tCKE, timings->tCKE) - 1; 722 tim2 |= val << EMIF_REG_T_CKE_SHIFT; 723 724 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; 725 tim2 |= val << EMIF_REG_T_RTP_SHIFT; 726 727 /* 728 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the 729 * same value 730 */ 731 val = ns_2_cycles(timings->tXSR) - 1; 732 tim2 |= val << EMIF_REG_T_XSRD_SHIFT; 733 tim2 |= val << EMIF_REG_T_XSNR_SHIFT; 734 735 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; 736 tim2 |= val << EMIF_REG_T_XP_SHIFT; 737 738 return tim2; 739 } 740 741 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, 742 const struct lpddr2_min_tck *min_tck, 743 const struct lpddr2_addressing *addressing) 744 { 745 u32 tim3 = 0, val = 0; 746 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); 747 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; 748 749 val = ns_2_cycles(timings->tRFCab) - 1; 750 tim3 |= val << EMIF_REG_T_RFC_SHIFT; 751 752 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; 753 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; 754 755 val = ns_2_cycles(timings->tZQCS) - 1; 756 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; 757 758 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; 759 tim3 |= val << EMIF_REG_T_CKESR_SHIFT; 760 761 return tim3; 762 } 763 764 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, 765 const struct lpddr2_addressing *addressing, 766 u8 volt_ramp) 767 { 768 u32 zq = 0, val = 0; 769 if (volt_ramp) 770 val = 771 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / 772 addressing->t_REFI_us_x10; 773 else 774 val = 775 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / 776 addressing->t_REFI_us_x10; 777 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; 778 779 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; 780 781 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; 782 783 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; 784 785 /* 786 * Assuming that two chipselects have a single calibration resistor 787 * If there are indeed two calibration resistors, then this flag should 788 * be enabled to take advantage of dual calibration feature. 789 * This data should ideally come from board files. But considering 790 * that none of the boards today have calibration resistors per CS, 791 * it would be an unnecessary overhead. 792 */ 793 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; 794 795 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; 796 797 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; 798 799 return zq; 800 } 801 802 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, 803 const struct lpddr2_addressing *addressing, 804 u8 is_derated) 805 { 806 u32 alert = 0, interval; 807 interval = 808 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; 809 if (is_derated) 810 interval *= 4; 811 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; 812 813 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; 814 815 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; 816 817 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; 818 819 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; 820 821 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; 822 823 return alert; 824 } 825 826 static u32 get_read_idle_ctrl_reg(u8 volt_ramp) 827 { 828 u32 idle = 0, val = 0; 829 if (volt_ramp) 830 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; 831 else 832 /*Maximum value in normal conditions - suggested by hw team */ 833 val = 0x1FF; 834 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; 835 836 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; 837 838 return idle; 839 } 840 841 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) 842 { 843 u32 phy = 0, val = 0; 844 845 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; 846 847 if (freq <= 100000000) 848 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; 849 else if (freq <= 200000000) 850 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; 851 else 852 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; 853 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; 854 855 /* Other fields are constant magic values. Hardcode them together */ 856 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << 857 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; 858 859 return phy; 860 } 861 862 static u32 get_emif_mem_size(u32 base) 863 { 864 u32 size_mbytes = 0, temp; 865 struct emif_device_details dev_details; 866 struct lpddr2_device_details cs0_dev_details, cs1_dev_details; 867 u32 emif_nr = emif_num(base); 868 869 emif_reset_phy(base); 870 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, 871 &cs0_dev_details); 872 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, 873 &cs1_dev_details); 874 emif_reset_phy(base); 875 876 if (dev_details.cs0_device_details) { 877 temp = dev_details.cs0_device_details->density; 878 size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; 879 } 880 881 if (dev_details.cs1_device_details) { 882 temp = dev_details.cs1_device_details->density; 883 size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; 884 } 885 /* convert to bytes */ 886 return size_mbytes << 20; 887 } 888 889 /* Gets the encoding corresponding to a given DMM section size */ 890 u32 get_dmm_section_size_map(u32 section_size) 891 { 892 /* 893 * Section size mapping: 894 * 0x0: 16-MiB section 895 * 0x1: 32-MiB section 896 * 0x2: 64-MiB section 897 * 0x3: 128-MiB section 898 * 0x4: 256-MiB section 899 * 0x5: 512-MiB section 900 * 0x6: 1-GiB section 901 * 0x7: 2-GiB section 902 */ 903 section_size >>= 24; /* divide by 16 MB */ 904 return log_2_n_round_down(section_size); 905 } 906 907 static void emif_calculate_regs( 908 const struct emif_device_details *emif_dev_details, 909 u32 freq, struct emif_regs *regs) 910 { 911 u32 temp, sys_freq; 912 const struct lpddr2_addressing *addressing; 913 const struct lpddr2_ac_timings *timings; 914 const struct lpddr2_min_tck *min_tck; 915 const struct lpddr2_device_details *cs0_dev_details = 916 emif_dev_details->cs0_device_details; 917 const struct lpddr2_device_details *cs1_dev_details = 918 emif_dev_details->cs1_device_details; 919 const struct lpddr2_device_timings *cs0_dev_timings = 920 emif_dev_details->cs0_device_timings; 921 922 emif_assert(emif_dev_details); 923 emif_assert(regs); 924 /* 925 * You can not have a device on CS1 without one on CS0 926 * So configuring EMIF without a device on CS0 doesn't 927 * make sense 928 */ 929 emif_assert(cs0_dev_details); 930 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); 931 /* 932 * If there is a device on CS1 it should be same type as CS0 933 * (or NVM. But NVM is not supported in this driver yet) 934 */ 935 emif_assert((cs1_dev_details == NULL) || 936 (cs1_dev_details->type == LPDDR2_TYPE_NVM) || 937 (cs0_dev_details->type == cs1_dev_details->type)); 938 emif_assert(freq <= MAX_LPDDR2_FREQ); 939 940 set_ddr_clk_period(freq); 941 942 /* 943 * The device on CS0 is used for all timing calculations 944 * There is only one set of registers for timings per EMIF. So, if the 945 * second CS(CS1) has a device, it should have the same timings as the 946 * device on CS0 947 */ 948 timings = get_timings_table(cs0_dev_timings->ac_timings, freq); 949 emif_assert(timings); 950 min_tck = cs0_dev_timings->min_tck; 951 952 temp = addressing_table_index(cs0_dev_details->type, 953 cs0_dev_details->density, 954 cs0_dev_details->io_width); 955 956 emif_assert((temp >= 0)); 957 addressing = &(addressing_table[temp]); 958 emif_assert(addressing); 959 960 sys_freq = get_sys_clk_freq(); 961 962 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, 963 cs1_dev_details, 964 addressing, RL_BOOT); 965 966 regs->sdram_config = get_sdram_config_reg(cs0_dev_details, 967 cs1_dev_details, 968 addressing, RL_FINAL); 969 970 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); 971 972 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); 973 974 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); 975 976 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); 977 978 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); 979 980 regs->temp_alert_config = 981 get_temp_alert_config(cs1_dev_details, addressing, 0); 982 983 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, 984 LPDDR2_VOLTAGE_STABLE); 985 986 regs->emif_ddr_phy_ctlr_1_init = 987 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); 988 989 regs->emif_ddr_phy_ctlr_1 = 990 get_ddr_phy_ctrl_1(freq, RL_FINAL); 991 992 regs->freq = freq; 993 994 print_timing_reg(regs->sdram_config_init); 995 print_timing_reg(regs->sdram_config); 996 print_timing_reg(regs->ref_ctrl); 997 print_timing_reg(regs->sdram_tim1); 998 print_timing_reg(regs->sdram_tim2); 999 print_timing_reg(regs->sdram_tim3); 1000 print_timing_reg(regs->read_idle_ctrl); 1001 print_timing_reg(regs->temp_alert_config); 1002 print_timing_reg(regs->zq_config); 1003 print_timing_reg(regs->emif_ddr_phy_ctlr_1); 1004 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); 1005 } 1006 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ 1007 1008 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1009 const char *get_lpddr2_type(u8 type_id) 1010 { 1011 switch (type_id) { 1012 case LPDDR2_TYPE_S4: 1013 return "LPDDR2-S4"; 1014 case LPDDR2_TYPE_S2: 1015 return "LPDDR2-S2"; 1016 default: 1017 return NULL; 1018 } 1019 } 1020 1021 const char *get_lpddr2_io_width(u8 width_id) 1022 { 1023 switch (width_id) { 1024 case LPDDR2_IO_WIDTH_8: 1025 return "x8"; 1026 case LPDDR2_IO_WIDTH_16: 1027 return "x16"; 1028 case LPDDR2_IO_WIDTH_32: 1029 return "x32"; 1030 default: 1031 return NULL; 1032 } 1033 } 1034 1035 const char *get_lpddr2_manufacturer(u32 manufacturer) 1036 { 1037 switch (manufacturer) { 1038 case LPDDR2_MANUFACTURER_SAMSUNG: 1039 return "Samsung"; 1040 case LPDDR2_MANUFACTURER_QIMONDA: 1041 return "Qimonda"; 1042 case LPDDR2_MANUFACTURER_ELPIDA: 1043 return "Elpida"; 1044 case LPDDR2_MANUFACTURER_ETRON: 1045 return "Etron"; 1046 case LPDDR2_MANUFACTURER_NANYA: 1047 return "Nanya"; 1048 case LPDDR2_MANUFACTURER_HYNIX: 1049 return "Hynix"; 1050 case LPDDR2_MANUFACTURER_MOSEL: 1051 return "Mosel"; 1052 case LPDDR2_MANUFACTURER_WINBOND: 1053 return "Winbond"; 1054 case LPDDR2_MANUFACTURER_ESMT: 1055 return "ESMT"; 1056 case LPDDR2_MANUFACTURER_SPANSION: 1057 return "Spansion"; 1058 case LPDDR2_MANUFACTURER_SST: 1059 return "SST"; 1060 case LPDDR2_MANUFACTURER_ZMOS: 1061 return "ZMOS"; 1062 case LPDDR2_MANUFACTURER_INTEL: 1063 return "Intel"; 1064 case LPDDR2_MANUFACTURER_NUMONYX: 1065 return "Numonyx"; 1066 case LPDDR2_MANUFACTURER_MICRON: 1067 return "Micron"; 1068 default: 1069 return NULL; 1070 } 1071 } 1072 1073 static void display_sdram_details(u32 emif_nr, u32 cs, 1074 struct lpddr2_device_details *device) 1075 { 1076 const char *mfg_str; 1077 const char *type_str; 1078 char density_str[10]; 1079 u32 density; 1080 1081 debug("EMIF%d CS%d\t", emif_nr, cs); 1082 1083 if (!device) { 1084 debug("None\n"); 1085 return; 1086 } 1087 1088 mfg_str = get_lpddr2_manufacturer(device->manufacturer); 1089 type_str = get_lpddr2_type(device->type); 1090 1091 density = lpddr2_density_2_size_in_mbytes[device->density]; 1092 if ((density / 1024 * 1024) == density) { 1093 density /= 1024; 1094 sprintf(density_str, "%d GB", density); 1095 } else 1096 sprintf(density_str, "%d MB", density); 1097 if (mfg_str && type_str) 1098 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); 1099 } 1100 1101 static u8 is_lpddr2_sdram_present(u32 base, u32 cs, 1102 struct lpddr2_device_details *lpddr2_device) 1103 { 1104 u32 mr = 0, temp; 1105 1106 mr = get_mr(base, cs, LPDDR2_MR0); 1107 if (mr > 0xFF) { 1108 /* Mode register value bigger than 8 bit */ 1109 return 0; 1110 } 1111 1112 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; 1113 if (temp) { 1114 /* Not SDRAM */ 1115 return 0; 1116 } 1117 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; 1118 1119 if (temp) { 1120 /* DNV supported - But DNV is only supported for NVM */ 1121 return 0; 1122 } 1123 1124 mr = get_mr(base, cs, LPDDR2_MR4); 1125 if (mr > 0xFF) { 1126 /* Mode register value bigger than 8 bit */ 1127 return 0; 1128 } 1129 1130 mr = get_mr(base, cs, LPDDR2_MR5); 1131 if (mr > 0xFF) { 1132 /* Mode register value bigger than 8 bit */ 1133 return 0; 1134 } 1135 1136 if (!get_lpddr2_manufacturer(mr)) { 1137 /* Manufacturer not identified */ 1138 return 0; 1139 } 1140 lpddr2_device->manufacturer = mr; 1141 1142 mr = get_mr(base, cs, LPDDR2_MR6); 1143 if (mr >= 0xFF) { 1144 /* Mode register value bigger than 8 bit */ 1145 return 0; 1146 } 1147 1148 mr = get_mr(base, cs, LPDDR2_MR7); 1149 if (mr >= 0xFF) { 1150 /* Mode register value bigger than 8 bit */ 1151 return 0; 1152 } 1153 1154 mr = get_mr(base, cs, LPDDR2_MR8); 1155 if (mr >= 0xFF) { 1156 /* Mode register value bigger than 8 bit */ 1157 return 0; 1158 } 1159 1160 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; 1161 if (!get_lpddr2_type(temp)) { 1162 /* Not SDRAM */ 1163 return 0; 1164 } 1165 lpddr2_device->type = temp; 1166 1167 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; 1168 if (temp > LPDDR2_DENSITY_32Gb) { 1169 /* Density not supported */ 1170 return 0; 1171 } 1172 lpddr2_device->density = temp; 1173 1174 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; 1175 if (!get_lpddr2_io_width(temp)) { 1176 /* IO width unsupported value */ 1177 return 0; 1178 } 1179 lpddr2_device->io_width = temp; 1180 1181 /* 1182 * If all the above tests pass we should 1183 * have a device on this chip-select 1184 */ 1185 return 1; 1186 } 1187 1188 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, 1189 struct lpddr2_device_details *lpddr2_dev_details) 1190 { 1191 u32 phy; 1192 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; 1193 1194 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1195 1196 if (!lpddr2_dev_details) 1197 return NULL; 1198 1199 /* Do the minimum init for mode register accesses */ 1200 if (!(running_from_sdram() || warm_reset())) { 1201 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); 1202 writel(phy, &emif->emif_ddr_phy_ctrl_1); 1203 } 1204 1205 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) 1206 return NULL; 1207 1208 display_sdram_details(emif_num(base), cs, lpddr2_dev_details); 1209 1210 return lpddr2_dev_details; 1211 } 1212 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ 1213 1214 static void do_sdram_init(u32 base) 1215 { 1216 const struct emif_regs *regs; 1217 u32 in_sdram, emif_nr; 1218 1219 debug(">>do_sdram_init() %x\n", base); 1220 1221 in_sdram = running_from_sdram(); 1222 emif_nr = (base == EMIF1_BASE) ? 1 : 2; 1223 1224 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1225 emif_get_reg_dump(emif_nr, ®s); 1226 if (!regs) { 1227 debug("EMIF: reg dump not provided\n"); 1228 return; 1229 } 1230 #else 1231 /* 1232 * The user has not provided the register values. We need to 1233 * calculate it based on the timings and the DDR frequency 1234 */ 1235 struct emif_device_details dev_details; 1236 struct emif_regs calculated_regs; 1237 1238 /* 1239 * Get device details: 1240 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set 1241 * - Obtained from user otherwise 1242 */ 1243 struct lpddr2_device_details cs0_dev_details, cs1_dev_details; 1244 emif_reset_phy(base); 1245 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, 1246 &cs0_dev_details); 1247 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, 1248 &cs1_dev_details); 1249 emif_reset_phy(base); 1250 1251 /* Return if no devices on this EMIF */ 1252 if (!dev_details.cs0_device_details && 1253 !dev_details.cs1_device_details) { 1254 return; 1255 } 1256 1257 /* 1258 * Get device timings: 1259 * - Default timings specified by JESD209-2 if 1260 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set 1261 * - Obtained from user otherwise 1262 */ 1263 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, 1264 &dev_details.cs1_device_timings); 1265 1266 /* Calculate the register values */ 1267 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); 1268 regs = &calculated_regs; 1269 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ 1270 1271 /* 1272 * Initializing the DDR device can not happen from SDRAM. 1273 * Changing the timing registers in EMIF can happen(going from one 1274 * OPP to another) 1275 */ 1276 if (!in_sdram && (!warm_reset() || is_dra7xx())) { 1277 if (emif_sdram_type(regs->sdram_config) == 1278 EMIF_SDRAM_TYPE_LPDDR2) 1279 lpddr2_init(base, regs); 1280 #ifndef CONFIG_OMAP44XX 1281 else 1282 ddr3_init(base, regs); 1283 #endif 1284 } 1285 #ifdef CONFIG_OMAP54XX 1286 if (warm_reset() && (emif_sdram_type(regs->sdram_config) == 1287 EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { 1288 set_lpmode_selfrefresh(base); 1289 emif_reset_phy(base); 1290 omap5_ddr3_leveling(base, regs); 1291 } 1292 #endif 1293 1294 /* Write to the shadow registers */ 1295 emif_update_timings(base, regs); 1296 1297 debug("<<do_sdram_init() %x\n", base); 1298 } 1299 1300 void emif_post_init_config(u32 base) 1301 { 1302 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1303 u32 omap_rev = omap_revision(); 1304 1305 /* reset phy on ES2.0 */ 1306 if (omap_rev == OMAP4430_ES2_0) 1307 emif_reset_phy(base); 1308 1309 /* Put EMIF back in smart idle on ES1.0 */ 1310 if (omap_rev == OMAP4430_ES1_0) 1311 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); 1312 } 1313 1314 void dmm_init(u32 base) 1315 { 1316 const struct dmm_lisa_map_regs *lisa_map_regs; 1317 u32 i, section, valid; 1318 1319 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1320 emif_get_dmm_regs(&lisa_map_regs); 1321 #else 1322 u32 emif1_size, emif2_size, mapped_size, section_map = 0; 1323 u32 section_cnt, sys_addr; 1324 struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; 1325 1326 mapped_size = 0; 1327 section_cnt = 3; 1328 sys_addr = CONFIG_SYS_SDRAM_BASE; 1329 emif1_size = get_emif_mem_size(EMIF1_BASE); 1330 emif2_size = get_emif_mem_size(EMIF2_BASE); 1331 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); 1332 1333 if (!emif1_size && !emif2_size) 1334 return; 1335 1336 /* symmetric interleaved section */ 1337 if (emif1_size && emif2_size) { 1338 mapped_size = min(emif1_size, emif2_size); 1339 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; 1340 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; 1341 /* only MSB */ 1342 section_map |= (sys_addr >> 24) << 1343 EMIF_SYS_ADDR_SHIFT; 1344 section_map |= get_dmm_section_size_map(mapped_size * 2) 1345 << EMIF_SYS_SIZE_SHIFT; 1346 lis_map_regs_calculated.dmm_lisa_map_3 = section_map; 1347 emif1_size -= mapped_size; 1348 emif2_size -= mapped_size; 1349 sys_addr += (mapped_size * 2); 1350 section_cnt--; 1351 } 1352 1353 /* 1354 * Single EMIF section(we can have a maximum of 1 single EMIF 1355 * section- either EMIF1 or EMIF2 or none, but not both) 1356 */ 1357 if (emif1_size) { 1358 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; 1359 section_map |= get_dmm_section_size_map(emif1_size) 1360 << EMIF_SYS_SIZE_SHIFT; 1361 /* only MSB */ 1362 section_map |= (mapped_size >> 24) << 1363 EMIF_SDRC_ADDR_SHIFT; 1364 /* only MSB */ 1365 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; 1366 section_cnt--; 1367 } 1368 if (emif2_size) { 1369 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; 1370 section_map |= get_dmm_section_size_map(emif2_size) << 1371 EMIF_SYS_SIZE_SHIFT; 1372 /* only MSB */ 1373 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; 1374 /* only MSB */ 1375 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; 1376 section_cnt--; 1377 } 1378 1379 if (section_cnt == 2) { 1380 /* Only 1 section - either symmetric or single EMIF */ 1381 lis_map_regs_calculated.dmm_lisa_map_3 = section_map; 1382 lis_map_regs_calculated.dmm_lisa_map_2 = 0; 1383 lis_map_regs_calculated.dmm_lisa_map_1 = 0; 1384 } else { 1385 /* 2 sections - 1 symmetric, 1 single EMIF */ 1386 lis_map_regs_calculated.dmm_lisa_map_2 = section_map; 1387 lis_map_regs_calculated.dmm_lisa_map_1 = 0; 1388 } 1389 1390 /* TRAP for invalid TILER mappings in section 0 */ 1391 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; 1392 1393 if (omap_revision() >= OMAP4460_ES1_0) 1394 lis_map_regs_calculated.is_ma_present = 1; 1395 1396 lisa_map_regs = &lis_map_regs_calculated; 1397 #endif 1398 struct dmm_lisa_map_regs *hw_lisa_map_regs = 1399 (struct dmm_lisa_map_regs *)base; 1400 1401 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); 1402 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); 1403 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); 1404 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); 1405 1406 writel(lisa_map_regs->dmm_lisa_map_3, 1407 &hw_lisa_map_regs->dmm_lisa_map_3); 1408 writel(lisa_map_regs->dmm_lisa_map_2, 1409 &hw_lisa_map_regs->dmm_lisa_map_2); 1410 writel(lisa_map_regs->dmm_lisa_map_1, 1411 &hw_lisa_map_regs->dmm_lisa_map_1); 1412 writel(lisa_map_regs->dmm_lisa_map_0, 1413 &hw_lisa_map_regs->dmm_lisa_map_0); 1414 1415 if (lisa_map_regs->is_ma_present) { 1416 hw_lisa_map_regs = 1417 (struct dmm_lisa_map_regs *)MA_BASE; 1418 1419 writel(lisa_map_regs->dmm_lisa_map_3, 1420 &hw_lisa_map_regs->dmm_lisa_map_3); 1421 writel(lisa_map_regs->dmm_lisa_map_2, 1422 &hw_lisa_map_regs->dmm_lisa_map_2); 1423 writel(lisa_map_regs->dmm_lisa_map_1, 1424 &hw_lisa_map_regs->dmm_lisa_map_1); 1425 writel(lisa_map_regs->dmm_lisa_map_0, 1426 &hw_lisa_map_regs->dmm_lisa_map_0); 1427 1428 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); 1429 } 1430 1431 /* 1432 * EMIF should be configured only when 1433 * memory is mapped on it. Using emif1_enabled 1434 * and emif2_enabled variables for this. 1435 */ 1436 emif1_enabled = 0; 1437 emif2_enabled = 0; 1438 for (i = 0; i < 4; i++) { 1439 section = __raw_readl(DMM_BASE + i*4); 1440 valid = (section & EMIF_SDRC_MAP_MASK) >> 1441 (EMIF_SDRC_MAP_SHIFT); 1442 if (valid == 3) { 1443 emif1_enabled = 1; 1444 emif2_enabled = 1; 1445 break; 1446 } 1447 1448 if (valid == 1) 1449 emif1_enabled = 1; 1450 1451 if (valid == 2) 1452 emif2_enabled = 1; 1453 } 1454 } 1455 1456 static void do_bug0039_workaround(u32 base) 1457 { 1458 u32 val, i, clkctrl; 1459 struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; 1460 const struct read_write_regs *bug_00339_regs; 1461 u32 iterations; 1462 u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; 1463 u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; 1464 1465 if (is_dra7xx()) 1466 phy_status_base++; 1467 1468 bug_00339_regs = get_bug_regs(&iterations); 1469 1470 /* Put EMIF in to idle */ 1471 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); 1472 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); 1473 1474 /* Copy the phy status registers in to phy ctrl shadow registers */ 1475 for (i = 0; i < iterations; i++) { 1476 val = __raw_readl(phy_status_base + 1477 bug_00339_regs[i].read_reg - 1); 1478 1479 __raw_writel(val, phy_ctrl_base + 1480 ((bug_00339_regs[i].write_reg - 1) << 1)); 1481 1482 __raw_writel(val, phy_ctrl_base + 1483 (bug_00339_regs[i].write_reg << 1) - 1); 1484 } 1485 1486 /* Disable leveling */ 1487 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); 1488 1489 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); 1490 } 1491 1492 /* 1493 * SDRAM initialization: 1494 * SDRAM initialization has two parts: 1495 * 1. Configuring the SDRAM device 1496 * 2. Update the AC timings related parameters in the EMIF module 1497 * (1) should be done only once and should not be done while we are 1498 * running from SDRAM. 1499 * (2) can and should be done more than once if OPP changes. 1500 * Particularly, this may be needed when we boot without SPL and 1501 * and using Configuration Header(CH). ROM code supports only at 50% OPP 1502 * at boot (low power boot). So u-boot has to switch to OPP100 and update 1503 * the frequency. So, 1504 * Doing (1) and (2) makes sense - first time initialization 1505 * Doing (2) and not (1) makes sense - OPP change (when using CH) 1506 * Doing (1) and not (2) doen't make sense 1507 * See do_sdram_init() for the details 1508 */ 1509 void sdram_init(void) 1510 { 1511 u32 in_sdram, size_prog, size_detect; 1512 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; 1513 u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); 1514 1515 debug(">>sdram_init()\n"); 1516 1517 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1518 return; 1519 1520 in_sdram = running_from_sdram(); 1521 debug("in_sdram = %d\n", in_sdram); 1522 1523 if (!in_sdram) { 1524 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) 1525 bypass_dpll((*prcm)->cm_clkmode_dpll_core); 1526 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) 1527 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); 1528 } 1529 1530 if (!in_sdram) 1531 dmm_init(DMM_BASE); 1532 1533 if (emif1_enabled) 1534 do_sdram_init(EMIF1_BASE); 1535 1536 if (emif2_enabled) 1537 do_sdram_init(EMIF2_BASE); 1538 1539 if (!(in_sdram || warm_reset())) { 1540 if (emif1_enabled) 1541 emif_post_init_config(EMIF1_BASE); 1542 if (emif2_enabled) 1543 emif_post_init_config(EMIF2_BASE); 1544 } 1545 1546 /* for the shadow registers to take effect */ 1547 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) 1548 freq_update_core(); 1549 1550 /* Do some testing after the init */ 1551 if (!in_sdram) { 1552 size_prog = omap_sdram_size(); 1553 size_prog = log_2_n_round_down(size_prog); 1554 size_prog = (1 << size_prog); 1555 1556 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 1557 size_prog); 1558 /* Compare with the size programmed */ 1559 if (size_detect != size_prog) { 1560 printf("SDRAM: identified size not same as expected" 1561 " size identified: %x expected: %x\n", 1562 size_detect, 1563 size_prog); 1564 } else 1565 debug("get_ram_size() successful"); 1566 } 1567 1568 #if defined(CONFIG_TI_SECURE_DEVICE) 1569 /* 1570 * On HS devices, do static EMIF firewall configuration 1571 * but only do it if not already running in SDRAM 1572 */ 1573 if (!in_sdram) 1574 if (0 != secure_emif_reserve()) 1575 hang(); 1576 1577 /* On HS devices, ensure static EMIF firewall APIs are locked */ 1578 if (0 != secure_emif_firewall_lock()) 1579 hang(); 1580 #endif 1581 1582 if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && 1583 (!in_sdram && !warm_reset()) && (!is_dra7xx())) { 1584 if (emif1_enabled) 1585 do_bug0039_workaround(EMIF1_BASE); 1586 if (emif2_enabled) 1587 do_bug0039_workaround(EMIF2_BASE); 1588 } 1589 1590 debug("<<sdram_init()\n"); 1591 } 1592