1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ti816x_emif4.c 4 * 5 * TI816x emif4 configuration file 6 * 7 * Copyright (C) 2017, Konsulko Group 8 */ 9 10 #include <common.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/ddr_defs.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/io.h> 17 #include <asm/emif.h> 18 19 /********************************************************************* 20 * Init DDR3 on TI816X EVM 21 *********************************************************************/ 22 static void ddr_init_settings(const struct cmd_control *ctrl, int emif) 23 { 24 /* 25 * setup use_rank_delays to 1. This is only necessary when 26 * multiple ranks are in use. Though the EVM does not have 27 * multiple ranks, this is a good value to set. 28 */ 29 writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS 30 writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS 31 writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS 32 writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS 33 34 config_cmd_ctrl(ctrl, emif); 35 36 /* for ddr3 this needs to be set to 1 */ 37 writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ 38 writel(0x1, DDRPHY_CONFIG_BASE + 0x104); 39 writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); 40 writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); 41 writel(0x1, DDRPHY_CONFIG_BASE + 0x240); 42 writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); 43 writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); 44 writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); 45 46 /* 47 * This represents the initial value for the leveling process. The 48 * value is a ratio - so 0x100 represents one cycle. The real delay 49 * is determined through the leveling process. 50 * 51 * During the leveling process, 0x20 is subtracted from the value, so 52 * we have added that to the value we want to set. We also set the 53 * values such that byte3 completes leveling after byte2 and byte1 54 * after byte0. 55 */ 56 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */ 57 writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */ 58 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */ 59 writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */ 60 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */ 61 writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */ 62 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */ 63 writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */ 64 65 66 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */ 67 writel(0x0, DDRPHY_CONFIG_BASE + 0x100); 68 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */ 69 writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); 70 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */ 71 writel(0x0, DDRPHY_CONFIG_BASE + 0x248); 72 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */ 73 writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); 74 75 writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */ 76 writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */ 77 writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */ 78 writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */ 79 writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */ 80 writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */ 81 writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */ 82 writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */ 83 writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */ 84 writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */ 85 writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */ 86 writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */ 87 writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */ 88 writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */ 89 } 90 91 static void ddr3_sw_levelling(const struct ddr_data *data, int emif) 92 { 93 /* Set the correct value to DDR_VTP_CTRL_0 */ 94 writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); 95 96 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108)); 97 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC)); 98 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250)); 99 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4)); 100 101 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC)); 102 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180)); 103 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224)); 104 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8)); 105 106 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); 107 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); 108 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); 109 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); 110 111 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8)); 112 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C)); 113 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210)); 114 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4)); 115 } 116 117 static struct dmm_lisa_map_regs *hw_lisa_map_regs = 118 (struct dmm_lisa_map_regs *)DMM_BASE; 119 120 #define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) 121 void config_dmm(const struct dmm_lisa_map_regs *regs) 122 { 123 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); 124 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); 125 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); 126 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); 127 128 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); 129 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); 130 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); 131 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); 132 133 /* Enable Tiled Access */ 134 writel(0x80000000, DMM_PAT_BASE_ADDR); 135 } 136 137 void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, 138 const struct emif_regs *regs, 139 const struct dmm_lisa_map_regs *lisa_regs, int nrs) 140 { 141 int i; 142 143 enable_emif_clocks(); 144 145 for (i = 0; i < nrs; i++) 146 ddr_init_settings(ctrl, i); 147 148 enable_dmm_clocks(); 149 150 /* Program the DMM to for non-interleaved configuration */ 151 config_dmm(lisa_regs); 152 153 /* Program EMIF CFG Registers */ 154 for (i = 0; i < nrs; i++) { 155 set_sdram_timings(regs, i); 156 config_sdram(regs, i); 157 } 158 159 udelay(1000); 160 for (i = 0; i < nrs; i++) 161 ddr3_sw_levelling(data, i); 162 163 udelay(50000); /* Some delay needed */ 164 } 165