1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * sys_info.c
4  *
5  * System information functions
6  *
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8  *
9  * Derived from Beagle Board and 3430 SDP code by
10  *      Richard Woodruff <r-woodruff2@ti.com>
11  *      Syed Mohammed Khasim <khasim@ti.com>
12  */
13 
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/clock.h>
19 #include <power/tps65910.h>
20 #include <linux/compiler.h>
21 
22 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
23 
24 /**
25  * get_cpu_rev(void) - extract rev info
26  */
27 u32 get_cpu_rev(void)
28 {
29 	u32 id;
30 	u32 rev;
31 
32 	id = readl(DEVICE_ID);
33 	rev = (id >> 28) & 0xff;
34 
35 	return rev;
36 }
37 
38 /**
39  * get_cpu_type(void) - extract cpu info
40  */
41 u32 get_cpu_type(void)
42 {
43 	u32 id = 0;
44 	u32 partnum;
45 
46 	id = readl(DEVICE_ID);
47 	partnum = (id >> 12) & 0xffff;
48 
49 	return partnum;
50 }
51 
52 /**
53  * get_sysboot_value(void) - return SYS_BOOT[4:0]
54  */
55 u32 get_sysboot_value(void)
56 {
57 	return readl(&cstat->statusreg) & SYSBOOT_MASK;
58 }
59 
60 u32 get_sys_clk_index(void)
61 {
62 	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
63 	u32 ind = readl(&ctrl->statusreg);
64 
65 #ifdef CONFIG_AM43XX
66 	u32 src;
67 	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
68 	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
69 		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
70 			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
71 	else /* Value read from SYS BOOT pins */
72 #endif
73 		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
74 			CTRL_SYSBOOT_15_14_SHIFT);
75 }
76 
77 
78 #ifdef CONFIG_DISPLAY_CPUINFO
79 static char *cpu_revs[] = {
80 		"1.0",
81 		"2.0",
82 		"2.1"};
83 
84 static char *cpu_revs_am43xx[] = {
85 		"1.0",
86 		"1.1",
87 		"1.2"};
88 
89 static char *dev_types[] = {
90 		"TST",
91 		"EMU",
92 		"HS",
93 		"GP"};
94 
95 /**
96  * Print CPU information
97  */
98 int print_cpuinfo(void)
99 {
100 	char *cpu_s, *sec_s, *rev_s;
101 	char **cpu_rev_arr = cpu_revs;
102 
103 	switch (get_cpu_type()) {
104 	case AM335X:
105 		cpu_s = "AM335X";
106 		break;
107 	case TI81XX:
108 		cpu_s = "TI81XX";
109 		break;
110 	case AM437X:
111 		cpu_s = "AM437X";
112 		cpu_rev_arr = cpu_revs_am43xx;
113 		break;
114 	default:
115 		cpu_s = "Unknown CPU type";
116 		break;
117 	}
118 
119 	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
120 		rev_s = cpu_rev_arr[get_cpu_rev()];
121 	else
122 		rev_s = "?";
123 
124 	if (get_device_type() < ARRAY_SIZE(dev_types))
125 		sec_s = dev_types[get_device_type()];
126 	else
127 		sec_s = "?";
128 
129 	printf("CPU  : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
130 
131 	return 0;
132 }
133 #endif	/* CONFIG_DISPLAY_CPUINFO */
134 
135 #ifdef CONFIG_AM33XX
136 int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
137 {
138 	int sil_rev;
139 
140 	sil_rev = readl(&cdev->deviceid) >> 28;
141 
142 	if (sil_rev == 0) {
143 		/* No efuse in PG 1.0. Use max speed */
144 		return MPUPLL_M_720;
145 	} else if (sil_rev >= 1) {
146 		/* Check what the efuse says our max speed is. */
147 		int efuse_arm_mpu_max_freq, package_type;
148 		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
149 		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
150 				PACKAGE_TYPE_SHIFT;
151 
152 		/* PG 2.0, efuse may not be set. */
153 		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
154 		    PACKAGE_TYPE_RESERVED)
155 			return MPUPLL_M_800;
156 
157 		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
158 		case AM335X_ZCZ_1000:
159 			return MPUPLL_M_1000;
160 		case AM335X_ZCZ_800:
161 			return MPUPLL_M_800;
162 		case AM335X_ZCZ_720:
163 			return MPUPLL_M_720;
164 		case AM335X_ZCZ_600:
165 		case AM335X_ZCE_600:
166 			return MPUPLL_M_600;
167 		case AM335X_ZCZ_300:
168 		case AM335X_ZCE_300:
169 			return MPUPLL_M_300;
170 		}
171 	}
172 
173 	/* unknown, use the PG1.0 max */
174 	return MPUPLL_M_720;
175 }
176 
177 int am335x_get_mpu_vdd(int sil_rev, int frequency)
178 {
179 	int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
180 
181 	switch (sel_mask) {
182 	case TPS65910_OP_REG_SEL_1_3_2_5:
183 		return 1325000;
184 	case TPS65910_OP_REG_SEL_1_2_0:
185 		return 1200000;
186 	case TPS65910_OP_REG_SEL_1_1_0:
187 		return 1100000;
188 	default:
189 		return 1262500;
190 	}
191 }
192 
193 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
194 {
195 	/* For PG2.0 and later, we have one set of values. */
196 	if (sil_rev >= 1) {
197 		switch (frequency) {
198 		case MPUPLL_M_1000:
199 			return TPS65910_OP_REG_SEL_1_3_2_5;
200 		case MPUPLL_M_800:
201 			return TPS65910_OP_REG_SEL_1_2_6;
202 		case MPUPLL_M_720:
203 			return TPS65910_OP_REG_SEL_1_2_0;
204 		case MPUPLL_M_600:
205 		case MPUPLL_M_500:
206 		case MPUPLL_M_300:
207 			return TPS65910_OP_REG_SEL_1_1_0;
208 		}
209 	}
210 
211 	/* Default to PG1.0 values. */
212 	return TPS65910_OP_REG_SEL_1_2_6;
213 }
214 #endif
215