1 /* 2 * emif4.c 3 * 4 * AM33XX emif4 configuration file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/ddr_defs.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/io.h> 18 #include <asm/emif.h> 19 20 static struct vtp_reg *vtpreg[2] = { 21 (struct vtp_reg *)VTP0_CTRL_ADDR, 22 (struct vtp_reg *)VTP1_CTRL_ADDR}; 23 #ifdef CONFIG_AM33XX 24 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; 25 #endif 26 #ifdef CONFIG_AM43XX 27 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; 28 static struct cm_device_inst *cm_device = 29 (struct cm_device_inst *)CM_DEVICE_INST; 30 #endif 31 32 #ifdef CONFIG_TI814X 33 void config_dmm(const struct dmm_lisa_map_regs *regs) 34 { 35 struct dmm_lisa_map_regs *hw_lisa_map_regs = 36 (struct dmm_lisa_map_regs *)DMM_BASE; 37 38 enable_dmm_clocks(); 39 40 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); 41 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); 42 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); 43 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); 44 45 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); 46 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); 47 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); 48 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); 49 } 50 #endif 51 52 static void config_vtp(int nr) 53 { 54 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, 55 &vtpreg[nr]->vtp0ctrlreg); 56 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), 57 &vtpreg[nr]->vtp0ctrlreg); 58 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, 59 &vtpreg[nr]->vtp0ctrlreg); 60 61 /* Poll for READY */ 62 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != 63 VTP_CTRL_READY) 64 ; 65 } 66 67 void __weak ddr_pll_config(unsigned int ddrpll_m) 68 { 69 } 70 71 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, 72 const struct ddr_data *data, const struct cmd_control *ctrl, 73 const struct emif_regs *regs, int nr) 74 { 75 ddr_pll_config(pll); 76 config_vtp(nr); 77 config_cmd_ctrl(ctrl, nr); 78 79 config_ddr_data(data, nr); 80 #ifdef CONFIG_AM33XX 81 config_io_ctrl(ioregs); 82 83 /* Set CKE to be controlled by EMIF/DDR PHY */ 84 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); 85 86 #endif 87 #ifdef CONFIG_AM43XX 88 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); 89 while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) 90 ; 91 92 config_io_ctrl(ioregs); 93 94 /* Set CKE to be controlled by EMIF/DDR PHY */ 95 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); 96 97 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) 98 /* Allow EMIF to control DDR_RESET */ 99 writel(0x00000000, &ddrctrl->ddrioctrl); 100 #endif 101 102 /* Program EMIF instance */ 103 config_ddr_phy(regs, nr); 104 set_sdram_timings(regs, nr); 105 if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) 106 config_sdram_emif4d5(regs, nr); 107 else 108 config_sdram(regs, nr); 109 } 110