1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * clock_ti814x.c
4 *
5 * Clocks for TI814X based boards
6 *
7 * Copyright (C) 2013, Texas Instruments, Incorporated
8 */
9
10 #include <common.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/io.h>
15
16 /* PRCM */
17 #define PRCM_MOD_EN 0x2
18
19 /* CLK_SRC */
20 #define OSC_SRC0 0
21 #define OSC_SRC1 1
22
23 #define L3_OSC_SRC OSC_SRC0
24
25 #define OSC_0_FREQ 20
26
27 #define DCO_HS2_MIN 500
28 #define DCO_HS2_MAX 1000
29 #define DCO_HS1_MIN 1000
30 #define DCO_HS1_MAX 2000
31
32 #define SELFREQDCO_HS2 0x00000801
33 #define SELFREQDCO_HS1 0x00001001
34
35 #define MPU_N 0x1
36 #define MPU_M 0x3C
37 #define MPU_M2 1
38 #define MPU_CLKCTRL 0x1
39
40 #define L3_N 19
41 #define L3_M 880
42 #define L3_M2 4
43 #define L3_CLKCTRL 0x801
44
45 #define DDR_N 19
46 #define DDR_M 666
47 #define DDR_M2 2
48 #define DDR_CLKCTRL 0x801
49
50 /* ADPLLJ register values */
51 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
52 #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
53 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
54 #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
55 #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
56 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
57 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
58 #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
59 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
60 #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
61 #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
62 #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
63 ADPLLJ_CLKCTRL_CLKOUTEN | \
64 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
65 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
66
67 #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
68 #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
69 #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
70 ADPLLJ_STATUS_FREQLOCK)
71 #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
72 #define ADPLLJ_STATUS_BYPASS (1 << 0)
73 #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
74 ADPLLJ_STATUS_BYPASS)
75
76 #define ADPLLJ_TENABLE_ENB (1 << 0)
77 #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
78
79 #define ADPLLJ_M2NDIV_M2SHIFT 16
80
81 #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
82 #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
83 #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
84
85 struct ad_pll {
86 unsigned int pwrctrl;
87 unsigned int clkctrl;
88 unsigned int tenable;
89 unsigned int tenablediv;
90 unsigned int m2ndiv;
91 unsigned int mn2div;
92 unsigned int fracdiv;
93 unsigned int bwctrl;
94 unsigned int fracctrl;
95 unsigned int status;
96 unsigned int m3div;
97 unsigned int rampctrl;
98 };
99
100 #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
101
102 #define ENET_CLKCTRL_CMPL 0x30000
103
104 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
105
106 struct sata_pll {
107 unsigned int pllcfg0;
108 unsigned int pllcfg1;
109 unsigned int pllcfg2;
110 unsigned int pllcfg3;
111 unsigned int pllcfg4;
112 unsigned int pllstatus;
113 unsigned int rxstatus;
114 unsigned int txstatus;
115 unsigned int testcfg;
116 };
117
118 #define SEL_IN_FREQ (0x1 << 31)
119 #define DIGCLRZ (0x1 << 30)
120 #define ENDIGLDO (0x1 << 4)
121 #define APLL_CP_CURR (0x1 << 3)
122 #define ENBGSC_REF (0x1 << 2)
123 #define ENPLLLDO (0x1 << 1)
124 #define ENPLL (0x1 << 0)
125
126 #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
127 #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
128 #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
129 #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
130 ENPLLLDO | ENPLL)
131
132 #define PLL_LOCK (0x1 << 0)
133
134 #define ENSATAMODE (0x1 << 31)
135 #define PLLREFSEL (0x1 << 30)
136 #define MDIVINT (0x4b << 18)
137 #define EN_CLKAUX (0x1 << 5)
138 #define EN_CLK125M (0x1 << 4)
139 #define EN_CLK100M (0x1 << 3)
140 #define EN_CLK50M (0x1 << 2)
141
142 #define SATA_PLLCFG1 (ENSATAMODE | \
143 PLLREFSEL | \
144 MDIVINT | \
145 EN_CLKAUX | \
146 EN_CLK125M | \
147 EN_CLK100M | \
148 EN_CLK50M)
149
150 #define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
151 #define PLLDO_EN_LDO_STABLE (0x1 << 11)
152 #define PLLDO_EN_BUF_CUR (0x1 << 7)
153 #define PLLDO_EN_LP (0x1 << 6)
154 #define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
155
156 #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
157 PLLDO_EN_LDO_STABLE | \
158 PLLDO_EN_BUF_CUR | \
159 PLLDO_EN_LP | \
160 PLLDO_CTRL_TRIM_1_4V)
161
162 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
163 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
164 const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
165
166 /*
167 * Enable the peripheral clock for required peripherals
168 */
enable_per_clocks(void)169 static void enable_per_clocks(void)
170 {
171 /* HSMMC1 */
172 writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
173 while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
174 ;
175
176 /* Ethernet */
177 writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
178 writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
179 while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
180 ;
181 writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
182 while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
183 ;
184
185 /* RTC clocks */
186 writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
187 writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
188 while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
189 ;
190 }
191
192 /*
193 * select the HS1 or HS2 for DCO Freq
194 * return : CLKCTRL
195 */
pll_dco_freq_sel(u32 clkout_dco)196 static u32 pll_dco_freq_sel(u32 clkout_dco)
197 {
198 if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
199 return SELFREQDCO_HS2;
200 else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
201 return SELFREQDCO_HS1;
202 else
203 return -1;
204 }
205
206 /*
207 * select the sigma delta config
208 * return: sigma delta val
209 */
pll_sigma_delta_val(u32 clkout_dco)210 static u32 pll_sigma_delta_val(u32 clkout_dco)
211 {
212 u32 sig_val = 0;
213
214 sig_val = (clkout_dco + 225) / 250;
215 sig_val = sig_val << 24;
216
217 return sig_val;
218 }
219
220 /*
221 * configure individual ADPLLJ
222 */
pll_config(u32 base,u32 n,u32 m,u32 m2,u32 clkctrl_val,int adpllj)223 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
224 u32 clkctrl_val, int adpllj)
225 {
226 const struct ad_pll *adpll = (struct ad_pll *)base;
227 u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
228 u32 sig_val = 0, hs_mod = 0;
229
230 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
231 mn2val = m;
232
233 /* calculate clkout_dco */
234 clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
235
236 /* sigma delta & Hs mode selection skip for ADPLLS*/
237 if (adpllj) {
238 sig_val = pll_sigma_delta_val(clkout_dco);
239 hs_mod = pll_dco_freq_sel(clkout_dco);
240 }
241
242 /* by-pass pll */
243 read_clkctrl = readl(&adpll->clkctrl);
244 writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
245 while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
246 != ADPLLJ_STATUS_BYPASSANDACK)
247 ;
248
249 /* clear TINITZ */
250 read_clkctrl = readl(&adpll->clkctrl);
251 writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
252
253 /*
254 * ref_clk = 20/(n + 1);
255 * clkout_dco = ref_clk * m;
256 * clk_out = clkout_dco/m2;
257 */
258 read_clkctrl = readl(&adpll->clkctrl) &
259 ~(ADPLLJ_CLKCTRL_LPMODE |
260 ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
261 ADPLLJ_CLKCTRL_REGM4XEN);
262 writel(m2nval, &adpll->m2ndiv);
263 writel(mn2val, &adpll->mn2div);
264
265 /* Skip for modena(ADPLLS) */
266 if (adpllj) {
267 writel(sig_val, &adpll->fracdiv);
268 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
269 }
270
271 /* Load M2, N2 dividers of ADPLL */
272 writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
273 writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
274
275 /* Load M, N dividers of ADPLL */
276 writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
277 writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
278
279 /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
280 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
281 if (adpllj)
282 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
283 &adpll->clkctrl);
284
285 /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
286 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
287 writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
288
289 /* Wait for phase and freq lock */
290 while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
291 ADPLLJ_STATUS_PHSFRQLOCK)
292 ;
293 }
294
unlock_pll_control_mmr(void)295 static void unlock_pll_control_mmr(void)
296 {
297 /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
298 writel(0x1EDA4C3D, 0x481C5040);
299 writel(0x2FF1AC2B, 0x48140060);
300 writel(0xF757FDC0, 0x48140064);
301 writel(0xE2BC3A6D, 0x48140068);
302 writel(0x1EBF131D, 0x4814006c);
303 writel(0x6F361E05, 0x48140070);
304 }
305
mpu_pll_config(void)306 static void mpu_pll_config(void)
307 {
308 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
309 }
310
l3_pll_config(void)311 static void l3_pll_config(void)
312 {
313 u32 l3_osc_src, rd_osc_src = 0;
314
315 l3_osc_src = L3_OSC_SRC;
316 rd_osc_src = readl(OSC_SRC_CTRL);
317
318 if (OSC_SRC0 == l3_osc_src)
319 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
320 else
321 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
322
323 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
324 }
325
ddr_pll_config(unsigned int ddrpll_m)326 void ddr_pll_config(unsigned int ddrpll_m)
327 {
328 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
329 }
330
sata_pll_config(void)331 void sata_pll_config(void)
332 {
333 /*
334 * This sequence for configuring the SATA PLL
335 * resident in the control module is documented
336 * in TI8148 TRM section 21.3.1
337 */
338 writel(SATA_PLLCFG1, &spll->pllcfg1);
339 udelay(50);
340
341 writel(SATA_PLLCFG3, &spll->pllcfg3);
342 udelay(50);
343
344 writel(SATA_PLLCFG0_1, &spll->pllcfg0);
345 udelay(50);
346
347 writel(SATA_PLLCFG0_2, &spll->pllcfg0);
348 udelay(50);
349
350 writel(SATA_PLLCFG0_3, &spll->pllcfg0);
351 udelay(50);
352
353 writel(SATA_PLLCFG0_4, &spll->pllcfg0);
354 udelay(50);
355
356 while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
357 ;
358 }
359
enable_dmm_clocks(void)360 void enable_dmm_clocks(void)
361 {
362 writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
363 writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
364 writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
365 while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
366 ;
367 writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
368 while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
369 ;
370 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
371 ;
372 writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
373 while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
374 ;
375 writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
376 while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
377 ;
378 }
379
setup_clocks_for_console(void)380 void setup_clocks_for_console(void)
381 {
382 unlock_pll_control_mmr();
383 /* UART0 */
384 writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
385 while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
386 ;
387 }
388
setup_early_clocks(void)389 void setup_early_clocks(void)
390 {
391 setup_clocks_for_console();
392 }
393
394 /*
395 * Configure the PLL/PRCM for necessary peripherals
396 */
prcm_init(void)397 void prcm_init(void)
398 {
399 /* Enable the control module */
400 writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
401
402 /* Configure PLLs */
403 mpu_pll_config();
404 l3_pll_config();
405 sata_pll_config();
406
407 /* Enable the required peripherals */
408 enable_per_clocks();
409 }
410