1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * clock_am43xx.c
4  *
5  * clocks for AM43XX based boards
6  * Derived from AM33XX based boards
7  *
8  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
9  */
10 
11 #include <common.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/io.h>
17 
18 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
19 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
20 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
21 
22 const struct dpll_regs dpll_mpu_regs = {
23 	.cm_clkmode_dpll	= CM_WKUP + 0x560,
24 	.cm_idlest_dpll		= CM_WKUP + 0x564,
25 	.cm_clksel_dpll		= CM_WKUP + 0x56c,
26 	.cm_div_m2_dpll		= CM_WKUP + 0x570,
27 };
28 
29 const struct dpll_regs dpll_core_regs = {
30 	.cm_clkmode_dpll	= CM_WKUP + 0x520,
31 	.cm_idlest_dpll		= CM_WKUP + 0x524,
32 	.cm_clksel_dpll		= CM_WKUP + 0x52C,
33 	.cm_div_m4_dpll		= CM_WKUP + 0x538,
34 	.cm_div_m5_dpll		= CM_WKUP + 0x53C,
35 	.cm_div_m6_dpll		= CM_WKUP + 0x540,
36 };
37 
38 const struct dpll_regs dpll_per_regs = {
39 	.cm_clkmode_dpll	= CM_WKUP + 0x5E0,
40 	.cm_idlest_dpll		= CM_WKUP + 0x5E4,
41 	.cm_clksel_dpll		= CM_WKUP + 0x5EC,
42 	.cm_div_m2_dpll		= CM_WKUP + 0x5F0,
43 };
44 
45 const struct dpll_regs dpll_ddr_regs = {
46 	.cm_clkmode_dpll	= CM_WKUP + 0x5A0,
47 	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
48 	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
49 	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
50 	.cm_div_m4_dpll		= CM_WKUP + 0x5B8,
51 };
52 
53 void setup_clocks_for_console(void)
54 {
55 	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
56 
57 	/* Do not add any spl_debug prints in this function */
58 	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
59 			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
60 			CD_CLKCTRL_CLKTRCTRL_SHIFT);
61 
62 	/* Enable UART0 */
63 	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
64 			MODULE_CLKCTRL_MODULEMODE_MASK,
65 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
66 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
67 
68 	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
69 		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
70 		clkctrl = readl(&cmwkup->wkup_uart0ctrl);
71 		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
72 			 MODULE_CLKCTRL_IDLEST_SHIFT;
73 	}
74 }
75 
76 void enable_basic_clocks(void)
77 {
78 	u32 *const clk_domains[] = {
79 		&cmper->l3clkstctrl,
80 		&cmper->l3sclkstctrl,
81 		&cmper->l4lsclkstctrl,
82 		&cmwkup->wkclkstctrl,
83 		&cmper->emifclkstctrl,
84 		0
85 	};
86 
87 	u32 *const clk_modules_explicit_en[] = {
88 		&cmper->l3clkctrl,
89 		&cmper->l4lsclkctrl,
90 		&cmper->l4fwclkctrl,
91 		&cmwkup->wkl4wkclkctrl,
92 		&cmper->l3instrclkctrl,
93 		&cmper->l4hsclkctrl,
94 		&cmwkup->wkgpio0clkctrl,
95 		&cmwkup->wkctrlclkctrl,
96 		&cmper->timer2clkctrl,
97 		&cmper->gpmcclkctrl,
98 		&cmper->elmclkctrl,
99 		&cmper->mmc0clkctrl,
100 		&cmper->mmc1clkctrl,
101 		&cmwkup->wkup_i2c0ctrl,
102 		&cmper->gpio1clkctrl,
103 		&cmper->gpio2clkctrl,
104 		&cmper->gpio3clkctrl,
105 		&cmper->gpio4clkctrl,
106 		&cmper->gpio5clkctrl,
107 		&cmper->i2c1clkctrl,
108 		&cmper->cpgmac0clkctrl,
109 		&cmper->emiffwclkctrl,
110 		&cmper->emifclkctrl,
111 		&cmper->otfaemifclkctrl,
112 		&cmper->qspiclkctrl,
113 		&cmper->spi0clkctrl,
114 		0
115 	};
116 
117 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
118 
119 	/* Select the Master osc clk as Timer2 clock source */
120 	writel(0x1, &cmdpll->clktimer2clk);
121 
122 	/* For OPP100 the mac clock should be /5. */
123 	writel(0x4, &cmdpll->clkselmacclk);
124 }
125 
126 void rtc_only_enable_basic_clocks(void)
127 {
128 	u32 *const clk_domains[] = {
129 		&cmper->emifclkstctrl,
130 		0
131 	};
132 
133 	u32 *const clk_modules_explicit_en[] = {
134 		&cmper->gpio5clkctrl,
135 		&cmper->emiffwclkctrl,
136 		&cmper->emifclkctrl,
137 		&cmper->otfaemifclkctrl,
138 		0
139 	};
140 
141 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
142 
143 	/* Select the Master osc clk as Timer2 clock source */
144 	writel(0x1, &cmdpll->clktimer2clk);
145 }
146 
147 #ifdef CONFIG_TI_EDMA3
148 void enable_edma3_clocks(void)
149 {
150 	u32 *const clk_domains_edma3[] = {
151 		0
152 	};
153 
154 	u32 *const clk_modules_explicit_en_edma3[] = {
155 		&cmper->tpccclkctrl,
156 		&cmper->tptc0clkctrl,
157 		0
158 	};
159 
160 	do_enable_clocks(clk_domains_edma3,
161 			 clk_modules_explicit_en_edma3,
162 			 1);
163 }
164 
165 void disable_edma3_clocks(void)
166 {
167 	u32 *const clk_domains_edma3[] = {
168 		0
169 	};
170 
171 	u32 *const clk_modules_disable_edma3[] = {
172 		&cmper->tpccclkctrl,
173 		&cmper->tptc0clkctrl,
174 		0
175 	};
176 
177 	do_disable_clocks(clk_domains_edma3,
178 			  clk_modules_disable_edma3,
179 			  1);
180 }
181 #endif
182 
183 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
184 void enable_usb_clocks(int index)
185 {
186 	u32 *usbclkctrl = 0;
187 	u32 *usbphyocp2scpclkctrl = 0;
188 
189 	if (index == 0) {
190 		usbclkctrl = &cmper->usb0clkctrl;
191 		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
192 		setbits_le32(&cmper->usb0clkctrl,
193 			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
194 		setbits_le32(&cmwkup->usbphy0clkctrl,
195 			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
196 	} else if (index == 1) {
197 		usbclkctrl = &cmper->usb1clkctrl;
198 		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
199 		setbits_le32(&cmper->usb1clkctrl,
200 			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
201 		setbits_le32(&cmwkup->usbphy1clkctrl,
202 			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
203 	}
204 
205 	u32 *const clk_domains_usb[] = {
206 		0
207 	};
208 
209 	u32 *const clk_modules_explicit_en_usb[] = {
210 		usbclkctrl,
211 		usbphyocp2scpclkctrl,
212 		0
213 	};
214 
215 	do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
216 }
217 
218 void disable_usb_clocks(int index)
219 {
220 	u32 *usbclkctrl = 0;
221 	u32 *usbphyocp2scpclkctrl = 0;
222 
223 	if (index == 0) {
224 		usbclkctrl = &cmper->usb0clkctrl;
225 		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
226 		clrbits_le32(&cmper->usb0clkctrl,
227 			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
228 		clrbits_le32(&cmwkup->usbphy0clkctrl,
229 			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
230 	} else if (index == 1) {
231 		usbclkctrl = &cmper->usb1clkctrl;
232 		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
233 		clrbits_le32(&cmper->usb1clkctrl,
234 			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
235 		clrbits_le32(&cmwkup->usbphy1clkctrl,
236 			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
237 	}
238 
239 	u32 *const clk_domains_usb[] = {
240 		0
241 	};
242 
243 	u32 *const clk_modules_disable_usb[] = {
244 		usbclkctrl,
245 		usbphyocp2scpclkctrl,
246 		0
247 	};
248 
249 	do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
250 }
251 #endif
252