1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 4 * Copyright (C) 2017, Grinn - http://grinn-global.com/ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/arch/clk_synthesizer.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/ddr_defs.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/omap.h> 14 #include <asm/arch/mem.h> 15 #include <asm/arch/mux.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/emif.h> 18 #include <asm/io.h> 19 #include <errno.h> 20 #include <i2c.h> 21 #include <power/tps65217.h> 22 #include <spl.h> 23 24 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 25 26 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 27 28 static struct module_pin_mux i2c0_pin_mux[] = { 29 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 30 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 31 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 32 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 33 {-1}, 34 }; 35 36 static struct module_pin_mux nand_pin_mux[] = { 37 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 38 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 39 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 40 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 41 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 42 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 43 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 44 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 45 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 46 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 47 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 48 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 49 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 50 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 51 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 52 {-1}, 53 }; 54 55 static void enable_i2c0_pin_mux(void) 56 { 57 configure_module_pin_mux(i2c0_pin_mux); 58 } 59 60 void chilisom_enable_pin_mux(void) 61 { 62 /* chilisom pin mux */ 63 configure_module_pin_mux(nand_pin_mux); 64 } 65 66 static const struct ddr_data ddr3_chilisom_data = { 67 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 68 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 69 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 70 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 71 }; 72 73 static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = { 74 .cmd0csratio = MT41K256M16HA125E_RATIO, 75 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 76 77 .cmd1csratio = MT41K256M16HA125E_RATIO, 78 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 79 80 .cmd2csratio = MT41K256M16HA125E_RATIO, 81 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 82 }; 83 84 static struct emif_regs ddr3_chilisom_emif_reg_data = { 85 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 86 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 87 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 88 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 89 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 90 .ocp_config = 0x00141414, 91 .zq_config = MT41K256M16HA125E_ZQ_CFG, 92 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 93 }; 94 95 void chilisom_spl_board_init(void) 96 { 97 int mpu_vdd; 98 int usb_cur_lim; 99 100 enable_i2c0_pin_mux(); 101 102 /* Get the frequency */ 103 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 104 105 106 if (i2c_probe(TPS65217_CHIP_PM)) 107 return; 108 109 /* 110 * Increase USB current limit to 1300mA or 1800mA and set 111 * the MPU voltage controller as needed. 112 */ 113 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 114 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 115 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 116 } else { 117 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 118 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 119 } 120 121 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 122 TPS65217_POWER_PATH, 123 usb_cur_lim, 124 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 125 puts("tps65217_reg_write failure\n"); 126 127 /* Set DCDC3 (CORE) voltage to 1.125V */ 128 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 129 TPS65217_DCDC_VOLT_SEL_1125MV)) { 130 puts("tps65217_voltage_update failure\n"); 131 return; 132 } 133 /* Set CORE Frequencies to OPP100 */ 134 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 135 136 /* Set DCDC2 (MPU) voltage */ 137 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 138 puts("tps65217_voltage_update failure\n"); 139 return; 140 } 141 142 /* Set LDO3 to 1.8V and LDO4 to 3.3V */ 143 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 144 TPS65217_DEFLS1, 145 TPS65217_LDO_VOLTAGE_OUT_1_8, 146 TPS65217_LDO_MASK)) 147 puts("tps65217_reg_write failure\n"); 148 149 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 150 TPS65217_DEFLS2, 151 TPS65217_LDO_VOLTAGE_OUT_3_3, 152 TPS65217_LDO_MASK)) 153 puts("tps65217_reg_write failure\n"); 154 155 /* Set MPU Frequency to what we detected now that voltages are set */ 156 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 157 } 158 159 #define OSC (V_OSCK/1000000) 160 const struct dpll_params dpll_ddr_chilisom = { 161 400, OSC-1, 1, -1, -1, -1, -1}; 162 163 const struct dpll_params *get_dpll_ddr_params(void) 164 { 165 return &dpll_ddr_chilisom; 166 } 167 168 const struct ctrl_ioregs ioregs_chilisom = { 169 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 170 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 171 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 172 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 173 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 174 }; 175 176 void sdram_init(void) 177 { 178 config_ddr(400, &ioregs_chilisom, 179 &ddr3_chilisom_data, 180 &ddr3_chilisom_cmd_ctrl_data, 181 &ddr3_chilisom_emif_reg_data, 0); 182 } 183 184 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 185