1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board.c
4  *
5  * Common board functions for AM33XX based boards
6  *
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8  */
9 
10 #include <common.h>
11 #include <dm.h>
12 #include <debug_uart.h>
13 #include <errno.h>
14 #include <ns16550.h>
15 #include <spl.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <asm/omap_common.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <cpsw.h>
32 #include <linux/errno.h>
33 #include <linux/compiler.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/musb.h>
37 #include <asm/omap_musb.h>
38 #include <asm/davinci_rtc.h>
39 
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 int dram_init(void)
43 {
44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
45 	sdram_init();
46 #endif
47 
48 	/* dram_init must store complete ramsize in gd->ram_size */
49 	gd->ram_size = get_ram_size(
50 			(void *)CONFIG_SYS_SDRAM_BASE,
51 			CONFIG_MAX_RAM_BANK_SIZE);
52 	return 0;
53 }
54 
55 int dram_init_banksize(void)
56 {
57 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
58 	gd->bd->bi_dram[0].size = gd->ram_size;
59 
60 	return 0;
61 }
62 
63 #if !CONFIG_IS_ENABLED(OF_CONTROL)
64 static const struct ns16550_platdata am33xx_serial[] = {
65 	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
66 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
67 # ifdef CONFIG_SYS_NS16550_COM2
68 	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
69 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
70 #  ifdef CONFIG_SYS_NS16550_COM3
71 	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
72 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
73 	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
74 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
75 	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
76 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
77 	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
78 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
79 #  endif
80 # endif
81 };
82 
83 U_BOOT_DEVICES(am33xx_uarts) = {
84 	{ "ns16550_serial", &am33xx_serial[0] },
85 #  ifdef CONFIG_SYS_NS16550_COM2
86 	{ "ns16550_serial", &am33xx_serial[1] },
87 #   ifdef CONFIG_SYS_NS16550_COM3
88 	{ "ns16550_serial", &am33xx_serial[2] },
89 	{ "ns16550_serial", &am33xx_serial[3] },
90 	{ "ns16550_serial", &am33xx_serial[4] },
91 	{ "ns16550_serial", &am33xx_serial[5] },
92 #   endif
93 #  endif
94 };
95 
96 #ifdef CONFIG_DM_GPIO
97 static const struct omap_gpio_platdata am33xx_gpio[] = {
98 	{ 0, AM33XX_GPIO0_BASE },
99 	{ 1, AM33XX_GPIO1_BASE },
100 	{ 2, AM33XX_GPIO2_BASE },
101 	{ 3, AM33XX_GPIO3_BASE },
102 #ifdef CONFIG_AM43XX
103 	{ 4, AM33XX_GPIO4_BASE },
104 	{ 5, AM33XX_GPIO5_BASE },
105 #endif
106 };
107 
108 U_BOOT_DEVICES(am33xx_gpios) = {
109 	{ "gpio_omap", &am33xx_gpio[0] },
110 	{ "gpio_omap", &am33xx_gpio[1] },
111 	{ "gpio_omap", &am33xx_gpio[2] },
112 	{ "gpio_omap", &am33xx_gpio[3] },
113 #ifdef CONFIG_AM43XX
114 	{ "gpio_omap", &am33xx_gpio[4] },
115 	{ "gpio_omap", &am33xx_gpio[5] },
116 #endif
117 };
118 #endif
119 #endif
120 
121 #ifndef CONFIG_DM_GPIO
122 static const struct gpio_bank gpio_bank_am33xx[] = {
123 	{ (void *)AM33XX_GPIO0_BASE },
124 	{ (void *)AM33XX_GPIO1_BASE },
125 	{ (void *)AM33XX_GPIO2_BASE },
126 	{ (void *)AM33XX_GPIO3_BASE },
127 #ifdef CONFIG_AM43XX
128 	{ (void *)AM33XX_GPIO4_BASE },
129 	{ (void *)AM33XX_GPIO5_BASE },
130 #endif
131 };
132 
133 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
134 #endif
135 
136 #if defined(CONFIG_MMC_OMAP_HS)
137 int cpu_mmc_init(bd_t *bis)
138 {
139 	int ret;
140 
141 	ret = omap_mmc_init(0, 0, 0, -1, -1);
142 	if (ret)
143 		return ret;
144 
145 	return omap_mmc_init(1, 0, 0, -1, -1);
146 }
147 #endif
148 
149 /*
150  * RTC only with DDR in self-refresh mode magic value, checked against during
151  * boot to see if we have a valid config. This should be in sync with the value
152  * that will be in drivers/soc/ti/pm33xx.c.
153  */
154 #define RTC_MAGIC_VAL		0x8cd0
155 
156 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
157 #define RTC_BOARD_TYPE_SHIFT	16
158 
159 /* AM33XX has two MUSB controllers which can be host or gadget */
160 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
161 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
162 	(!defined(CONFIG_DM_USB))
163 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
164 
165 /* USB 2.0 PHY Control */
166 #define CM_PHY_PWRDN			(1 << 0)
167 #define CM_PHY_OTG_PWRDN		(1 << 1)
168 #define OTGVDET_EN			(1 << 19)
169 #define OTGSESSENDEN			(1 << 20)
170 
171 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
172 {
173 	if (on) {
174 		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
175 				OTGVDET_EN | OTGSESSENDEN);
176 	} else {
177 		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
178 	}
179 }
180 
181 static struct musb_hdrc_config musb_config = {
182 	.multipoint     = 1,
183 	.dyn_fifo       = 1,
184 	.num_eps        = 16,
185 	.ram_bits       = 12,
186 };
187 
188 #ifdef CONFIG_AM335X_USB0
189 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
190 {
191 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
192 }
193 
194 struct omap_musb_board_data otg0_board_data = {
195 	.set_phy_power = am33xx_otg0_set_phy_power,
196 };
197 
198 static struct musb_hdrc_platform_data otg0_plat = {
199 	.mode           = CONFIG_AM335X_USB0_MODE,
200 	.config         = &musb_config,
201 	.power          = 50,
202 	.platform_ops	= &musb_dsps_ops,
203 	.board_data	= &otg0_board_data,
204 };
205 #endif
206 
207 #ifdef CONFIG_AM335X_USB1
208 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
209 {
210 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
211 }
212 
213 struct omap_musb_board_data otg1_board_data = {
214 	.set_phy_power = am33xx_otg1_set_phy_power,
215 };
216 
217 static struct musb_hdrc_platform_data otg1_plat = {
218 	.mode           = CONFIG_AM335X_USB1_MODE,
219 	.config         = &musb_config,
220 	.power          = 50,
221 	.platform_ops	= &musb_dsps_ops,
222 	.board_data	= &otg1_board_data,
223 };
224 #endif
225 
226 int arch_misc_init(void)
227 {
228 #ifdef CONFIG_AM335X_USB0
229 	musb_register(&otg0_plat, &otg0_board_data,
230 		(void *)USB0_OTG_BASE);
231 #endif
232 #ifdef CONFIG_AM335X_USB1
233 	musb_register(&otg1_plat, &otg1_board_data,
234 		(void *)USB1_OTG_BASE);
235 #endif
236 	return 0;
237 }
238 
239 #else	/* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
240 
241 int arch_misc_init(void)
242 {
243 	struct udevice *dev;
244 	int ret;
245 
246 	ret = uclass_first_device(UCLASS_MISC, &dev);
247 	if (ret || !dev)
248 		return ret;
249 
250 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
251 	ret = usb_ether_init();
252 	if (ret) {
253 		pr_err("USB ether init failed\n");
254 		return ret;
255 	}
256 #endif
257 
258 	return 0;
259 }
260 
261 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
262 
263 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
264 
265 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
266 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
267 static void rtc32k_unlock(struct davinci_rtc *rtc)
268 {
269 	/*
270 	 * Unlock the RTC's registers.  For more details please see the
271 	 * RTC_SS section of the TRM.  In order to unlock we need to
272 	 * write these specific values (keys) in this order.
273 	 */
274 	writel(RTC_KICK0R_WE, &rtc->kick0r);
275 	writel(RTC_KICK1R_WE, &rtc->kick1r);
276 }
277 #endif
278 
279 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
280 /*
281  * Write contents of the RTC_SCRATCH1 register based on board type
282  * Two things are passed
283  * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
284  * control gets to kernel, kernel reads the scratchpad register and gets to
285  * know that bootloader has rtc_only support.
286  *
287  * Second important thing is the board type  (16:31). This is needed in the
288  * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
289  * identify the board type and we go ahead and copy the board strings to
290  * am43xx_board_name.
291  */
292 void update_rtc_magic(void)
293 {
294 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
295 	u32 magic = RTC_MAGIC_VAL;
296 
297 	magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
298 
299 	rtc32k_unlock(rtc);
300 
301 	/* write magic */
302 	writel(magic, &rtc->scratch1);
303 }
304 #endif
305 
306 /*
307  * In the case of non-SPL based booting we'll want to call these
308  * functions a tiny bit later as it will require gd to be set and cleared
309  * and that's not true in s_init in this case so we cannot do it there.
310  */
311 int board_early_init_f(void)
312 {
313 	prcm_init();
314 	set_mux_conf_regs();
315 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
316 	update_rtc_magic();
317 #endif
318 	return 0;
319 }
320 
321 /*
322  * This function is the place to do per-board things such as ramp up the
323  * MPU clock frequency.
324  */
325 __weak void am33xx_spl_board_init(void)
326 {
327 }
328 
329 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
330 static void rtc32k_enable(void)
331 {
332 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
333 
334 	rtc32k_unlock(rtc);
335 
336 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
337 	writel((1 << 3) | (1 << 6), &rtc->osc);
338 }
339 #endif
340 
341 static void uart_soft_reset(void)
342 {
343 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
344 	u32 regval;
345 
346 	regval = readl(&uart_base->uartsyscfg);
347 	regval |= UART_RESET;
348 	writel(regval, &uart_base->uartsyscfg);
349 	while ((readl(&uart_base->uartsyssts) &
350 		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
351 		;
352 
353 	/* Disable smart idle */
354 	regval = readl(&uart_base->uartsyscfg);
355 	regval |= UART_SMART_IDLE_EN;
356 	writel(regval, &uart_base->uartsyscfg);
357 }
358 
359 static void watchdog_disable(void)
360 {
361 	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
362 
363 	writel(0xAAAA, &wdtimer->wdtwspr);
364 	while (readl(&wdtimer->wdtwwps) != 0x0)
365 		;
366 	writel(0x5555, &wdtimer->wdtwspr);
367 	while (readl(&wdtimer->wdtwwps) != 0x0)
368 		;
369 }
370 
371 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
372 /*
373  * Check if we are executing rtc-only + DDR mode, and resume from it if needed
374  */
375 static void rtc_only(void)
376 {
377 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
378 	struct prm_device_inst *prm_device =
379 				(struct prm_device_inst *)PRM_DEVICE_INST;
380 
381 	u32 scratch1;
382 	void (*resume_func)(void);
383 
384 	scratch1 = readl(&rtc->scratch1);
385 
386 	/*
387 	 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
388 	 * written to this register when we want to wake up from RTC only
389 	 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
390 	 * bits 0-15:  RTC_MAGIC_VAL
391 	 * bits 16-31: board type (needed for sdram_init)
392 	 */
393 	if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
394 		return;
395 
396 	rtc32k_unlock(rtc);
397 
398 	/* Clear RTC magic */
399 	writel(0, &rtc->scratch1);
400 
401 	/*
402 	 * Update board type based on value stored on RTC_SCRATCH1, this
403 	 * is done so that we don't need to read the board type from eeprom
404 	 * over i2c bus which is expensive
405 	 */
406 	rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
407 
408 	/*
409 	 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
410 	 * are resuming from self-refresh. This avoids an unnecessary re-init
411 	 * of the DDR. The re-init takes time and we would need to wait for
412 	 * it to complete before accessing DDR to avoid L3 NOC errors.
413 	 */
414 	writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
415 
416 	rtc_only_prcm_init();
417 	sdram_init();
418 
419 	/* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
420 	writel(0, &prm_device->emif_ctrl);
421 
422 	resume_func = (void *)readl(&rtc->scratch0);
423 	if (resume_func)
424 		resume_func();
425 }
426 #endif
427 
428 void s_init(void)
429 {
430 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
431 	rtc_only();
432 #endif
433 }
434 
435 void early_system_init(void)
436 {
437 	/*
438 	 * The ROM will only have set up sufficient pinmux to allow for the
439 	 * first 4KiB NOR to be read, we must finish doing what we know of
440 	 * the NOR mux in this space in order to continue.
441 	 */
442 #ifdef CONFIG_NOR_BOOT
443 	enable_norboot_pin_mux();
444 #endif
445 	watchdog_disable();
446 	set_uart_mux_conf();
447 	setup_early_clocks();
448 	uart_soft_reset();
449 #ifdef CONFIG_SPL_BUILD
450 	/*
451 	 * Save the boot parameters passed from romcode.
452 	 * We cannot delay the saving further than this,
453 	 * to prevent overwrites.
454 	 */
455 	save_omap_boot_params();
456 #endif
457 #ifdef CONFIG_DEBUG_UART_OMAP
458 	debug_uart_init();
459 #endif
460 #ifdef CONFIG_TI_I2C_BOARD_DETECT
461 	do_board_detect();
462 #endif
463 #ifdef CONFIG_SPL_BUILD
464 	spl_early_init();
465 #endif
466 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
467 	/* Enable RTC32K clock */
468 	rtc32k_enable();
469 #endif
470 }
471 
472 #ifdef CONFIG_SPL_BUILD
473 void board_init_f(ulong dummy)
474 {
475 	hw_data_init();
476 	early_system_init();
477 	board_early_init_f();
478 	sdram_init();
479 	/* dram_init must store complete ramsize in gd->ram_size */
480 	gd->ram_size = get_ram_size(
481 			(void *)CONFIG_SYS_SDRAM_BASE,
482 			CONFIG_MAX_RAM_BANK_SIZE);
483 }
484 #endif
485 
486 #endif
487 
488 int arch_cpu_init_dm(void)
489 {
490 	hw_data_init();
491 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
492 	early_system_init();
493 #endif
494 	return 0;
495 }
496