1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * Common board functions for AM33XX based boards 6 * 7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <debug_uart.h> 13 #include <errno.h> 14 #include <ns16550.h> 15 #include <spl.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/i2c.h> 23 #include <asm/arch/mem.h> 24 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <asm/omap_common.h> 30 #include <i2c.h> 31 #include <miiphy.h> 32 #include <cpsw.h> 33 #include <linux/errno.h> 34 #include <linux/compiler.h> 35 #include <linux/usb/ch9.h> 36 #include <linux/usb/gadget.h> 37 #include <linux/usb/musb.h> 38 #include <asm/omap_musb.h> 39 #include <asm/davinci_rtc.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int dram_init(void) 44 { 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 46 sdram_init(); 47 #endif 48 49 /* dram_init must store complete ramsize in gd->ram_size */ 50 gd->ram_size = get_ram_size( 51 (void *)CONFIG_SYS_SDRAM_BASE, 52 CONFIG_MAX_RAM_BANK_SIZE); 53 return 0; 54 } 55 56 int dram_init_banksize(void) 57 { 58 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 59 gd->bd->bi_dram[0].size = gd->ram_size; 60 61 return 0; 62 } 63 64 #if !CONFIG_IS_ENABLED(OF_CONTROL) 65 static const struct ns16550_platdata am33xx_serial[] = { 66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 67 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 68 # ifdef CONFIG_SYS_NS16550_COM2 69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 70 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 71 # ifdef CONFIG_SYS_NS16550_COM3 72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 73 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 75 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 77 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 79 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 80 # endif 81 # endif 82 }; 83 84 U_BOOT_DEVICES(am33xx_uarts) = { 85 { "ns16550_serial", &am33xx_serial[0] }, 86 # ifdef CONFIG_SYS_NS16550_COM2 87 { "ns16550_serial", &am33xx_serial[1] }, 88 # ifdef CONFIG_SYS_NS16550_COM3 89 { "ns16550_serial", &am33xx_serial[2] }, 90 { "ns16550_serial", &am33xx_serial[3] }, 91 { "ns16550_serial", &am33xx_serial[4] }, 92 { "ns16550_serial", &am33xx_serial[5] }, 93 # endif 94 # endif 95 }; 96 97 #ifdef CONFIG_DM_I2C 98 static const struct omap_i2c_platdata am33xx_i2c[] = { 99 { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, 100 { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, 101 { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, 102 }; 103 104 U_BOOT_DEVICES(am33xx_i2c) = { 105 { "i2c_omap", &am33xx_i2c[0] }, 106 { "i2c_omap", &am33xx_i2c[1] }, 107 { "i2c_omap", &am33xx_i2c[2] }, 108 }; 109 #endif 110 111 #ifdef CONFIG_DM_GPIO 112 static const struct omap_gpio_platdata am33xx_gpio[] = { 113 { 0, AM33XX_GPIO0_BASE }, 114 { 1, AM33XX_GPIO1_BASE }, 115 { 2, AM33XX_GPIO2_BASE }, 116 { 3, AM33XX_GPIO3_BASE }, 117 #ifdef CONFIG_AM43XX 118 { 4, AM33XX_GPIO4_BASE }, 119 { 5, AM33XX_GPIO5_BASE }, 120 #endif 121 }; 122 123 U_BOOT_DEVICES(am33xx_gpios) = { 124 { "gpio_omap", &am33xx_gpio[0] }, 125 { "gpio_omap", &am33xx_gpio[1] }, 126 { "gpio_omap", &am33xx_gpio[2] }, 127 { "gpio_omap", &am33xx_gpio[3] }, 128 #ifdef CONFIG_AM43XX 129 { "gpio_omap", &am33xx_gpio[4] }, 130 { "gpio_omap", &am33xx_gpio[5] }, 131 #endif 132 }; 133 #endif 134 #endif 135 136 #ifndef CONFIG_DM_GPIO 137 static const struct gpio_bank gpio_bank_am33xx[] = { 138 { (void *)AM33XX_GPIO0_BASE }, 139 { (void *)AM33XX_GPIO1_BASE }, 140 { (void *)AM33XX_GPIO2_BASE }, 141 { (void *)AM33XX_GPIO3_BASE }, 142 #ifdef CONFIG_AM43XX 143 { (void *)AM33XX_GPIO4_BASE }, 144 { (void *)AM33XX_GPIO5_BASE }, 145 #endif 146 }; 147 148 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 149 #endif 150 151 #if defined(CONFIG_MMC_OMAP_HS) 152 int cpu_mmc_init(bd_t *bis) 153 { 154 int ret; 155 156 ret = omap_mmc_init(0, 0, 0, -1, -1); 157 if (ret) 158 return ret; 159 160 return omap_mmc_init(1, 0, 0, -1, -1); 161 } 162 #endif 163 164 /* 165 * RTC only with DDR in self-refresh mode magic value, checked against during 166 * boot to see if we have a valid config. This should be in sync with the value 167 * that will be in drivers/soc/ti/pm33xx.c. 168 */ 169 #define RTC_MAGIC_VAL 0x8cd0 170 171 /* Board type field bit shift for RTC only with DDR in self-refresh mode */ 172 #define RTC_BOARD_TYPE_SHIFT 16 173 174 /* AM33XX has two MUSB controllers which can be host or gadget */ 175 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 176 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 177 (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \ 178 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT)) 179 180 static struct musb_hdrc_config musb_config = { 181 .multipoint = 1, 182 .dyn_fifo = 1, 183 .num_eps = 16, 184 .ram_bits = 12, 185 }; 186 187 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL) 188 static struct ti_musb_platdata usb0 = { 189 .base = (void *)USB0_OTG_BASE, 190 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0, 191 .plat = { 192 .config = &musb_config, 193 .power = 50, 194 .platform_ops = &musb_dsps_ops, 195 }, 196 }; 197 198 static struct ti_musb_platdata usb1 = { 199 .base = (void *)USB1_OTG_BASE, 200 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1, 201 .plat = { 202 .config = &musb_config, 203 .power = 50, 204 .platform_ops = &musb_dsps_ops, 205 }, 206 }; 207 208 U_BOOT_DEVICES(am33xx_usbs) = { 209 #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL 210 { "ti-musb-peripheral", &usb0 }, 211 #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST 212 { "ti-musb-host", &usb0 }, 213 #endif 214 #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL 215 { "ti-musb-peripheral", &usb1 }, 216 #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST 217 { "ti-musb-host", &usb1 }, 218 #endif 219 }; 220 221 int arch_misc_init(void) 222 { 223 return 0; 224 } 225 #else 226 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 227 228 /* USB 2.0 PHY Control */ 229 #define CM_PHY_PWRDN (1 << 0) 230 #define CM_PHY_OTG_PWRDN (1 << 1) 231 #define OTGVDET_EN (1 << 19) 232 #define OTGSESSENDEN (1 << 20) 233 234 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 235 { 236 if (on) { 237 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 238 OTGVDET_EN | OTGSESSENDEN); 239 } else { 240 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 241 } 242 } 243 244 #ifdef CONFIG_AM335X_USB0 245 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 246 { 247 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 248 } 249 250 struct omap_musb_board_data otg0_board_data = { 251 .set_phy_power = am33xx_otg0_set_phy_power, 252 }; 253 254 static struct musb_hdrc_platform_data otg0_plat = { 255 .mode = CONFIG_AM335X_USB0_MODE, 256 .config = &musb_config, 257 .power = 50, 258 .platform_ops = &musb_dsps_ops, 259 .board_data = &otg0_board_data, 260 }; 261 #endif 262 263 #ifdef CONFIG_AM335X_USB1 264 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 265 { 266 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 267 } 268 269 struct omap_musb_board_data otg1_board_data = { 270 .set_phy_power = am33xx_otg1_set_phy_power, 271 }; 272 273 static struct musb_hdrc_platform_data otg1_plat = { 274 .mode = CONFIG_AM335X_USB1_MODE, 275 .config = &musb_config, 276 .power = 50, 277 .platform_ops = &musb_dsps_ops, 278 .board_data = &otg1_board_data, 279 }; 280 #endif 281 282 int arch_misc_init(void) 283 { 284 #ifdef CONFIG_AM335X_USB0 285 musb_register(&otg0_plat, &otg0_board_data, 286 (void *)USB0_OTG_BASE); 287 #endif 288 #ifdef CONFIG_AM335X_USB1 289 musb_register(&otg1_plat, &otg1_board_data, 290 (void *)USB1_OTG_BASE); 291 #endif 292 return 0; 293 } 294 #endif 295 296 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 297 298 int arch_misc_init(void) 299 { 300 struct udevice *dev; 301 int ret; 302 303 ret = uclass_first_device(UCLASS_MISC, &dev); 304 if (ret || !dev) 305 return ret; 306 307 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 308 ret = usb_ether_init(); 309 if (ret) { 310 pr_err("USB ether init failed\n"); 311 return ret; 312 } 313 #endif 314 315 return 0; 316 } 317 318 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 319 320 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 321 322 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 323 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 324 static void rtc32k_unlock(struct davinci_rtc *rtc) 325 { 326 /* 327 * Unlock the RTC's registers. For more details please see the 328 * RTC_SS section of the TRM. In order to unlock we need to 329 * write these specific values (keys) in this order. 330 */ 331 writel(RTC_KICK0R_WE, &rtc->kick0r); 332 writel(RTC_KICK1R_WE, &rtc->kick1r); 333 } 334 #endif 335 336 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 337 /* 338 * Write contents of the RTC_SCRATCH1 register based on board type 339 * Two things are passed 340 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 341 * control gets to kernel, kernel reads the scratchpad register and gets to 342 * know that bootloader has rtc_only support. 343 * 344 * Second important thing is the board type (16:31). This is needed in the 345 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 346 * identify the board type and we go ahead and copy the board strings to 347 * am43xx_board_name. 348 */ 349 void update_rtc_magic(void) 350 { 351 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 352 u32 magic = RTC_MAGIC_VAL; 353 354 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 355 356 rtc32k_unlock(rtc); 357 358 /* write magic */ 359 writel(magic, &rtc->scratch1); 360 } 361 #endif 362 363 /* 364 * In the case of non-SPL based booting we'll want to call these 365 * functions a tiny bit later as it will require gd to be set and cleared 366 * and that's not true in s_init in this case so we cannot do it there. 367 */ 368 int board_early_init_f(void) 369 { 370 prcm_init(); 371 set_mux_conf_regs(); 372 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 373 update_rtc_magic(); 374 #endif 375 return 0; 376 } 377 378 /* 379 * This function is the place to do per-board things such as ramp up the 380 * MPU clock frequency. 381 */ 382 __weak void am33xx_spl_board_init(void) 383 { 384 } 385 386 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 387 static void rtc32k_enable(void) 388 { 389 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 390 391 rtc32k_unlock(rtc); 392 393 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 394 writel((1 << 3) | (1 << 6), &rtc->osc); 395 } 396 #endif 397 398 static void uart_soft_reset(void) 399 { 400 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 401 u32 regval; 402 403 regval = readl(&uart_base->uartsyscfg); 404 regval |= UART_RESET; 405 writel(regval, &uart_base->uartsyscfg); 406 while ((readl(&uart_base->uartsyssts) & 407 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 408 ; 409 410 /* Disable smart idle */ 411 regval = readl(&uart_base->uartsyscfg); 412 regval |= UART_SMART_IDLE_EN; 413 writel(regval, &uart_base->uartsyscfg); 414 } 415 416 static void watchdog_disable(void) 417 { 418 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 419 420 writel(0xAAAA, &wdtimer->wdtwspr); 421 while (readl(&wdtimer->wdtwwps) != 0x0) 422 ; 423 writel(0x5555, &wdtimer->wdtwspr); 424 while (readl(&wdtimer->wdtwwps) != 0x0) 425 ; 426 } 427 428 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 429 /* 430 * Check if we are executing rtc-only + DDR mode, and resume from it if needed 431 */ 432 static void rtc_only(void) 433 { 434 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 435 struct prm_device_inst *prm_device = 436 (struct prm_device_inst *)PRM_DEVICE_INST; 437 438 u32 scratch1; 439 void (*resume_func)(void); 440 441 scratch1 = readl(&rtc->scratch1); 442 443 /* 444 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 445 * written to this register when we want to wake up from RTC only 446 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 447 * bits 0-15: RTC_MAGIC_VAL 448 * bits 16-31: board type (needed for sdram_init) 449 */ 450 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 451 return; 452 453 rtc32k_unlock(rtc); 454 455 /* Clear RTC magic */ 456 writel(0, &rtc->scratch1); 457 458 /* 459 * Update board type based on value stored on RTC_SCRATCH1, this 460 * is done so that we don't need to read the board type from eeprom 461 * over i2c bus which is expensive 462 */ 463 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 464 465 /* 466 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 467 * are resuming from self-refresh. This avoids an unnecessary re-init 468 * of the DDR. The re-init takes time and we would need to wait for 469 * it to complete before accessing DDR to avoid L3 NOC errors. 470 */ 471 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 472 473 rtc_only_prcm_init(); 474 sdram_init(); 475 476 /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ 477 writel(0, &prm_device->emif_ctrl); 478 479 resume_func = (void *)readl(&rtc->scratch0); 480 if (resume_func) 481 resume_func(); 482 } 483 #endif 484 485 void s_init(void) 486 { 487 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 488 rtc_only(); 489 #endif 490 } 491 492 void early_system_init(void) 493 { 494 /* 495 * The ROM will only have set up sufficient pinmux to allow for the 496 * first 4KiB NOR to be read, we must finish doing what we know of 497 * the NOR mux in this space in order to continue. 498 */ 499 #ifdef CONFIG_NOR_BOOT 500 enable_norboot_pin_mux(); 501 #endif 502 watchdog_disable(); 503 set_uart_mux_conf(); 504 setup_early_clocks(); 505 uart_soft_reset(); 506 #ifdef CONFIG_SPL_BUILD 507 /* 508 * Save the boot parameters passed from romcode. 509 * We cannot delay the saving further than this, 510 * to prevent overwrites. 511 */ 512 save_omap_boot_params(); 513 #endif 514 #ifdef CONFIG_DEBUG_UART_OMAP 515 debug_uart_init(); 516 #endif 517 518 #ifdef CONFIG_SPL_BUILD 519 spl_early_init(); 520 #endif 521 522 #ifdef CONFIG_TI_I2C_BOARD_DETECT 523 do_board_detect(); 524 #endif 525 526 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 527 /* Enable RTC32K clock */ 528 rtc32k_enable(); 529 #endif 530 } 531 532 #ifdef CONFIG_SPL_BUILD 533 void board_init_f(ulong dummy) 534 { 535 hw_data_init(); 536 early_system_init(); 537 board_early_init_f(); 538 sdram_init(); 539 /* dram_init must store complete ramsize in gd->ram_size */ 540 gd->ram_size = get_ram_size( 541 (void *)CONFIG_SYS_SDRAM_BASE, 542 CONFIG_MAX_RAM_BANK_SIZE); 543 } 544 #endif 545 546 #endif 547 548 int arch_cpu_init_dm(void) 549 { 550 hw_data_init(); 551 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 552 early_system_init(); 553 #endif 554 return 0; 555 } 556