1 /* 2 * board.c 3 * 4 * Common board functions for AM33XX based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <ns16550.h> 15 #include <spl.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mem.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/io.h> 26 #include <asm/emif.h> 27 #include <asm/gpio.h> 28 #include <i2c.h> 29 #include <miiphy.h> 30 #include <cpsw.h> 31 #include <linux/errno.h> 32 #include <linux/compiler.h> 33 #include <linux/usb/ch9.h> 34 #include <linux/usb/gadget.h> 35 #include <linux/usb/musb.h> 36 #include <asm/omap_musb.h> 37 #include <asm/davinci_rtc.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 #if !CONFIG_IS_ENABLED(OF_CONTROL) 42 static const struct ns16550_platdata am33xx_serial[] = { 43 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 44 # ifdef CONFIG_SYS_NS16550_COM2 45 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 46 # ifdef CONFIG_SYS_NS16550_COM3 47 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 48 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 49 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 50 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 51 # endif 52 # endif 53 }; 54 55 U_BOOT_DEVICES(am33xx_uarts) = { 56 { "ns16550_serial", &am33xx_serial[0] }, 57 # ifdef CONFIG_SYS_NS16550_COM2 58 { "ns16550_serial", &am33xx_serial[1] }, 59 # ifdef CONFIG_SYS_NS16550_COM3 60 { "ns16550_serial", &am33xx_serial[2] }, 61 { "ns16550_serial", &am33xx_serial[3] }, 62 { "ns16550_serial", &am33xx_serial[4] }, 63 { "ns16550_serial", &am33xx_serial[5] }, 64 # endif 65 # endif 66 }; 67 68 #ifdef CONFIG_DM_GPIO 69 static const struct omap_gpio_platdata am33xx_gpio[] = { 70 { 0, AM33XX_GPIO0_BASE }, 71 { 1, AM33XX_GPIO1_BASE }, 72 { 2, AM33XX_GPIO2_BASE }, 73 { 3, AM33XX_GPIO3_BASE }, 74 #ifdef CONFIG_AM43XX 75 { 4, AM33XX_GPIO4_BASE }, 76 { 5, AM33XX_GPIO5_BASE }, 77 #endif 78 }; 79 80 U_BOOT_DEVICES(am33xx_gpios) = { 81 { "gpio_omap", &am33xx_gpio[0] }, 82 { "gpio_omap", &am33xx_gpio[1] }, 83 { "gpio_omap", &am33xx_gpio[2] }, 84 { "gpio_omap", &am33xx_gpio[3] }, 85 #ifdef CONFIG_AM43XX 86 { "gpio_omap", &am33xx_gpio[4] }, 87 { "gpio_omap", &am33xx_gpio[5] }, 88 #endif 89 }; 90 #endif 91 #endif 92 93 #ifndef CONFIG_DM_GPIO 94 static const struct gpio_bank gpio_bank_am33xx[] = { 95 { (void *)AM33XX_GPIO0_BASE }, 96 { (void *)AM33XX_GPIO1_BASE }, 97 { (void *)AM33XX_GPIO2_BASE }, 98 { (void *)AM33XX_GPIO3_BASE }, 99 #ifdef CONFIG_AM43XX 100 { (void *)AM33XX_GPIO4_BASE }, 101 { (void *)AM33XX_GPIO5_BASE }, 102 #endif 103 }; 104 105 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 106 #endif 107 108 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) 109 int cpu_mmc_init(bd_t *bis) 110 { 111 int ret; 112 113 ret = omap_mmc_init(0, 0, 0, -1, -1); 114 if (ret) 115 return ret; 116 117 return omap_mmc_init(1, 0, 0, -1, -1); 118 } 119 #endif 120 121 /* AM33XX has two MUSB controllers which can be host or gadget */ 122 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 123 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) 124 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 125 126 /* USB 2.0 PHY Control */ 127 #define CM_PHY_PWRDN (1 << 0) 128 #define CM_PHY_OTG_PWRDN (1 << 1) 129 #define OTGVDET_EN (1 << 19) 130 #define OTGSESSENDEN (1 << 20) 131 132 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 133 { 134 if (on) { 135 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 136 OTGVDET_EN | OTGSESSENDEN); 137 } else { 138 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 139 } 140 } 141 142 static struct musb_hdrc_config musb_config = { 143 .multipoint = 1, 144 .dyn_fifo = 1, 145 .num_eps = 16, 146 .ram_bits = 12, 147 }; 148 149 #ifdef CONFIG_AM335X_USB0 150 static void am33xx_otg0_set_phy_power(u8 on) 151 { 152 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 153 } 154 155 struct omap_musb_board_data otg0_board_data = { 156 .set_phy_power = am33xx_otg0_set_phy_power, 157 }; 158 159 static struct musb_hdrc_platform_data otg0_plat = { 160 .mode = CONFIG_AM335X_USB0_MODE, 161 .config = &musb_config, 162 .power = 50, 163 .platform_ops = &musb_dsps_ops, 164 .board_data = &otg0_board_data, 165 }; 166 #endif 167 168 #ifdef CONFIG_AM335X_USB1 169 static void am33xx_otg1_set_phy_power(u8 on) 170 { 171 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 172 } 173 174 struct omap_musb_board_data otg1_board_data = { 175 .set_phy_power = am33xx_otg1_set_phy_power, 176 }; 177 178 static struct musb_hdrc_platform_data otg1_plat = { 179 .mode = CONFIG_AM335X_USB1_MODE, 180 .config = &musb_config, 181 .power = 50, 182 .platform_ops = &musb_dsps_ops, 183 .board_data = &otg1_board_data, 184 }; 185 #endif 186 #endif 187 188 int arch_misc_init(void) 189 { 190 #ifdef CONFIG_AM335X_USB0 191 musb_register(&otg0_plat, &otg0_board_data, 192 (void *)USB0_OTG_BASE); 193 #endif 194 #ifdef CONFIG_AM335X_USB1 195 musb_register(&otg1_plat, &otg1_board_data, 196 (void *)USB1_OTG_BASE); 197 #endif 198 return 0; 199 } 200 201 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 202 /* 203 * In the case of non-SPL based booting we'll want to call these 204 * functions a tiny bit later as it will require gd to be set and cleared 205 * and that's not true in s_init in this case so we cannot do it there. 206 */ 207 int board_early_init_f(void) 208 { 209 prcm_init(); 210 set_mux_conf_regs(); 211 212 return 0; 213 } 214 215 /* 216 * This function is the place to do per-board things such as ramp up the 217 * MPU clock frequency. 218 */ 219 __weak void am33xx_spl_board_init(void) 220 { 221 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 222 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 223 } 224 225 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 226 static void rtc32k_enable(void) 227 { 228 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 229 230 /* 231 * Unlock the RTC's registers. For more details please see the 232 * RTC_SS section of the TRM. In order to unlock we need to 233 * write these specific values (keys) in this order. 234 */ 235 writel(RTC_KICK0R_WE, &rtc->kick0r); 236 writel(RTC_KICK1R_WE, &rtc->kick1r); 237 238 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 239 writel((1 << 3) | (1 << 6), &rtc->osc); 240 } 241 #endif 242 243 static void uart_soft_reset(void) 244 { 245 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 246 u32 regval; 247 248 regval = readl(&uart_base->uartsyscfg); 249 regval |= UART_RESET; 250 writel(regval, &uart_base->uartsyscfg); 251 while ((readl(&uart_base->uartsyssts) & 252 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 253 ; 254 255 /* Disable smart idle */ 256 regval = readl(&uart_base->uartsyscfg); 257 regval |= UART_SMART_IDLE_EN; 258 writel(regval, &uart_base->uartsyscfg); 259 } 260 261 static void watchdog_disable(void) 262 { 263 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 264 265 writel(0xAAAA, &wdtimer->wdtwspr); 266 while (readl(&wdtimer->wdtwwps) != 0x0) 267 ; 268 writel(0x5555, &wdtimer->wdtwspr); 269 while (readl(&wdtimer->wdtwwps) != 0x0) 270 ; 271 } 272 273 void s_init(void) 274 { 275 } 276 277 void early_system_init(void) 278 { 279 /* 280 * The ROM will only have set up sufficient pinmux to allow for the 281 * first 4KiB NOR to be read, we must finish doing what we know of 282 * the NOR mux in this space in order to continue. 283 */ 284 #ifdef CONFIG_NOR_BOOT 285 enable_norboot_pin_mux(); 286 #endif 287 watchdog_disable(); 288 set_uart_mux_conf(); 289 setup_early_clocks(); 290 uart_soft_reset(); 291 #ifdef CONFIG_TI_I2C_BOARD_DETECT 292 do_board_detect(); 293 #endif 294 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 295 /* Enable RTC32K clock */ 296 rtc32k_enable(); 297 #endif 298 } 299 300 #ifdef CONFIG_SPL_BUILD 301 void board_init_f(ulong dummy) 302 { 303 early_system_init(); 304 board_early_init_f(); 305 sdram_init(); 306 } 307 #endif 308 309 #endif 310 311 int arch_cpu_init_dm(void) 312 { 313 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 314 early_system_init(); 315 #endif 316 return 0; 317 } 318