1 /*
2  * board.c
3  *
4  * Common board functions for AM33XX based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <ns16550.h>
15 #include <spl.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <i2c.h>
29 #include <miiphy.h>
30 #include <cpsw.h>
31 #include <linux/errno.h>
32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h>
38 
39 DECLARE_GLOBAL_DATA_PTR;
40 
41 #if !CONFIG_IS_ENABLED(OF_CONTROL)
42 static const struct ns16550_platdata am33xx_serial[] = {
43 	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
44 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
45 # ifdef CONFIG_SYS_NS16550_COM2
46 	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
47 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
48 #  ifdef CONFIG_SYS_NS16550_COM3
49 	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
50 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
51 	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
52 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
53 	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
54 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
55 	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
56 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
57 #  endif
58 # endif
59 };
60 
61 U_BOOT_DEVICES(am33xx_uarts) = {
62 	{ "ns16550_serial", &am33xx_serial[0] },
63 #  ifdef CONFIG_SYS_NS16550_COM2
64 	{ "ns16550_serial", &am33xx_serial[1] },
65 #   ifdef CONFIG_SYS_NS16550_COM3
66 	{ "ns16550_serial", &am33xx_serial[2] },
67 	{ "ns16550_serial", &am33xx_serial[3] },
68 	{ "ns16550_serial", &am33xx_serial[4] },
69 	{ "ns16550_serial", &am33xx_serial[5] },
70 #   endif
71 #  endif
72 };
73 
74 #ifdef CONFIG_DM_GPIO
75 static const struct omap_gpio_platdata am33xx_gpio[] = {
76 	{ 0, AM33XX_GPIO0_BASE },
77 	{ 1, AM33XX_GPIO1_BASE },
78 	{ 2, AM33XX_GPIO2_BASE },
79 	{ 3, AM33XX_GPIO3_BASE },
80 #ifdef CONFIG_AM43XX
81 	{ 4, AM33XX_GPIO4_BASE },
82 	{ 5, AM33XX_GPIO5_BASE },
83 #endif
84 };
85 
86 U_BOOT_DEVICES(am33xx_gpios) = {
87 	{ "gpio_omap", &am33xx_gpio[0] },
88 	{ "gpio_omap", &am33xx_gpio[1] },
89 	{ "gpio_omap", &am33xx_gpio[2] },
90 	{ "gpio_omap", &am33xx_gpio[3] },
91 #ifdef CONFIG_AM43XX
92 	{ "gpio_omap", &am33xx_gpio[4] },
93 	{ "gpio_omap", &am33xx_gpio[5] },
94 #endif
95 };
96 #endif
97 #endif
98 
99 #ifndef CONFIG_DM_GPIO
100 static const struct gpio_bank gpio_bank_am33xx[] = {
101 	{ (void *)AM33XX_GPIO0_BASE },
102 	{ (void *)AM33XX_GPIO1_BASE },
103 	{ (void *)AM33XX_GPIO2_BASE },
104 	{ (void *)AM33XX_GPIO3_BASE },
105 #ifdef CONFIG_AM43XX
106 	{ (void *)AM33XX_GPIO4_BASE },
107 	{ (void *)AM33XX_GPIO5_BASE },
108 #endif
109 };
110 
111 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
112 #endif
113 
114 #if defined(CONFIG_MMC_OMAP_HS)
115 int cpu_mmc_init(bd_t *bis)
116 {
117 	int ret;
118 
119 	ret = omap_mmc_init(0, 0, 0, -1, -1);
120 	if (ret)
121 		return ret;
122 
123 	return omap_mmc_init(1, 0, 0, -1, -1);
124 }
125 #endif
126 
127 /* AM33XX has two MUSB controllers which can be host or gadget */
128 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
129 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
130 	(!defined(CONFIG_DM_USB))
131 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
132 
133 /* USB 2.0 PHY Control */
134 #define CM_PHY_PWRDN			(1 << 0)
135 #define CM_PHY_OTG_PWRDN		(1 << 1)
136 #define OTGVDET_EN			(1 << 19)
137 #define OTGSESSENDEN			(1 << 20)
138 
139 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
140 {
141 	if (on) {
142 		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
143 				OTGVDET_EN | OTGSESSENDEN);
144 	} else {
145 		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
146 	}
147 }
148 
149 static struct musb_hdrc_config musb_config = {
150 	.multipoint     = 1,
151 	.dyn_fifo       = 1,
152 	.num_eps        = 16,
153 	.ram_bits       = 12,
154 };
155 
156 #ifdef CONFIG_AM335X_USB0
157 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
158 {
159 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
160 }
161 
162 struct omap_musb_board_data otg0_board_data = {
163 	.set_phy_power = am33xx_otg0_set_phy_power,
164 };
165 
166 static struct musb_hdrc_platform_data otg0_plat = {
167 	.mode           = CONFIG_AM335X_USB0_MODE,
168 	.config         = &musb_config,
169 	.power          = 50,
170 	.platform_ops	= &musb_dsps_ops,
171 	.board_data	= &otg0_board_data,
172 };
173 #endif
174 
175 #ifdef CONFIG_AM335X_USB1
176 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
177 {
178 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
179 }
180 
181 struct omap_musb_board_data otg1_board_data = {
182 	.set_phy_power = am33xx_otg1_set_phy_power,
183 };
184 
185 static struct musb_hdrc_platform_data otg1_plat = {
186 	.mode           = CONFIG_AM335X_USB1_MODE,
187 	.config         = &musb_config,
188 	.power          = 50,
189 	.platform_ops	= &musb_dsps_ops,
190 	.board_data	= &otg1_board_data,
191 };
192 #endif
193 #endif
194 
195 int arch_misc_init(void)
196 {
197 #ifndef CONFIG_DM_USB
198 #ifdef CONFIG_AM335X_USB0
199 	musb_register(&otg0_plat, &otg0_board_data,
200 		(void *)USB0_OTG_BASE);
201 #endif
202 #ifdef CONFIG_AM335X_USB1
203 	musb_register(&otg1_plat, &otg1_board_data,
204 		(void *)USB1_OTG_BASE);
205 #endif
206 #else
207 	struct udevice *dev;
208 	int ret;
209 
210 	ret = uclass_first_device(UCLASS_MISC, &dev);
211 	if (ret || !dev)
212 		return ret;
213 
214 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
215 	ret = usb_ether_init();
216 	if (ret) {
217 		error("USB ether init failed\n");
218 		return ret;
219 	}
220 #endif
221 #endif
222 	return 0;
223 }
224 
225 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
226 /*
227  * In the case of non-SPL based booting we'll want to call these
228  * functions a tiny bit later as it will require gd to be set and cleared
229  * and that's not true in s_init in this case so we cannot do it there.
230  */
231 int board_early_init_f(void)
232 {
233 	prcm_init();
234 	set_mux_conf_regs();
235 
236 	return 0;
237 }
238 
239 /*
240  * This function is the place to do per-board things such as ramp up the
241  * MPU clock frequency.
242  */
243 __weak void am33xx_spl_board_init(void)
244 {
245 	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
246 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
247 }
248 
249 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
250 static void rtc32k_enable(void)
251 {
252 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
253 
254 	/*
255 	 * Unlock the RTC's registers.  For more details please see the
256 	 * RTC_SS section of the TRM.  In order to unlock we need to
257 	 * write these specific values (keys) in this order.
258 	 */
259 	writel(RTC_KICK0R_WE, &rtc->kick0r);
260 	writel(RTC_KICK1R_WE, &rtc->kick1r);
261 
262 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
263 	writel((1 << 3) | (1 << 6), &rtc->osc);
264 }
265 #endif
266 
267 static void uart_soft_reset(void)
268 {
269 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
270 	u32 regval;
271 
272 	regval = readl(&uart_base->uartsyscfg);
273 	regval |= UART_RESET;
274 	writel(regval, &uart_base->uartsyscfg);
275 	while ((readl(&uart_base->uartsyssts) &
276 		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
277 		;
278 
279 	/* Disable smart idle */
280 	regval = readl(&uart_base->uartsyscfg);
281 	regval |= UART_SMART_IDLE_EN;
282 	writel(regval, &uart_base->uartsyscfg);
283 }
284 
285 static void watchdog_disable(void)
286 {
287 	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
288 
289 	writel(0xAAAA, &wdtimer->wdtwspr);
290 	while (readl(&wdtimer->wdtwwps) != 0x0)
291 		;
292 	writel(0x5555, &wdtimer->wdtwspr);
293 	while (readl(&wdtimer->wdtwwps) != 0x0)
294 		;
295 }
296 
297 void s_init(void)
298 {
299 }
300 
301 void early_system_init(void)
302 {
303 	/*
304 	 * The ROM will only have set up sufficient pinmux to allow for the
305 	 * first 4KiB NOR to be read, we must finish doing what we know of
306 	 * the NOR mux in this space in order to continue.
307 	 */
308 #ifdef CONFIG_NOR_BOOT
309 	enable_norboot_pin_mux();
310 #endif
311 	watchdog_disable();
312 	set_uart_mux_conf();
313 	setup_early_clocks();
314 	uart_soft_reset();
315 #ifdef CONFIG_TI_I2C_BOARD_DETECT
316 	do_board_detect();
317 #endif
318 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
319 	/* Enable RTC32K clock */
320 	rtc32k_enable();
321 #endif
322 }
323 
324 #ifdef CONFIG_SPL_BUILD
325 void board_init_f(ulong dummy)
326 {
327 	early_system_init();
328 	board_early_init_f();
329 	sdram_init();
330 	/* dram_init must store complete ramsize in gd->ram_size */
331 	gd->ram_size = get_ram_size(
332 			(void *)CONFIG_SYS_SDRAM_BASE,
333 			CONFIG_MAX_RAM_BANK_SIZE);
334 }
335 #endif
336 
337 #endif
338 
339 int arch_cpu_init_dm(void)
340 {
341 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
342 	early_system_init();
343 #endif
344 	return 0;
345 }
346