1 /* 2 * board.c 3 * 4 * Common board functions for AM33XX based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <debug_uart.h> 14 #include <errno.h> 15 #include <ns16550.h> 16 #include <spl.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/omap.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/mem.h> 24 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <asm/omap_common.h> 30 #include <i2c.h> 31 #include <miiphy.h> 32 #include <cpsw.h> 33 #include <linux/errno.h> 34 #include <linux/compiler.h> 35 #include <linux/usb/ch9.h> 36 #include <linux/usb/gadget.h> 37 #include <linux/usb/musb.h> 38 #include <asm/omap_musb.h> 39 #include <asm/davinci_rtc.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int dram_init(void) 44 { 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 46 sdram_init(); 47 #endif 48 49 /* dram_init must store complete ramsize in gd->ram_size */ 50 gd->ram_size = get_ram_size( 51 (void *)CONFIG_SYS_SDRAM_BASE, 52 CONFIG_MAX_RAM_BANK_SIZE); 53 return 0; 54 } 55 56 int dram_init_banksize(void) 57 { 58 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 59 gd->bd->bi_dram[0].size = gd->ram_size; 60 61 return 0; 62 } 63 64 #if !CONFIG_IS_ENABLED(OF_CONTROL) 65 static const struct ns16550_platdata am33xx_serial[] = { 66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 67 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 68 # ifdef CONFIG_SYS_NS16550_COM2 69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 70 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 71 # ifdef CONFIG_SYS_NS16550_COM3 72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 73 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 75 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 77 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 79 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 80 # endif 81 # endif 82 }; 83 84 U_BOOT_DEVICES(am33xx_uarts) = { 85 { "ns16550_serial", &am33xx_serial[0] }, 86 # ifdef CONFIG_SYS_NS16550_COM2 87 { "ns16550_serial", &am33xx_serial[1] }, 88 # ifdef CONFIG_SYS_NS16550_COM3 89 { "ns16550_serial", &am33xx_serial[2] }, 90 { "ns16550_serial", &am33xx_serial[3] }, 91 { "ns16550_serial", &am33xx_serial[4] }, 92 { "ns16550_serial", &am33xx_serial[5] }, 93 # endif 94 # endif 95 }; 96 97 #ifdef CONFIG_DM_GPIO 98 static const struct omap_gpio_platdata am33xx_gpio[] = { 99 { 0, AM33XX_GPIO0_BASE }, 100 { 1, AM33XX_GPIO1_BASE }, 101 { 2, AM33XX_GPIO2_BASE }, 102 { 3, AM33XX_GPIO3_BASE }, 103 #ifdef CONFIG_AM43XX 104 { 4, AM33XX_GPIO4_BASE }, 105 { 5, AM33XX_GPIO5_BASE }, 106 #endif 107 }; 108 109 U_BOOT_DEVICES(am33xx_gpios) = { 110 { "gpio_omap", &am33xx_gpio[0] }, 111 { "gpio_omap", &am33xx_gpio[1] }, 112 { "gpio_omap", &am33xx_gpio[2] }, 113 { "gpio_omap", &am33xx_gpio[3] }, 114 #ifdef CONFIG_AM43XX 115 { "gpio_omap", &am33xx_gpio[4] }, 116 { "gpio_omap", &am33xx_gpio[5] }, 117 #endif 118 }; 119 #endif 120 #endif 121 122 #ifndef CONFIG_DM_GPIO 123 static const struct gpio_bank gpio_bank_am33xx[] = { 124 { (void *)AM33XX_GPIO0_BASE }, 125 { (void *)AM33XX_GPIO1_BASE }, 126 { (void *)AM33XX_GPIO2_BASE }, 127 { (void *)AM33XX_GPIO3_BASE }, 128 #ifdef CONFIG_AM43XX 129 { (void *)AM33XX_GPIO4_BASE }, 130 { (void *)AM33XX_GPIO5_BASE }, 131 #endif 132 }; 133 134 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 135 #endif 136 137 #if defined(CONFIG_MMC_OMAP_HS) 138 int cpu_mmc_init(bd_t *bis) 139 { 140 int ret; 141 142 ret = omap_mmc_init(0, 0, 0, -1, -1); 143 if (ret) 144 return ret; 145 146 return omap_mmc_init(1, 0, 0, -1, -1); 147 } 148 #endif 149 150 /* 151 * RTC only with DDR in self-refresh mode magic value, checked against during 152 * boot to see if we have a valid config. This should be in sync with the value 153 * that will be in drivers/soc/ti/pm33xx.c. 154 */ 155 #define RTC_MAGIC_VAL 0x8cd0 156 157 /* Board type field bit shift for RTC only with DDR in self-refresh mode */ 158 #define RTC_BOARD_TYPE_SHIFT 16 159 160 /* AM33XX has two MUSB controllers which can be host or gadget */ 161 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 162 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 163 (!defined(CONFIG_DM_USB)) 164 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 165 166 /* USB 2.0 PHY Control */ 167 #define CM_PHY_PWRDN (1 << 0) 168 #define CM_PHY_OTG_PWRDN (1 << 1) 169 #define OTGVDET_EN (1 << 19) 170 #define OTGSESSENDEN (1 << 20) 171 172 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 173 { 174 if (on) { 175 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 176 OTGVDET_EN | OTGSESSENDEN); 177 } else { 178 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 179 } 180 } 181 182 static struct musb_hdrc_config musb_config = { 183 .multipoint = 1, 184 .dyn_fifo = 1, 185 .num_eps = 16, 186 .ram_bits = 12, 187 }; 188 189 #ifdef CONFIG_AM335X_USB0 190 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 191 { 192 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 193 } 194 195 struct omap_musb_board_data otg0_board_data = { 196 .set_phy_power = am33xx_otg0_set_phy_power, 197 }; 198 199 static struct musb_hdrc_platform_data otg0_plat = { 200 .mode = CONFIG_AM335X_USB0_MODE, 201 .config = &musb_config, 202 .power = 50, 203 .platform_ops = &musb_dsps_ops, 204 .board_data = &otg0_board_data, 205 }; 206 #endif 207 208 #ifdef CONFIG_AM335X_USB1 209 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 210 { 211 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 212 } 213 214 struct omap_musb_board_data otg1_board_data = { 215 .set_phy_power = am33xx_otg1_set_phy_power, 216 }; 217 218 static struct musb_hdrc_platform_data otg1_plat = { 219 .mode = CONFIG_AM335X_USB1_MODE, 220 .config = &musb_config, 221 .power = 50, 222 .platform_ops = &musb_dsps_ops, 223 .board_data = &otg1_board_data, 224 }; 225 #endif 226 227 int arch_misc_init(void) 228 { 229 #ifdef CONFIG_AM335X_USB0 230 musb_register(&otg0_plat, &otg0_board_data, 231 (void *)USB0_OTG_BASE); 232 #endif 233 #ifdef CONFIG_AM335X_USB1 234 musb_register(&otg1_plat, &otg1_board_data, 235 (void *)USB1_OTG_BASE); 236 #endif 237 return 0; 238 } 239 240 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 241 242 int arch_misc_init(void) 243 { 244 struct udevice *dev; 245 int ret; 246 247 ret = uclass_first_device(UCLASS_MISC, &dev); 248 if (ret || !dev) 249 return ret; 250 251 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 252 ret = usb_ether_init(); 253 if (ret) { 254 pr_err("USB ether init failed\n"); 255 return ret; 256 } 257 #endif 258 259 return 0; 260 } 261 262 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 263 264 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 265 266 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 267 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 268 static void rtc32k_unlock(struct davinci_rtc *rtc) 269 { 270 /* 271 * Unlock the RTC's registers. For more details please see the 272 * RTC_SS section of the TRM. In order to unlock we need to 273 * write these specific values (keys) in this order. 274 */ 275 writel(RTC_KICK0R_WE, &rtc->kick0r); 276 writel(RTC_KICK1R_WE, &rtc->kick1r); 277 } 278 #endif 279 280 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 281 /* 282 * Write contents of the RTC_SCRATCH1 register based on board type 283 * Two things are passed 284 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 285 * control gets to kernel, kernel reads the scratchpad register and gets to 286 * know that bootloader has rtc_only support. 287 * 288 * Second important thing is the board type (16:31). This is needed in the 289 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 290 * identify the board type and we go ahead and copy the board strings to 291 * am43xx_board_name. 292 */ 293 void update_rtc_magic(void) 294 { 295 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 296 u32 magic = RTC_MAGIC_VAL; 297 298 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 299 300 rtc32k_unlock(rtc); 301 302 /* write magic */ 303 writel(magic, &rtc->scratch1); 304 } 305 #endif 306 307 /* 308 * In the case of non-SPL based booting we'll want to call these 309 * functions a tiny bit later as it will require gd to be set and cleared 310 * and that's not true in s_init in this case so we cannot do it there. 311 */ 312 int board_early_init_f(void) 313 { 314 prcm_init(); 315 set_mux_conf_regs(); 316 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 317 update_rtc_magic(); 318 #endif 319 return 0; 320 } 321 322 /* 323 * This function is the place to do per-board things such as ramp up the 324 * MPU clock frequency. 325 */ 326 __weak void am33xx_spl_board_init(void) 327 { 328 } 329 330 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 331 static void rtc32k_enable(void) 332 { 333 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 334 335 rtc32k_unlock(rtc); 336 337 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 338 writel((1 << 3) | (1 << 6), &rtc->osc); 339 } 340 #endif 341 342 static void uart_soft_reset(void) 343 { 344 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 345 u32 regval; 346 347 regval = readl(&uart_base->uartsyscfg); 348 regval |= UART_RESET; 349 writel(regval, &uart_base->uartsyscfg); 350 while ((readl(&uart_base->uartsyssts) & 351 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 352 ; 353 354 /* Disable smart idle */ 355 regval = readl(&uart_base->uartsyscfg); 356 regval |= UART_SMART_IDLE_EN; 357 writel(regval, &uart_base->uartsyscfg); 358 } 359 360 static void watchdog_disable(void) 361 { 362 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 363 364 writel(0xAAAA, &wdtimer->wdtwspr); 365 while (readl(&wdtimer->wdtwwps) != 0x0) 366 ; 367 writel(0x5555, &wdtimer->wdtwspr); 368 while (readl(&wdtimer->wdtwwps) != 0x0) 369 ; 370 } 371 372 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 373 /* 374 * Check if we are executing rtc-only + DDR mode, and resume from it if needed 375 */ 376 static void rtc_only(void) 377 { 378 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 379 struct prm_device_inst *prm_device = 380 (struct prm_device_inst *)PRM_DEVICE_INST; 381 382 u32 scratch1; 383 void (*resume_func)(void); 384 385 scratch1 = readl(&rtc->scratch1); 386 387 /* 388 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 389 * written to this register when we want to wake up from RTC only 390 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 391 * bits 0-15: RTC_MAGIC_VAL 392 * bits 16-31: board type (needed for sdram_init) 393 */ 394 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 395 return; 396 397 rtc32k_unlock(rtc); 398 399 /* Clear RTC magic */ 400 writel(0, &rtc->scratch1); 401 402 /* 403 * Update board type based on value stored on RTC_SCRATCH1, this 404 * is done so that we don't need to read the board type from eeprom 405 * over i2c bus which is expensive 406 */ 407 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 408 409 /* 410 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 411 * are resuming from self-refresh. This avoids an unnecessary re-init 412 * of the DDR. The re-init takes time and we would need to wait for 413 * it to complete before accessing DDR to avoid L3 NOC errors. 414 */ 415 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 416 417 rtc_only_prcm_init(); 418 sdram_init(); 419 420 /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ 421 writel(0, &prm_device->emif_ctrl); 422 423 resume_func = (void *)readl(&rtc->scratch0); 424 if (resume_func) 425 resume_func(); 426 } 427 #endif 428 429 void s_init(void) 430 { 431 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 432 rtc_only(); 433 #endif 434 } 435 436 void early_system_init(void) 437 { 438 /* 439 * The ROM will only have set up sufficient pinmux to allow for the 440 * first 4KiB NOR to be read, we must finish doing what we know of 441 * the NOR mux in this space in order to continue. 442 */ 443 #ifdef CONFIG_NOR_BOOT 444 enable_norboot_pin_mux(); 445 #endif 446 watchdog_disable(); 447 set_uart_mux_conf(); 448 setup_early_clocks(); 449 uart_soft_reset(); 450 #ifdef CONFIG_SPL_BUILD 451 /* 452 * Save the boot parameters passed from romcode. 453 * We cannot delay the saving further than this, 454 * to prevent overwrites. 455 */ 456 save_omap_boot_params(); 457 #endif 458 #ifdef CONFIG_DEBUG_UART_OMAP 459 debug_uart_init(); 460 #endif 461 #ifdef CONFIG_TI_I2C_BOARD_DETECT 462 do_board_detect(); 463 #endif 464 #ifdef CONFIG_SPL_BUILD 465 spl_early_init(); 466 #endif 467 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 468 /* Enable RTC32K clock */ 469 rtc32k_enable(); 470 #endif 471 } 472 473 #ifdef CONFIG_SPL_BUILD 474 void board_init_f(ulong dummy) 475 { 476 hw_data_init(); 477 early_system_init(); 478 board_early_init_f(); 479 sdram_init(); 480 /* dram_init must store complete ramsize in gd->ram_size */ 481 gd->ram_size = get_ram_size( 482 (void *)CONFIG_SYS_SDRAM_BASE, 483 CONFIG_MAX_RAM_BANK_SIZE); 484 } 485 #endif 486 487 #endif 488 489 int arch_cpu_init_dm(void) 490 { 491 hw_data_init(); 492 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 493 early_system_init(); 494 #endif 495 return 0; 496 } 497