1 /* 2 * board.c 3 * 4 * Common board functions for AM33XX based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <debug_uart.h> 14 #include <errno.h> 15 #include <ns16550.h> 16 #include <spl.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/omap.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/mem.h> 24 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <i2c.h> 30 #include <miiphy.h> 31 #include <cpsw.h> 32 #include <linux/errno.h> 33 #include <linux/compiler.h> 34 #include <linux/usb/ch9.h> 35 #include <linux/usb/gadget.h> 36 #include <linux/usb/musb.h> 37 #include <asm/omap_musb.h> 38 #include <asm/davinci_rtc.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 int dram_init(void) 43 { 44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 45 sdram_init(); 46 #endif 47 48 /* dram_init must store complete ramsize in gd->ram_size */ 49 gd->ram_size = get_ram_size( 50 (void *)CONFIG_SYS_SDRAM_BASE, 51 CONFIG_MAX_RAM_BANK_SIZE); 52 return 0; 53 } 54 55 int dram_init_banksize(void) 56 { 57 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 58 gd->bd->bi_dram[0].size = gd->ram_size; 59 60 return 0; 61 } 62 63 #if !CONFIG_IS_ENABLED(OF_CONTROL) 64 static const struct ns16550_platdata am33xx_serial[] = { 65 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 66 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 67 # ifdef CONFIG_SYS_NS16550_COM2 68 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 69 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 70 # ifdef CONFIG_SYS_NS16550_COM3 71 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 72 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 73 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 74 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 75 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 76 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 77 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 78 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 79 # endif 80 # endif 81 }; 82 83 U_BOOT_DEVICES(am33xx_uarts) = { 84 { "ns16550_serial", &am33xx_serial[0] }, 85 # ifdef CONFIG_SYS_NS16550_COM2 86 { "ns16550_serial", &am33xx_serial[1] }, 87 # ifdef CONFIG_SYS_NS16550_COM3 88 { "ns16550_serial", &am33xx_serial[2] }, 89 { "ns16550_serial", &am33xx_serial[3] }, 90 { "ns16550_serial", &am33xx_serial[4] }, 91 { "ns16550_serial", &am33xx_serial[5] }, 92 # endif 93 # endif 94 }; 95 96 #ifdef CONFIG_DM_GPIO 97 static const struct omap_gpio_platdata am33xx_gpio[] = { 98 { 0, AM33XX_GPIO0_BASE }, 99 { 1, AM33XX_GPIO1_BASE }, 100 { 2, AM33XX_GPIO2_BASE }, 101 { 3, AM33XX_GPIO3_BASE }, 102 #ifdef CONFIG_AM43XX 103 { 4, AM33XX_GPIO4_BASE }, 104 { 5, AM33XX_GPIO5_BASE }, 105 #endif 106 }; 107 108 U_BOOT_DEVICES(am33xx_gpios) = { 109 { "gpio_omap", &am33xx_gpio[0] }, 110 { "gpio_omap", &am33xx_gpio[1] }, 111 { "gpio_omap", &am33xx_gpio[2] }, 112 { "gpio_omap", &am33xx_gpio[3] }, 113 #ifdef CONFIG_AM43XX 114 { "gpio_omap", &am33xx_gpio[4] }, 115 { "gpio_omap", &am33xx_gpio[5] }, 116 #endif 117 }; 118 #endif 119 #endif 120 121 #ifndef CONFIG_DM_GPIO 122 static const struct gpio_bank gpio_bank_am33xx[] = { 123 { (void *)AM33XX_GPIO0_BASE }, 124 { (void *)AM33XX_GPIO1_BASE }, 125 { (void *)AM33XX_GPIO2_BASE }, 126 { (void *)AM33XX_GPIO3_BASE }, 127 #ifdef CONFIG_AM43XX 128 { (void *)AM33XX_GPIO4_BASE }, 129 { (void *)AM33XX_GPIO5_BASE }, 130 #endif 131 }; 132 133 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 134 #endif 135 136 #if defined(CONFIG_MMC_OMAP_HS) 137 int cpu_mmc_init(bd_t *bis) 138 { 139 int ret; 140 141 ret = omap_mmc_init(0, 0, 0, -1, -1); 142 if (ret) 143 return ret; 144 145 return omap_mmc_init(1, 0, 0, -1, -1); 146 } 147 #endif 148 149 /* AM33XX has two MUSB controllers which can be host or gadget */ 150 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 151 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 152 (!defined(CONFIG_DM_USB)) 153 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 154 155 /* USB 2.0 PHY Control */ 156 #define CM_PHY_PWRDN (1 << 0) 157 #define CM_PHY_OTG_PWRDN (1 << 1) 158 #define OTGVDET_EN (1 << 19) 159 #define OTGSESSENDEN (1 << 20) 160 161 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 162 { 163 if (on) { 164 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 165 OTGVDET_EN | OTGSESSENDEN); 166 } else { 167 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 168 } 169 } 170 171 static struct musb_hdrc_config musb_config = { 172 .multipoint = 1, 173 .dyn_fifo = 1, 174 .num_eps = 16, 175 .ram_bits = 12, 176 }; 177 178 #ifdef CONFIG_AM335X_USB0 179 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 180 { 181 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 182 } 183 184 struct omap_musb_board_data otg0_board_data = { 185 .set_phy_power = am33xx_otg0_set_phy_power, 186 }; 187 188 static struct musb_hdrc_platform_data otg0_plat = { 189 .mode = CONFIG_AM335X_USB0_MODE, 190 .config = &musb_config, 191 .power = 50, 192 .platform_ops = &musb_dsps_ops, 193 .board_data = &otg0_board_data, 194 }; 195 #endif 196 197 #ifdef CONFIG_AM335X_USB1 198 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 199 { 200 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 201 } 202 203 struct omap_musb_board_data otg1_board_data = { 204 .set_phy_power = am33xx_otg1_set_phy_power, 205 }; 206 207 static struct musb_hdrc_platform_data otg1_plat = { 208 .mode = CONFIG_AM335X_USB1_MODE, 209 .config = &musb_config, 210 .power = 50, 211 .platform_ops = &musb_dsps_ops, 212 .board_data = &otg1_board_data, 213 }; 214 #endif 215 #endif 216 217 int arch_misc_init(void) 218 { 219 #ifndef CONFIG_DM_USB 220 #ifdef CONFIG_AM335X_USB0 221 musb_register(&otg0_plat, &otg0_board_data, 222 (void *)USB0_OTG_BASE); 223 #endif 224 #ifdef CONFIG_AM335X_USB1 225 musb_register(&otg1_plat, &otg1_board_data, 226 (void *)USB1_OTG_BASE); 227 #endif 228 #else 229 struct udevice *dev; 230 int ret; 231 232 ret = uclass_first_device(UCLASS_MISC, &dev); 233 if (ret || !dev) 234 return ret; 235 236 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 237 ret = usb_ether_init(); 238 if (ret) { 239 error("USB ether init failed\n"); 240 return ret; 241 } 242 #endif 243 #endif 244 return 0; 245 } 246 247 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 248 /* 249 * In the case of non-SPL based booting we'll want to call these 250 * functions a tiny bit later as it will require gd to be set and cleared 251 * and that's not true in s_init in this case so we cannot do it there. 252 */ 253 int board_early_init_f(void) 254 { 255 prcm_init(); 256 set_mux_conf_regs(); 257 258 return 0; 259 } 260 261 /* 262 * This function is the place to do per-board things such as ramp up the 263 * MPU clock frequency. 264 */ 265 __weak void am33xx_spl_board_init(void) 266 { 267 } 268 269 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 270 static void rtc32k_enable(void) 271 { 272 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 273 274 /* 275 * Unlock the RTC's registers. For more details please see the 276 * RTC_SS section of the TRM. In order to unlock we need to 277 * write these specific values (keys) in this order. 278 */ 279 writel(RTC_KICK0R_WE, &rtc->kick0r); 280 writel(RTC_KICK1R_WE, &rtc->kick1r); 281 282 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 283 writel((1 << 3) | (1 << 6), &rtc->osc); 284 } 285 #endif 286 287 static void uart_soft_reset(void) 288 { 289 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 290 u32 regval; 291 292 regval = readl(&uart_base->uartsyscfg); 293 regval |= UART_RESET; 294 writel(regval, &uart_base->uartsyscfg); 295 while ((readl(&uart_base->uartsyssts) & 296 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 297 ; 298 299 /* Disable smart idle */ 300 regval = readl(&uart_base->uartsyscfg); 301 regval |= UART_SMART_IDLE_EN; 302 writel(regval, &uart_base->uartsyscfg); 303 } 304 305 static void watchdog_disable(void) 306 { 307 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 308 309 writel(0xAAAA, &wdtimer->wdtwspr); 310 while (readl(&wdtimer->wdtwwps) != 0x0) 311 ; 312 writel(0x5555, &wdtimer->wdtwspr); 313 while (readl(&wdtimer->wdtwwps) != 0x0) 314 ; 315 } 316 317 void s_init(void) 318 { 319 } 320 321 void early_system_init(void) 322 { 323 /* 324 * The ROM will only have set up sufficient pinmux to allow for the 325 * first 4KiB NOR to be read, we must finish doing what we know of 326 * the NOR mux in this space in order to continue. 327 */ 328 #ifdef CONFIG_NOR_BOOT 329 enable_norboot_pin_mux(); 330 #endif 331 watchdog_disable(); 332 set_uart_mux_conf(); 333 setup_early_clocks(); 334 uart_soft_reset(); 335 #ifdef CONFIG_DEBUG_UART_OMAP 336 debug_uart_init(); 337 #endif 338 #ifdef CONFIG_TI_I2C_BOARD_DETECT 339 do_board_detect(); 340 #endif 341 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 342 /* Enable RTC32K clock */ 343 rtc32k_enable(); 344 #endif 345 } 346 347 #ifdef CONFIG_SPL_BUILD 348 void board_init_f(ulong dummy) 349 { 350 early_system_init(); 351 board_early_init_f(); 352 sdram_init(); 353 /* dram_init must store complete ramsize in gd->ram_size */ 354 gd->ram_size = get_ram_size( 355 (void *)CONFIG_SYS_SDRAM_BASE, 356 CONFIG_MAX_RAM_BANK_SIZE); 357 } 358 #endif 359 360 #endif 361 362 int arch_cpu_init_dm(void) 363 { 364 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 365 early_system_init(); 366 #endif 367 return 0; 368 } 369