1983e3700STom Rini /* 2983e3700STom Rini * board.c 3983e3700STom Rini * 4983e3700STom Rini * Common board functions for AM33XX based boards 5983e3700STom Rini * 6983e3700STom Rini * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7983e3700STom Rini * 8983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+ 9983e3700STom Rini */ 10983e3700STom Rini 11983e3700STom Rini #include <common.h> 12983e3700STom Rini #include <dm.h> 13983e3700STom Rini #include <errno.h> 14983e3700STom Rini #include <ns16550.h> 15983e3700STom Rini #include <spl.h> 16983e3700STom Rini #include <asm/arch/cpu.h> 17983e3700STom Rini #include <asm/arch/hardware.h> 18983e3700STom Rini #include <asm/arch/omap.h> 19983e3700STom Rini #include <asm/arch/ddr_defs.h> 20983e3700STom Rini #include <asm/arch/clock.h> 21983e3700STom Rini #include <asm/arch/gpio.h> 22983e3700STom Rini #include <asm/arch/mem.h> 23983e3700STom Rini #include <asm/arch/mmc_host_def.h> 24983e3700STom Rini #include <asm/arch/sys_proto.h> 25983e3700STom Rini #include <asm/io.h> 26983e3700STom Rini #include <asm/emif.h> 27983e3700STom Rini #include <asm/gpio.h> 28983e3700STom Rini #include <i2c.h> 29983e3700STom Rini #include <miiphy.h> 30983e3700STom Rini #include <cpsw.h> 31983e3700STom Rini #include <linux/errno.h> 32983e3700STom Rini #include <linux/compiler.h> 33983e3700STom Rini #include <linux/usb/ch9.h> 34983e3700STom Rini #include <linux/usb/gadget.h> 35983e3700STom Rini #include <linux/usb/musb.h> 36983e3700STom Rini #include <asm/omap_musb.h> 37983e3700STom Rini #include <asm/davinci_rtc.h> 38983e3700STom Rini 39983e3700STom Rini DECLARE_GLOBAL_DATA_PTR; 40983e3700STom Rini 41983e3700STom Rini #if !CONFIG_IS_ENABLED(OF_CONTROL) 42983e3700STom Rini static const struct ns16550_platdata am33xx_serial[] = { 4317fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 4417fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 45983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 4617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 4717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 48983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 4917fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 5017fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 5117fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 5217fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 5317fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 5417fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 5517fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 5617fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 57983e3700STom Rini # endif 58983e3700STom Rini # endif 59983e3700STom Rini }; 60983e3700STom Rini 61983e3700STom Rini U_BOOT_DEVICES(am33xx_uarts) = { 62983e3700STom Rini { "ns16550_serial", &am33xx_serial[0] }, 63983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 64983e3700STom Rini { "ns16550_serial", &am33xx_serial[1] }, 65983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 66983e3700STom Rini { "ns16550_serial", &am33xx_serial[2] }, 67983e3700STom Rini { "ns16550_serial", &am33xx_serial[3] }, 68983e3700STom Rini { "ns16550_serial", &am33xx_serial[4] }, 69983e3700STom Rini { "ns16550_serial", &am33xx_serial[5] }, 70983e3700STom Rini # endif 71983e3700STom Rini # endif 72983e3700STom Rini }; 73983e3700STom Rini 74983e3700STom Rini #ifdef CONFIG_DM_GPIO 75983e3700STom Rini static const struct omap_gpio_platdata am33xx_gpio[] = { 76983e3700STom Rini { 0, AM33XX_GPIO0_BASE }, 77983e3700STom Rini { 1, AM33XX_GPIO1_BASE }, 78983e3700STom Rini { 2, AM33XX_GPIO2_BASE }, 79983e3700STom Rini { 3, AM33XX_GPIO3_BASE }, 80983e3700STom Rini #ifdef CONFIG_AM43XX 81983e3700STom Rini { 4, AM33XX_GPIO4_BASE }, 82983e3700STom Rini { 5, AM33XX_GPIO5_BASE }, 83983e3700STom Rini #endif 84983e3700STom Rini }; 85983e3700STom Rini 86983e3700STom Rini U_BOOT_DEVICES(am33xx_gpios) = { 87983e3700STom Rini { "gpio_omap", &am33xx_gpio[0] }, 88983e3700STom Rini { "gpio_omap", &am33xx_gpio[1] }, 89983e3700STom Rini { "gpio_omap", &am33xx_gpio[2] }, 90983e3700STom Rini { "gpio_omap", &am33xx_gpio[3] }, 91983e3700STom Rini #ifdef CONFIG_AM43XX 92983e3700STom Rini { "gpio_omap", &am33xx_gpio[4] }, 93983e3700STom Rini { "gpio_omap", &am33xx_gpio[5] }, 94983e3700STom Rini #endif 95983e3700STom Rini }; 96983e3700STom Rini #endif 97983e3700STom Rini #endif 98983e3700STom Rini 99983e3700STom Rini #ifndef CONFIG_DM_GPIO 100983e3700STom Rini static const struct gpio_bank gpio_bank_am33xx[] = { 101983e3700STom Rini { (void *)AM33XX_GPIO0_BASE }, 102983e3700STom Rini { (void *)AM33XX_GPIO1_BASE }, 103983e3700STom Rini { (void *)AM33XX_GPIO2_BASE }, 104983e3700STom Rini { (void *)AM33XX_GPIO3_BASE }, 105983e3700STom Rini #ifdef CONFIG_AM43XX 106983e3700STom Rini { (void *)AM33XX_GPIO4_BASE }, 107983e3700STom Rini { (void *)AM33XX_GPIO5_BASE }, 108983e3700STom Rini #endif 109983e3700STom Rini }; 110983e3700STom Rini 111983e3700STom Rini const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 112983e3700STom Rini #endif 113983e3700STom Rini 114*d5abcf94SJean-Jacques Hiblot #if defined(CONFIG_MMC_OMAP_HS) 115983e3700STom Rini int cpu_mmc_init(bd_t *bis) 116983e3700STom Rini { 117983e3700STom Rini int ret; 118983e3700STom Rini 119983e3700STom Rini ret = omap_mmc_init(0, 0, 0, -1, -1); 120983e3700STom Rini if (ret) 121983e3700STom Rini return ret; 122983e3700STom Rini 123983e3700STom Rini return omap_mmc_init(1, 0, 0, -1, -1); 124983e3700STom Rini } 125983e3700STom Rini #endif 126983e3700STom Rini 127983e3700STom Rini /* AM33XX has two MUSB controllers which can be host or gadget */ 128983e3700STom Rini #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 12919570221SMugunthan V N (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 13019570221SMugunthan V N (!defined(CONFIG_DM_USB)) 131983e3700STom Rini static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 132983e3700STom Rini 133983e3700STom Rini /* USB 2.0 PHY Control */ 134983e3700STom Rini #define CM_PHY_PWRDN (1 << 0) 135983e3700STom Rini #define CM_PHY_OTG_PWRDN (1 << 1) 136983e3700STom Rini #define OTGVDET_EN (1 << 19) 137983e3700STom Rini #define OTGSESSENDEN (1 << 20) 138983e3700STom Rini 139983e3700STom Rini static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 140983e3700STom Rini { 141983e3700STom Rini if (on) { 142983e3700STom Rini clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 143983e3700STom Rini OTGVDET_EN | OTGSESSENDEN); 144983e3700STom Rini } else { 145983e3700STom Rini clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 146983e3700STom Rini } 147983e3700STom Rini } 148983e3700STom Rini 149983e3700STom Rini static struct musb_hdrc_config musb_config = { 150983e3700STom Rini .multipoint = 1, 151983e3700STom Rini .dyn_fifo = 1, 152983e3700STom Rini .num_eps = 16, 153983e3700STom Rini .ram_bits = 12, 154983e3700STom Rini }; 155983e3700STom Rini 156983e3700STom Rini #ifdef CONFIG_AM335X_USB0 1571cac34ceSMugunthan V N static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 158983e3700STom Rini { 159983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 160983e3700STom Rini } 161983e3700STom Rini 162983e3700STom Rini struct omap_musb_board_data otg0_board_data = { 163983e3700STom Rini .set_phy_power = am33xx_otg0_set_phy_power, 164983e3700STom Rini }; 165983e3700STom Rini 166983e3700STom Rini static struct musb_hdrc_platform_data otg0_plat = { 167983e3700STom Rini .mode = CONFIG_AM335X_USB0_MODE, 168983e3700STom Rini .config = &musb_config, 169983e3700STom Rini .power = 50, 170983e3700STom Rini .platform_ops = &musb_dsps_ops, 171983e3700STom Rini .board_data = &otg0_board_data, 172983e3700STom Rini }; 173983e3700STom Rini #endif 174983e3700STom Rini 175983e3700STom Rini #ifdef CONFIG_AM335X_USB1 1761cac34ceSMugunthan V N static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 177983e3700STom Rini { 178983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 179983e3700STom Rini } 180983e3700STom Rini 181983e3700STom Rini struct omap_musb_board_data otg1_board_data = { 182983e3700STom Rini .set_phy_power = am33xx_otg1_set_phy_power, 183983e3700STom Rini }; 184983e3700STom Rini 185983e3700STom Rini static struct musb_hdrc_platform_data otg1_plat = { 186983e3700STom Rini .mode = CONFIG_AM335X_USB1_MODE, 187983e3700STom Rini .config = &musb_config, 188983e3700STom Rini .power = 50, 189983e3700STom Rini .platform_ops = &musb_dsps_ops, 190983e3700STom Rini .board_data = &otg1_board_data, 191983e3700STom Rini }; 192983e3700STom Rini #endif 193983e3700STom Rini #endif 194983e3700STom Rini 195983e3700STom Rini int arch_misc_init(void) 196983e3700STom Rini { 19719570221SMugunthan V N #ifndef CONFIG_DM_USB 198983e3700STom Rini #ifdef CONFIG_AM335X_USB0 199983e3700STom Rini musb_register(&otg0_plat, &otg0_board_data, 200983e3700STom Rini (void *)USB0_OTG_BASE); 201983e3700STom Rini #endif 202983e3700STom Rini #ifdef CONFIG_AM335X_USB1 203983e3700STom Rini musb_register(&otg1_plat, &otg1_board_data, 204983e3700STom Rini (void *)USB1_OTG_BASE); 205983e3700STom Rini #endif 2063aec2648SMugunthan V N #else 2073aec2648SMugunthan V N struct udevice *dev; 2083aec2648SMugunthan V N int ret; 2093aec2648SMugunthan V N 2103aec2648SMugunthan V N ret = uclass_first_device(UCLASS_MISC, &dev); 2113aec2648SMugunthan V N if (ret || !dev) 2123aec2648SMugunthan V N return ret; 213ba7916c7SMugunthan V N 214ba7916c7SMugunthan V N #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 215ba7916c7SMugunthan V N ret = usb_ether_init(); 216ba7916c7SMugunthan V N if (ret) { 217ba7916c7SMugunthan V N error("USB ether init failed\n"); 218ba7916c7SMugunthan V N return ret; 219ba7916c7SMugunthan V N } 220ba7916c7SMugunthan V N #endif 22119570221SMugunthan V N #endif 222983e3700STom Rini return 0; 223983e3700STom Rini } 224983e3700STom Rini 225983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 226983e3700STom Rini /* 227983e3700STom Rini * In the case of non-SPL based booting we'll want to call these 228983e3700STom Rini * functions a tiny bit later as it will require gd to be set and cleared 229983e3700STom Rini * and that's not true in s_init in this case so we cannot do it there. 230983e3700STom Rini */ 231983e3700STom Rini int board_early_init_f(void) 232983e3700STom Rini { 233983e3700STom Rini prcm_init(); 234983e3700STom Rini set_mux_conf_regs(); 235983e3700STom Rini 236983e3700STom Rini return 0; 237983e3700STom Rini } 238983e3700STom Rini 239983e3700STom Rini /* 240983e3700STom Rini * This function is the place to do per-board things such as ramp up the 241983e3700STom Rini * MPU clock frequency. 242983e3700STom Rini */ 243983e3700STom Rini __weak void am33xx_spl_board_init(void) 244983e3700STom Rini { 245983e3700STom Rini do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 246983e3700STom Rini do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 247983e3700STom Rini } 248983e3700STom Rini 249983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 250983e3700STom Rini static void rtc32k_enable(void) 251983e3700STom Rini { 252983e3700STom Rini struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 253983e3700STom Rini 254983e3700STom Rini /* 255983e3700STom Rini * Unlock the RTC's registers. For more details please see the 256983e3700STom Rini * RTC_SS section of the TRM. In order to unlock we need to 257983e3700STom Rini * write these specific values (keys) in this order. 258983e3700STom Rini */ 259983e3700STom Rini writel(RTC_KICK0R_WE, &rtc->kick0r); 260983e3700STom Rini writel(RTC_KICK1R_WE, &rtc->kick1r); 261983e3700STom Rini 262983e3700STom Rini /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 263983e3700STom Rini writel((1 << 3) | (1 << 6), &rtc->osc); 264983e3700STom Rini } 265983e3700STom Rini #endif 266983e3700STom Rini 267983e3700STom Rini static void uart_soft_reset(void) 268983e3700STom Rini { 269983e3700STom Rini struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 270983e3700STom Rini u32 regval; 271983e3700STom Rini 272983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 273983e3700STom Rini regval |= UART_RESET; 274983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 275983e3700STom Rini while ((readl(&uart_base->uartsyssts) & 276983e3700STom Rini UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 277983e3700STom Rini ; 278983e3700STom Rini 279983e3700STom Rini /* Disable smart idle */ 280983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 281983e3700STom Rini regval |= UART_SMART_IDLE_EN; 282983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 283983e3700STom Rini } 284983e3700STom Rini 285983e3700STom Rini static void watchdog_disable(void) 286983e3700STom Rini { 287983e3700STom Rini struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 288983e3700STom Rini 289983e3700STom Rini writel(0xAAAA, &wdtimer->wdtwspr); 290983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 291983e3700STom Rini ; 292983e3700STom Rini writel(0x5555, &wdtimer->wdtwspr); 293983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 294983e3700STom Rini ; 295983e3700STom Rini } 296983e3700STom Rini 297983e3700STom Rini void s_init(void) 298983e3700STom Rini { 299983e3700STom Rini } 300983e3700STom Rini 301983e3700STom Rini void early_system_init(void) 302983e3700STom Rini { 303983e3700STom Rini /* 304983e3700STom Rini * The ROM will only have set up sufficient pinmux to allow for the 305983e3700STom Rini * first 4KiB NOR to be read, we must finish doing what we know of 306983e3700STom Rini * the NOR mux in this space in order to continue. 307983e3700STom Rini */ 308983e3700STom Rini #ifdef CONFIG_NOR_BOOT 309983e3700STom Rini enable_norboot_pin_mux(); 310983e3700STom Rini #endif 311983e3700STom Rini watchdog_disable(); 312983e3700STom Rini set_uart_mux_conf(); 313983e3700STom Rini setup_early_clocks(); 314983e3700STom Rini uart_soft_reset(); 315983e3700STom Rini #ifdef CONFIG_TI_I2C_BOARD_DETECT 316983e3700STom Rini do_board_detect(); 317983e3700STom Rini #endif 318983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 319983e3700STom Rini /* Enable RTC32K clock */ 320983e3700STom Rini rtc32k_enable(); 321983e3700STom Rini #endif 322983e3700STom Rini } 323983e3700STom Rini 324983e3700STom Rini #ifdef CONFIG_SPL_BUILD 325983e3700STom Rini void board_init_f(ulong dummy) 326983e3700STom Rini { 327983e3700STom Rini early_system_init(); 328983e3700STom Rini board_early_init_f(); 329983e3700STom Rini sdram_init(); 330983e3700STom Rini } 331983e3700STom Rini #endif 332983e3700STom Rini 333983e3700STom Rini #endif 334983e3700STom Rini 335983e3700STom Rini int arch_cpu_init_dm(void) 336983e3700STom Rini { 337983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 338983e3700STom Rini early_system_init(); 339983e3700STom Rini #endif 340983e3700STom Rini return 0; 341983e3700STom Rini } 342