1983e3700STom Rini /* 2983e3700STom Rini * board.c 3983e3700STom Rini * 4983e3700STom Rini * Common board functions for AM33XX based boards 5983e3700STom Rini * 6983e3700STom Rini * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7983e3700STom Rini * 8983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+ 9983e3700STom Rini */ 10983e3700STom Rini 11983e3700STom Rini #include <common.h> 12983e3700STom Rini #include <dm.h> 13878d8856SLokesh Vutla #include <debug_uart.h> 14983e3700STom Rini #include <errno.h> 15983e3700STom Rini #include <ns16550.h> 16983e3700STom Rini #include <spl.h> 17983e3700STom Rini #include <asm/arch/cpu.h> 18983e3700STom Rini #include <asm/arch/hardware.h> 19983e3700STom Rini #include <asm/arch/omap.h> 20983e3700STom Rini #include <asm/arch/ddr_defs.h> 21983e3700STom Rini #include <asm/arch/clock.h> 22983e3700STom Rini #include <asm/arch/gpio.h> 23983e3700STom Rini #include <asm/arch/mem.h> 24983e3700STom Rini #include <asm/arch/mmc_host_def.h> 25983e3700STom Rini #include <asm/arch/sys_proto.h> 26983e3700STom Rini #include <asm/io.h> 27983e3700STom Rini #include <asm/emif.h> 28983e3700STom Rini #include <asm/gpio.h> 2900bbe96eSSemen Protsenko #include <asm/omap_common.h> 30983e3700STom Rini #include <i2c.h> 31983e3700STom Rini #include <miiphy.h> 32983e3700STom Rini #include <cpsw.h> 33983e3700STom Rini #include <linux/errno.h> 34983e3700STom Rini #include <linux/compiler.h> 35983e3700STom Rini #include <linux/usb/ch9.h> 36983e3700STom Rini #include <linux/usb/gadget.h> 37983e3700STom Rini #include <linux/usb/musb.h> 38983e3700STom Rini #include <asm/omap_musb.h> 39983e3700STom Rini #include <asm/davinci_rtc.h> 40983e3700STom Rini 41983e3700STom Rini DECLARE_GLOBAL_DATA_PTR; 42983e3700STom Rini 4386277339STom Rini int dram_init(void) 4486277339STom Rini { 4586277339STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 4686277339STom Rini sdram_init(); 4786277339STom Rini #endif 4886277339STom Rini 4986277339STom Rini /* dram_init must store complete ramsize in gd->ram_size */ 5086277339STom Rini gd->ram_size = get_ram_size( 5186277339STom Rini (void *)CONFIG_SYS_SDRAM_BASE, 5286277339STom Rini CONFIG_MAX_RAM_BANK_SIZE); 5386277339STom Rini return 0; 5486277339STom Rini } 5586277339STom Rini 5686277339STom Rini int dram_init_banksize(void) 5786277339STom Rini { 5886277339STom Rini gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 5986277339STom Rini gd->bd->bi_dram[0].size = gd->ram_size; 6086277339STom Rini 6186277339STom Rini return 0; 6286277339STom Rini } 6386277339STom Rini 64983e3700STom Rini #if !CONFIG_IS_ENABLED(OF_CONTROL) 65983e3700STom Rini static const struct ns16550_platdata am33xx_serial[] = { 6617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 6717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 68983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 6917fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 7017fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 71983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 7217fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 7317fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7417fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 7517fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 7717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7817fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 7917fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 80983e3700STom Rini # endif 81983e3700STom Rini # endif 82983e3700STom Rini }; 83983e3700STom Rini 84983e3700STom Rini U_BOOT_DEVICES(am33xx_uarts) = { 85983e3700STom Rini { "ns16550_serial", &am33xx_serial[0] }, 86983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 87983e3700STom Rini { "ns16550_serial", &am33xx_serial[1] }, 88983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 89983e3700STom Rini { "ns16550_serial", &am33xx_serial[2] }, 90983e3700STom Rini { "ns16550_serial", &am33xx_serial[3] }, 91983e3700STom Rini { "ns16550_serial", &am33xx_serial[4] }, 92983e3700STom Rini { "ns16550_serial", &am33xx_serial[5] }, 93983e3700STom Rini # endif 94983e3700STom Rini # endif 95983e3700STom Rini }; 96983e3700STom Rini 97983e3700STom Rini #ifdef CONFIG_DM_GPIO 98983e3700STom Rini static const struct omap_gpio_platdata am33xx_gpio[] = { 99983e3700STom Rini { 0, AM33XX_GPIO0_BASE }, 100983e3700STom Rini { 1, AM33XX_GPIO1_BASE }, 101983e3700STom Rini { 2, AM33XX_GPIO2_BASE }, 102983e3700STom Rini { 3, AM33XX_GPIO3_BASE }, 103983e3700STom Rini #ifdef CONFIG_AM43XX 104983e3700STom Rini { 4, AM33XX_GPIO4_BASE }, 105983e3700STom Rini { 5, AM33XX_GPIO5_BASE }, 106983e3700STom Rini #endif 107983e3700STom Rini }; 108983e3700STom Rini 109983e3700STom Rini U_BOOT_DEVICES(am33xx_gpios) = { 110983e3700STom Rini { "gpio_omap", &am33xx_gpio[0] }, 111983e3700STom Rini { "gpio_omap", &am33xx_gpio[1] }, 112983e3700STom Rini { "gpio_omap", &am33xx_gpio[2] }, 113983e3700STom Rini { "gpio_omap", &am33xx_gpio[3] }, 114983e3700STom Rini #ifdef CONFIG_AM43XX 115983e3700STom Rini { "gpio_omap", &am33xx_gpio[4] }, 116983e3700STom Rini { "gpio_omap", &am33xx_gpio[5] }, 117983e3700STom Rini #endif 118983e3700STom Rini }; 119983e3700STom Rini #endif 120983e3700STom Rini #endif 121983e3700STom Rini 122983e3700STom Rini #ifndef CONFIG_DM_GPIO 123983e3700STom Rini static const struct gpio_bank gpio_bank_am33xx[] = { 124983e3700STom Rini { (void *)AM33XX_GPIO0_BASE }, 125983e3700STom Rini { (void *)AM33XX_GPIO1_BASE }, 126983e3700STom Rini { (void *)AM33XX_GPIO2_BASE }, 127983e3700STom Rini { (void *)AM33XX_GPIO3_BASE }, 128983e3700STom Rini #ifdef CONFIG_AM43XX 129983e3700STom Rini { (void *)AM33XX_GPIO4_BASE }, 130983e3700STom Rini { (void *)AM33XX_GPIO5_BASE }, 131983e3700STom Rini #endif 132983e3700STom Rini }; 133983e3700STom Rini 134983e3700STom Rini const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 135983e3700STom Rini #endif 136983e3700STom Rini 137d5abcf94SJean-Jacques Hiblot #if defined(CONFIG_MMC_OMAP_HS) 138983e3700STom Rini int cpu_mmc_init(bd_t *bis) 139983e3700STom Rini { 140983e3700STom Rini int ret; 141983e3700STom Rini 142983e3700STom Rini ret = omap_mmc_init(0, 0, 0, -1, -1); 143983e3700STom Rini if (ret) 144983e3700STom Rini return ret; 145983e3700STom Rini 146983e3700STom Rini return omap_mmc_init(1, 0, 0, -1, -1); 147983e3700STom Rini } 148983e3700STom Rini #endif 149983e3700STom Rini 150983e3700STom Rini /* AM33XX has two MUSB controllers which can be host or gadget */ 151983e3700STom Rini #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 15219570221SMugunthan V N (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 15319570221SMugunthan V N (!defined(CONFIG_DM_USB)) 154983e3700STom Rini static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 155983e3700STom Rini 156983e3700STom Rini /* USB 2.0 PHY Control */ 157983e3700STom Rini #define CM_PHY_PWRDN (1 << 0) 158983e3700STom Rini #define CM_PHY_OTG_PWRDN (1 << 1) 159983e3700STom Rini #define OTGVDET_EN (1 << 19) 160983e3700STom Rini #define OTGSESSENDEN (1 << 20) 161983e3700STom Rini 162983e3700STom Rini static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 163983e3700STom Rini { 164983e3700STom Rini if (on) { 165983e3700STom Rini clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 166983e3700STom Rini OTGVDET_EN | OTGSESSENDEN); 167983e3700STom Rini } else { 168983e3700STom Rini clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 169983e3700STom Rini } 170983e3700STom Rini } 171983e3700STom Rini 172983e3700STom Rini static struct musb_hdrc_config musb_config = { 173983e3700STom Rini .multipoint = 1, 174983e3700STom Rini .dyn_fifo = 1, 175983e3700STom Rini .num_eps = 16, 176983e3700STom Rini .ram_bits = 12, 177983e3700STom Rini }; 178983e3700STom Rini 179983e3700STom Rini #ifdef CONFIG_AM335X_USB0 1801cac34ceSMugunthan V N static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 181983e3700STom Rini { 182983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 183983e3700STom Rini } 184983e3700STom Rini 185983e3700STom Rini struct omap_musb_board_data otg0_board_data = { 186983e3700STom Rini .set_phy_power = am33xx_otg0_set_phy_power, 187983e3700STom Rini }; 188983e3700STom Rini 189983e3700STom Rini static struct musb_hdrc_platform_data otg0_plat = { 190983e3700STom Rini .mode = CONFIG_AM335X_USB0_MODE, 191983e3700STom Rini .config = &musb_config, 192983e3700STom Rini .power = 50, 193983e3700STom Rini .platform_ops = &musb_dsps_ops, 194983e3700STom Rini .board_data = &otg0_board_data, 195983e3700STom Rini }; 196983e3700STom Rini #endif 197983e3700STom Rini 198983e3700STom Rini #ifdef CONFIG_AM335X_USB1 1991cac34ceSMugunthan V N static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 200983e3700STom Rini { 201983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 202983e3700STom Rini } 203983e3700STom Rini 204983e3700STom Rini struct omap_musb_board_data otg1_board_data = { 205983e3700STom Rini .set_phy_power = am33xx_otg1_set_phy_power, 206983e3700STom Rini }; 207983e3700STom Rini 208983e3700STom Rini static struct musb_hdrc_platform_data otg1_plat = { 209983e3700STom Rini .mode = CONFIG_AM335X_USB1_MODE, 210983e3700STom Rini .config = &musb_config, 211983e3700STom Rini .power = 50, 212983e3700STom Rini .platform_ops = &musb_dsps_ops, 213983e3700STom Rini .board_data = &otg1_board_data, 214983e3700STom Rini }; 215983e3700STom Rini #endif 216983e3700STom Rini 217983e3700STom Rini int arch_misc_init(void) 218983e3700STom Rini { 219983e3700STom Rini #ifdef CONFIG_AM335X_USB0 220983e3700STom Rini musb_register(&otg0_plat, &otg0_board_data, 221983e3700STom Rini (void *)USB0_OTG_BASE); 222983e3700STom Rini #endif 223983e3700STom Rini #ifdef CONFIG_AM335X_USB1 224983e3700STom Rini musb_register(&otg1_plat, &otg1_board_data, 225983e3700STom Rini (void *)USB1_OTG_BASE); 226983e3700STom Rini #endif 227409a81ddSAlexandru Gagniuc return 0; 228409a81ddSAlexandru Gagniuc } 229409a81ddSAlexandru Gagniuc 230409a81ddSAlexandru Gagniuc #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 231409a81ddSAlexandru Gagniuc 232409a81ddSAlexandru Gagniuc int arch_misc_init(void) 233409a81ddSAlexandru Gagniuc { 2343aec2648SMugunthan V N struct udevice *dev; 2353aec2648SMugunthan V N int ret; 2363aec2648SMugunthan V N 2373aec2648SMugunthan V N ret = uclass_first_device(UCLASS_MISC, &dev); 2383aec2648SMugunthan V N if (ret || !dev) 2393aec2648SMugunthan V N return ret; 240ba7916c7SMugunthan V N 241ba7916c7SMugunthan V N #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 242ba7916c7SMugunthan V N ret = usb_ether_init(); 243ba7916c7SMugunthan V N if (ret) { 2449b643e31SMasahiro Yamada pr_err("USB ether init failed\n"); 245ba7916c7SMugunthan V N return ret; 246ba7916c7SMugunthan V N } 247ba7916c7SMugunthan V N #endif 248409a81ddSAlexandru Gagniuc 249983e3700STom Rini return 0; 250983e3700STom Rini } 251983e3700STom Rini 252409a81ddSAlexandru Gagniuc #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 253409a81ddSAlexandru Gagniuc 254983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 255983e3700STom Rini /* 256983e3700STom Rini * In the case of non-SPL based booting we'll want to call these 257983e3700STom Rini * functions a tiny bit later as it will require gd to be set and cleared 258983e3700STom Rini * and that's not true in s_init in this case so we cannot do it there. 259983e3700STom Rini */ 260983e3700STom Rini int board_early_init_f(void) 261983e3700STom Rini { 262983e3700STom Rini prcm_init(); 263983e3700STom Rini set_mux_conf_regs(); 264983e3700STom Rini 265983e3700STom Rini return 0; 266983e3700STom Rini } 267983e3700STom Rini 268983e3700STom Rini /* 269983e3700STom Rini * This function is the place to do per-board things such as ramp up the 270983e3700STom Rini * MPU clock frequency. 271983e3700STom Rini */ 272983e3700STom Rini __weak void am33xx_spl_board_init(void) 273983e3700STom Rini { 274983e3700STom Rini } 275983e3700STom Rini 276983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 277983e3700STom Rini static void rtc32k_enable(void) 278983e3700STom Rini { 279983e3700STom Rini struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 280983e3700STom Rini 281983e3700STom Rini /* 282983e3700STom Rini * Unlock the RTC's registers. For more details please see the 283983e3700STom Rini * RTC_SS section of the TRM. In order to unlock we need to 284983e3700STom Rini * write these specific values (keys) in this order. 285983e3700STom Rini */ 286983e3700STom Rini writel(RTC_KICK0R_WE, &rtc->kick0r); 287983e3700STom Rini writel(RTC_KICK1R_WE, &rtc->kick1r); 288983e3700STom Rini 289983e3700STom Rini /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 290983e3700STom Rini writel((1 << 3) | (1 << 6), &rtc->osc); 291983e3700STom Rini } 292983e3700STom Rini #endif 293983e3700STom Rini 294983e3700STom Rini static void uart_soft_reset(void) 295983e3700STom Rini { 296983e3700STom Rini struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 297983e3700STom Rini u32 regval; 298983e3700STom Rini 299983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 300983e3700STom Rini regval |= UART_RESET; 301983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 302983e3700STom Rini while ((readl(&uart_base->uartsyssts) & 303983e3700STom Rini UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 304983e3700STom Rini ; 305983e3700STom Rini 306983e3700STom Rini /* Disable smart idle */ 307983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 308983e3700STom Rini regval |= UART_SMART_IDLE_EN; 309983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 310983e3700STom Rini } 311983e3700STom Rini 312983e3700STom Rini static void watchdog_disable(void) 313983e3700STom Rini { 314983e3700STom Rini struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 315983e3700STom Rini 316983e3700STom Rini writel(0xAAAA, &wdtimer->wdtwspr); 317983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 318983e3700STom Rini ; 319983e3700STom Rini writel(0x5555, &wdtimer->wdtwspr); 320983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 321983e3700STom Rini ; 322983e3700STom Rini } 323983e3700STom Rini 324983e3700STom Rini void s_init(void) 325983e3700STom Rini { 326983e3700STom Rini } 327983e3700STom Rini 328983e3700STom Rini void early_system_init(void) 329983e3700STom Rini { 330983e3700STom Rini /* 331983e3700STom Rini * The ROM will only have set up sufficient pinmux to allow for the 332983e3700STom Rini * first 4KiB NOR to be read, we must finish doing what we know of 333983e3700STom Rini * the NOR mux in this space in order to continue. 334983e3700STom Rini */ 335983e3700STom Rini #ifdef CONFIG_NOR_BOOT 336983e3700STom Rini enable_norboot_pin_mux(); 337983e3700STom Rini #endif 338983e3700STom Rini watchdog_disable(); 339983e3700STom Rini set_uart_mux_conf(); 340983e3700STom Rini setup_early_clocks(); 341983e3700STom Rini uart_soft_reset(); 3424bd754d8SLokesh Vutla #ifdef CONFIG_SPL_BUILD 3434bd754d8SLokesh Vutla /* 3444bd754d8SLokesh Vutla * Save the boot parameters passed from romcode. 3454bd754d8SLokesh Vutla * We cannot delay the saving further than this, 3464bd754d8SLokesh Vutla * to prevent overwrites. 3474bd754d8SLokesh Vutla */ 3484bd754d8SLokesh Vutla save_omap_boot_params(); 3494bd754d8SLokesh Vutla #endif 350878d8856SLokesh Vutla #ifdef CONFIG_DEBUG_UART_OMAP 351878d8856SLokesh Vutla debug_uart_init(); 352878d8856SLokesh Vutla #endif 353983e3700STom Rini #ifdef CONFIG_TI_I2C_BOARD_DETECT 354983e3700STom Rini do_board_detect(); 355983e3700STom Rini #endif 356*b442e16bSFaiz Abbas #ifdef CONFIG_SPL_BUILD 357*b442e16bSFaiz Abbas spl_early_init(); 358*b442e16bSFaiz Abbas #endif 359983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 360983e3700STom Rini /* Enable RTC32K clock */ 361983e3700STom Rini rtc32k_enable(); 362983e3700STom Rini #endif 363983e3700STom Rini } 364983e3700STom Rini 365983e3700STom Rini #ifdef CONFIG_SPL_BUILD 366983e3700STom Rini void board_init_f(ulong dummy) 367983e3700STom Rini { 36800bbe96eSSemen Protsenko hw_data_init(); 369983e3700STom Rini early_system_init(); 370983e3700STom Rini board_early_init_f(); 371983e3700STom Rini sdram_init(); 37286282798SLokesh Vutla /* dram_init must store complete ramsize in gd->ram_size */ 37386282798SLokesh Vutla gd->ram_size = get_ram_size( 37486282798SLokesh Vutla (void *)CONFIG_SYS_SDRAM_BASE, 37586282798SLokesh Vutla CONFIG_MAX_RAM_BANK_SIZE); 376983e3700STom Rini } 377983e3700STom Rini #endif 378983e3700STom Rini 379983e3700STom Rini #endif 380983e3700STom Rini 381983e3700STom Rini int arch_cpu_init_dm(void) 382983e3700STom Rini { 38300bbe96eSSemen Protsenko hw_data_init(); 384983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 385983e3700STom Rini early_system_init(); 386983e3700STom Rini #endif 387983e3700STom Rini return 0; 388983e3700STom Rini } 389