1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2983e3700STom Rini /* 3983e3700STom Rini * board.c 4983e3700STom Rini * 5983e3700STom Rini * Common board functions for AM33XX based boards 6983e3700STom Rini * 7983e3700STom Rini * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8983e3700STom Rini */ 9983e3700STom Rini 10983e3700STom Rini #include <common.h> 11983e3700STom Rini #include <dm.h> 12878d8856SLokesh Vutla #include <debug_uart.h> 13983e3700STom Rini #include <errno.h> 14983e3700STom Rini #include <ns16550.h> 15983e3700STom Rini #include <spl.h> 16983e3700STom Rini #include <asm/arch/cpu.h> 17983e3700STom Rini #include <asm/arch/hardware.h> 18983e3700STom Rini #include <asm/arch/omap.h> 19983e3700STom Rini #include <asm/arch/ddr_defs.h> 20983e3700STom Rini #include <asm/arch/clock.h> 21983e3700STom Rini #include <asm/arch/gpio.h> 22983e3700STom Rini #include <asm/arch/mem.h> 23983e3700STom Rini #include <asm/arch/mmc_host_def.h> 24983e3700STom Rini #include <asm/arch/sys_proto.h> 25983e3700STom Rini #include <asm/io.h> 26983e3700STom Rini #include <asm/emif.h> 27983e3700STom Rini #include <asm/gpio.h> 2800bbe96eSSemen Protsenko #include <asm/omap_common.h> 29983e3700STom Rini #include <i2c.h> 30983e3700STom Rini #include <miiphy.h> 31983e3700STom Rini #include <cpsw.h> 32983e3700STom Rini #include <linux/errno.h> 33983e3700STom Rini #include <linux/compiler.h> 34983e3700STom Rini #include <linux/usb/ch9.h> 35983e3700STom Rini #include <linux/usb/gadget.h> 36983e3700STom Rini #include <linux/usb/musb.h> 37983e3700STom Rini #include <asm/omap_musb.h> 38983e3700STom Rini #include <asm/davinci_rtc.h> 39983e3700STom Rini 40983e3700STom Rini DECLARE_GLOBAL_DATA_PTR; 41983e3700STom Rini 4286277339STom Rini int dram_init(void) 4386277339STom Rini { 4486277339STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 4586277339STom Rini sdram_init(); 4686277339STom Rini #endif 4786277339STom Rini 4886277339STom Rini /* dram_init must store complete ramsize in gd->ram_size */ 4986277339STom Rini gd->ram_size = get_ram_size( 5086277339STom Rini (void *)CONFIG_SYS_SDRAM_BASE, 5186277339STom Rini CONFIG_MAX_RAM_BANK_SIZE); 5286277339STom Rini return 0; 5386277339STom Rini } 5486277339STom Rini 5586277339STom Rini int dram_init_banksize(void) 5686277339STom Rini { 5786277339STom Rini gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 5886277339STom Rini gd->bd->bi_dram[0].size = gd->ram_size; 5986277339STom Rini 6086277339STom Rini return 0; 6186277339STom Rini } 6286277339STom Rini 63983e3700STom Rini #if !CONFIG_IS_ENABLED(OF_CONTROL) 64983e3700STom Rini static const struct ns16550_platdata am33xx_serial[] = { 6517fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 6617fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 67983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 6817fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 6917fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 70983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 7117fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 7217fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7317fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 7417fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7517fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 7617fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7717fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 7817fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 79983e3700STom Rini # endif 80983e3700STom Rini # endif 81983e3700STom Rini }; 82983e3700STom Rini 83983e3700STom Rini U_BOOT_DEVICES(am33xx_uarts) = { 84983e3700STom Rini { "ns16550_serial", &am33xx_serial[0] }, 85983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 86983e3700STom Rini { "ns16550_serial", &am33xx_serial[1] }, 87983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 88983e3700STom Rini { "ns16550_serial", &am33xx_serial[2] }, 89983e3700STom Rini { "ns16550_serial", &am33xx_serial[3] }, 90983e3700STom Rini { "ns16550_serial", &am33xx_serial[4] }, 91983e3700STom Rini { "ns16550_serial", &am33xx_serial[5] }, 92983e3700STom Rini # endif 93983e3700STom Rini # endif 94983e3700STom Rini }; 95983e3700STom Rini 96983e3700STom Rini #ifdef CONFIG_DM_GPIO 97983e3700STom Rini static const struct omap_gpio_platdata am33xx_gpio[] = { 98983e3700STom Rini { 0, AM33XX_GPIO0_BASE }, 99983e3700STom Rini { 1, AM33XX_GPIO1_BASE }, 100983e3700STom Rini { 2, AM33XX_GPIO2_BASE }, 101983e3700STom Rini { 3, AM33XX_GPIO3_BASE }, 102983e3700STom Rini #ifdef CONFIG_AM43XX 103983e3700STom Rini { 4, AM33XX_GPIO4_BASE }, 104983e3700STom Rini { 5, AM33XX_GPIO5_BASE }, 105983e3700STom Rini #endif 106983e3700STom Rini }; 107983e3700STom Rini 108983e3700STom Rini U_BOOT_DEVICES(am33xx_gpios) = { 109983e3700STom Rini { "gpio_omap", &am33xx_gpio[0] }, 110983e3700STom Rini { "gpio_omap", &am33xx_gpio[1] }, 111983e3700STom Rini { "gpio_omap", &am33xx_gpio[2] }, 112983e3700STom Rini { "gpio_omap", &am33xx_gpio[3] }, 113983e3700STom Rini #ifdef CONFIG_AM43XX 114983e3700STom Rini { "gpio_omap", &am33xx_gpio[4] }, 115983e3700STom Rini { "gpio_omap", &am33xx_gpio[5] }, 116983e3700STom Rini #endif 117983e3700STom Rini }; 118983e3700STom Rini #endif 119983e3700STom Rini #endif 120983e3700STom Rini 121983e3700STom Rini #ifndef CONFIG_DM_GPIO 122983e3700STom Rini static const struct gpio_bank gpio_bank_am33xx[] = { 123983e3700STom Rini { (void *)AM33XX_GPIO0_BASE }, 124983e3700STom Rini { (void *)AM33XX_GPIO1_BASE }, 125983e3700STom Rini { (void *)AM33XX_GPIO2_BASE }, 126983e3700STom Rini { (void *)AM33XX_GPIO3_BASE }, 127983e3700STom Rini #ifdef CONFIG_AM43XX 128983e3700STom Rini { (void *)AM33XX_GPIO4_BASE }, 129983e3700STom Rini { (void *)AM33XX_GPIO5_BASE }, 130983e3700STom Rini #endif 131983e3700STom Rini }; 132983e3700STom Rini 133983e3700STom Rini const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 134983e3700STom Rini #endif 135983e3700STom Rini 136d5abcf94SJean-Jacques Hiblot #if defined(CONFIG_MMC_OMAP_HS) 137983e3700STom Rini int cpu_mmc_init(bd_t *bis) 138983e3700STom Rini { 139983e3700STom Rini int ret; 140983e3700STom Rini 141983e3700STom Rini ret = omap_mmc_init(0, 0, 0, -1, -1); 142983e3700STom Rini if (ret) 143983e3700STom Rini return ret; 144983e3700STom Rini 145983e3700STom Rini return omap_mmc_init(1, 0, 0, -1, -1); 146983e3700STom Rini } 147983e3700STom Rini #endif 148983e3700STom Rini 1497619badbSTero Kristo /* 1507619badbSTero Kristo * RTC only with DDR in self-refresh mode magic value, checked against during 1517619badbSTero Kristo * boot to see if we have a valid config. This should be in sync with the value 1527619badbSTero Kristo * that will be in drivers/soc/ti/pm33xx.c. 1537619badbSTero Kristo */ 1547619badbSTero Kristo #define RTC_MAGIC_VAL 0x8cd0 1557619badbSTero Kristo 1567619badbSTero Kristo /* Board type field bit shift for RTC only with DDR in self-refresh mode */ 1577619badbSTero Kristo #define RTC_BOARD_TYPE_SHIFT 16 1587619badbSTero Kristo 159983e3700STom Rini /* AM33XX has two MUSB controllers which can be host or gadget */ 160983e3700STom Rini #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 16119570221SMugunthan V N (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 16219570221SMugunthan V N (!defined(CONFIG_DM_USB)) 163983e3700STom Rini static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 164983e3700STom Rini 165983e3700STom Rini /* USB 2.0 PHY Control */ 166983e3700STom Rini #define CM_PHY_PWRDN (1 << 0) 167983e3700STom Rini #define CM_PHY_OTG_PWRDN (1 << 1) 168983e3700STom Rini #define OTGVDET_EN (1 << 19) 169983e3700STom Rini #define OTGSESSENDEN (1 << 20) 170983e3700STom Rini 171983e3700STom Rini static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 172983e3700STom Rini { 173983e3700STom Rini if (on) { 174983e3700STom Rini clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 175983e3700STom Rini OTGVDET_EN | OTGSESSENDEN); 176983e3700STom Rini } else { 177983e3700STom Rini clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 178983e3700STom Rini } 179983e3700STom Rini } 180983e3700STom Rini 181983e3700STom Rini static struct musb_hdrc_config musb_config = { 182983e3700STom Rini .multipoint = 1, 183983e3700STom Rini .dyn_fifo = 1, 184983e3700STom Rini .num_eps = 16, 185983e3700STom Rini .ram_bits = 12, 186983e3700STom Rini }; 187983e3700STom Rini 188983e3700STom Rini #ifdef CONFIG_AM335X_USB0 1891cac34ceSMugunthan V N static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 190983e3700STom Rini { 191983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 192983e3700STom Rini } 193983e3700STom Rini 194983e3700STom Rini struct omap_musb_board_data otg0_board_data = { 195983e3700STom Rini .set_phy_power = am33xx_otg0_set_phy_power, 196983e3700STom Rini }; 197983e3700STom Rini 198983e3700STom Rini static struct musb_hdrc_platform_data otg0_plat = { 199983e3700STom Rini .mode = CONFIG_AM335X_USB0_MODE, 200983e3700STom Rini .config = &musb_config, 201983e3700STom Rini .power = 50, 202983e3700STom Rini .platform_ops = &musb_dsps_ops, 203983e3700STom Rini .board_data = &otg0_board_data, 204983e3700STom Rini }; 205983e3700STom Rini #endif 206983e3700STom Rini 207983e3700STom Rini #ifdef CONFIG_AM335X_USB1 2081cac34ceSMugunthan V N static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 209983e3700STom Rini { 210983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 211983e3700STom Rini } 212983e3700STom Rini 213983e3700STom Rini struct omap_musb_board_data otg1_board_data = { 214983e3700STom Rini .set_phy_power = am33xx_otg1_set_phy_power, 215983e3700STom Rini }; 216983e3700STom Rini 217983e3700STom Rini static struct musb_hdrc_platform_data otg1_plat = { 218983e3700STom Rini .mode = CONFIG_AM335X_USB1_MODE, 219983e3700STom Rini .config = &musb_config, 220983e3700STom Rini .power = 50, 221983e3700STom Rini .platform_ops = &musb_dsps_ops, 222983e3700STom Rini .board_data = &otg1_board_data, 223983e3700STom Rini }; 224983e3700STom Rini #endif 225983e3700STom Rini 226983e3700STom Rini int arch_misc_init(void) 227983e3700STom Rini { 228983e3700STom Rini #ifdef CONFIG_AM335X_USB0 229983e3700STom Rini musb_register(&otg0_plat, &otg0_board_data, 230983e3700STom Rini (void *)USB0_OTG_BASE); 231983e3700STom Rini #endif 232983e3700STom Rini #ifdef CONFIG_AM335X_USB1 233983e3700STom Rini musb_register(&otg1_plat, &otg1_board_data, 234983e3700STom Rini (void *)USB1_OTG_BASE); 235983e3700STom Rini #endif 236409a81ddSAlexandru Gagniuc return 0; 237409a81ddSAlexandru Gagniuc } 238409a81ddSAlexandru Gagniuc 239409a81ddSAlexandru Gagniuc #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 240409a81ddSAlexandru Gagniuc 241409a81ddSAlexandru Gagniuc int arch_misc_init(void) 242409a81ddSAlexandru Gagniuc { 2433aec2648SMugunthan V N struct udevice *dev; 2443aec2648SMugunthan V N int ret; 2453aec2648SMugunthan V N 2463aec2648SMugunthan V N ret = uclass_first_device(UCLASS_MISC, &dev); 2473aec2648SMugunthan V N if (ret || !dev) 2483aec2648SMugunthan V N return ret; 249ba7916c7SMugunthan V N 250ba7916c7SMugunthan V N #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 251ba7916c7SMugunthan V N ret = usb_ether_init(); 252ba7916c7SMugunthan V N if (ret) { 2539b643e31SMasahiro Yamada pr_err("USB ether init failed\n"); 254ba7916c7SMugunthan V N return ret; 255ba7916c7SMugunthan V N } 256ba7916c7SMugunthan V N #endif 257409a81ddSAlexandru Gagniuc 258983e3700STom Rini return 0; 259983e3700STom Rini } 260983e3700STom Rini 261409a81ddSAlexandru Gagniuc #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 262409a81ddSAlexandru Gagniuc 263983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 2647619badbSTero Kristo 2657619badbSTero Kristo #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 2667619badbSTero Kristo (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 2677619badbSTero Kristo static void rtc32k_unlock(struct davinci_rtc *rtc) 2687619badbSTero Kristo { 2697619badbSTero Kristo /* 2707619badbSTero Kristo * Unlock the RTC's registers. For more details please see the 2717619badbSTero Kristo * RTC_SS section of the TRM. In order to unlock we need to 2727619badbSTero Kristo * write these specific values (keys) in this order. 2737619badbSTero Kristo */ 2747619badbSTero Kristo writel(RTC_KICK0R_WE, &rtc->kick0r); 2757619badbSTero Kristo writel(RTC_KICK1R_WE, &rtc->kick1r); 2767619badbSTero Kristo } 2777619badbSTero Kristo #endif 2787619badbSTero Kristo 2797619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 2807619badbSTero Kristo /* 2817619badbSTero Kristo * Write contents of the RTC_SCRATCH1 register based on board type 2827619badbSTero Kristo * Two things are passed 2837619badbSTero Kristo * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 2847619badbSTero Kristo * control gets to kernel, kernel reads the scratchpad register and gets to 2857619badbSTero Kristo * know that bootloader has rtc_only support. 2867619badbSTero Kristo * 2877619badbSTero Kristo * Second important thing is the board type (16:31). This is needed in the 2887619badbSTero Kristo * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 2897619badbSTero Kristo * identify the board type and we go ahead and copy the board strings to 2907619badbSTero Kristo * am43xx_board_name. 2917619badbSTero Kristo */ 2927619badbSTero Kristo void update_rtc_magic(void) 2937619badbSTero Kristo { 2947619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 2957619badbSTero Kristo u32 magic = RTC_MAGIC_VAL; 2967619badbSTero Kristo 2977619badbSTero Kristo magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 2987619badbSTero Kristo 2997619badbSTero Kristo rtc32k_unlock(rtc); 3007619badbSTero Kristo 3017619badbSTero Kristo /* write magic */ 3027619badbSTero Kristo writel(magic, &rtc->scratch1); 3037619badbSTero Kristo } 3047619badbSTero Kristo #endif 3057619badbSTero Kristo 306983e3700STom Rini /* 307983e3700STom Rini * In the case of non-SPL based booting we'll want to call these 308983e3700STom Rini * functions a tiny bit later as it will require gd to be set and cleared 309983e3700STom Rini * and that's not true in s_init in this case so we cannot do it there. 310983e3700STom Rini */ 311983e3700STom Rini int board_early_init_f(void) 312983e3700STom Rini { 313983e3700STom Rini prcm_init(); 314983e3700STom Rini set_mux_conf_regs(); 3157619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 3167619badbSTero Kristo update_rtc_magic(); 3177619badbSTero Kristo #endif 318983e3700STom Rini return 0; 319983e3700STom Rini } 320983e3700STom Rini 321983e3700STom Rini /* 322983e3700STom Rini * This function is the place to do per-board things such as ramp up the 323983e3700STom Rini * MPU clock frequency. 324983e3700STom Rini */ 325983e3700STom Rini __weak void am33xx_spl_board_init(void) 326983e3700STom Rini { 327983e3700STom Rini } 328983e3700STom Rini 329983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 330983e3700STom Rini static void rtc32k_enable(void) 331983e3700STom Rini { 332983e3700STom Rini struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 333983e3700STom Rini 3347619badbSTero Kristo rtc32k_unlock(rtc); 335983e3700STom Rini 336983e3700STom Rini /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 337983e3700STom Rini writel((1 << 3) | (1 << 6), &rtc->osc); 338983e3700STom Rini } 339983e3700STom Rini #endif 340983e3700STom Rini 341983e3700STom Rini static void uart_soft_reset(void) 342983e3700STom Rini { 343983e3700STom Rini struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 344983e3700STom Rini u32 regval; 345983e3700STom Rini 346983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 347983e3700STom Rini regval |= UART_RESET; 348983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 349983e3700STom Rini while ((readl(&uart_base->uartsyssts) & 350983e3700STom Rini UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 351983e3700STom Rini ; 352983e3700STom Rini 353983e3700STom Rini /* Disable smart idle */ 354983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 355983e3700STom Rini regval |= UART_SMART_IDLE_EN; 356983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 357983e3700STom Rini } 358983e3700STom Rini 359983e3700STom Rini static void watchdog_disable(void) 360983e3700STom Rini { 361983e3700STom Rini struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 362983e3700STom Rini 363983e3700STom Rini writel(0xAAAA, &wdtimer->wdtwspr); 364983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 365983e3700STom Rini ; 366983e3700STom Rini writel(0x5555, &wdtimer->wdtwspr); 367983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 368983e3700STom Rini ; 369983e3700STom Rini } 370983e3700STom Rini 3717619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 3727619badbSTero Kristo /* 3737619badbSTero Kristo * Check if we are executing rtc-only + DDR mode, and resume from it if needed 3747619badbSTero Kristo */ 3757619badbSTero Kristo static void rtc_only(void) 3767619badbSTero Kristo { 3777619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 378025a0d40SRuss Dill struct prm_device_inst *prm_device = 379025a0d40SRuss Dill (struct prm_device_inst *)PRM_DEVICE_INST; 380025a0d40SRuss Dill 3817619badbSTero Kristo u32 scratch1; 3827619badbSTero Kristo void (*resume_func)(void); 3837619badbSTero Kristo 3847619badbSTero Kristo scratch1 = readl(&rtc->scratch1); 3857619badbSTero Kristo 3867619badbSTero Kristo /* 3877619badbSTero Kristo * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 3887619badbSTero Kristo * written to this register when we want to wake up from RTC only 3897619badbSTero Kristo * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 3907619badbSTero Kristo * bits 0-15: RTC_MAGIC_VAL 3917619badbSTero Kristo * bits 16-31: board type (needed for sdram_init) 3927619badbSTero Kristo */ 3937619badbSTero Kristo if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 3947619badbSTero Kristo return; 3957619badbSTero Kristo 3967619badbSTero Kristo rtc32k_unlock(rtc); 3977619badbSTero Kristo 3987619badbSTero Kristo /* Clear RTC magic */ 3997619badbSTero Kristo writel(0, &rtc->scratch1); 4007619badbSTero Kristo 4017619badbSTero Kristo /* 4027619badbSTero Kristo * Update board type based on value stored on RTC_SCRATCH1, this 4037619badbSTero Kristo * is done so that we don't need to read the board type from eeprom 4047619badbSTero Kristo * over i2c bus which is expensive 4057619badbSTero Kristo */ 4067619badbSTero Kristo rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 4077619badbSTero Kristo 408025a0d40SRuss Dill /* 409025a0d40SRuss Dill * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 410025a0d40SRuss Dill * are resuming from self-refresh. This avoids an unnecessary re-init 411025a0d40SRuss Dill * of the DDR. The re-init takes time and we would need to wait for 412025a0d40SRuss Dill * it to complete before accessing DDR to avoid L3 NOC errors. 413025a0d40SRuss Dill */ 414025a0d40SRuss Dill writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 415025a0d40SRuss Dill 4167619badbSTero Kristo rtc_only_prcm_init(); 4177619badbSTero Kristo sdram_init(); 4187619badbSTero Kristo 419025a0d40SRuss Dill /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ 420025a0d40SRuss Dill writel(0, &prm_device->emif_ctrl); 421025a0d40SRuss Dill 4227619badbSTero Kristo resume_func = (void *)readl(&rtc->scratch0); 4237619badbSTero Kristo if (resume_func) 4247619badbSTero Kristo resume_func(); 4257619badbSTero Kristo } 4267619badbSTero Kristo #endif 4277619badbSTero Kristo 428983e3700STom Rini void s_init(void) 429983e3700STom Rini { 4307619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 4317619badbSTero Kristo rtc_only(); 4327619badbSTero Kristo #endif 433983e3700STom Rini } 434983e3700STom Rini 435983e3700STom Rini void early_system_init(void) 436983e3700STom Rini { 437983e3700STom Rini /* 438983e3700STom Rini * The ROM will only have set up sufficient pinmux to allow for the 439983e3700STom Rini * first 4KiB NOR to be read, we must finish doing what we know of 440983e3700STom Rini * the NOR mux in this space in order to continue. 441983e3700STom Rini */ 442983e3700STom Rini #ifdef CONFIG_NOR_BOOT 443983e3700STom Rini enable_norboot_pin_mux(); 444983e3700STom Rini #endif 445983e3700STom Rini watchdog_disable(); 446983e3700STom Rini set_uart_mux_conf(); 447983e3700STom Rini setup_early_clocks(); 448983e3700STom Rini uart_soft_reset(); 4494bd754d8SLokesh Vutla #ifdef CONFIG_SPL_BUILD 4504bd754d8SLokesh Vutla /* 4514bd754d8SLokesh Vutla * Save the boot parameters passed from romcode. 4524bd754d8SLokesh Vutla * We cannot delay the saving further than this, 4534bd754d8SLokesh Vutla * to prevent overwrites. 4544bd754d8SLokesh Vutla */ 4554bd754d8SLokesh Vutla save_omap_boot_params(); 4564bd754d8SLokesh Vutla #endif 457878d8856SLokesh Vutla #ifdef CONFIG_DEBUG_UART_OMAP 458878d8856SLokesh Vutla debug_uart_init(); 459878d8856SLokesh Vutla #endif 460983e3700STom Rini #ifdef CONFIG_TI_I2C_BOARD_DETECT 461983e3700STom Rini do_board_detect(); 462983e3700STom Rini #endif 463b442e16bSFaiz Abbas #ifdef CONFIG_SPL_BUILD 464b442e16bSFaiz Abbas spl_early_init(); 465b442e16bSFaiz Abbas #endif 466983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 467983e3700STom Rini /* Enable RTC32K clock */ 468983e3700STom Rini rtc32k_enable(); 469983e3700STom Rini #endif 470983e3700STom Rini } 471983e3700STom Rini 472983e3700STom Rini #ifdef CONFIG_SPL_BUILD 473983e3700STom Rini void board_init_f(ulong dummy) 474983e3700STom Rini { 47500bbe96eSSemen Protsenko hw_data_init(); 476983e3700STom Rini early_system_init(); 477983e3700STom Rini board_early_init_f(); 478983e3700STom Rini sdram_init(); 47986282798SLokesh Vutla /* dram_init must store complete ramsize in gd->ram_size */ 48086282798SLokesh Vutla gd->ram_size = get_ram_size( 48186282798SLokesh Vutla (void *)CONFIG_SYS_SDRAM_BASE, 48286282798SLokesh Vutla CONFIG_MAX_RAM_BANK_SIZE); 483983e3700STom Rini } 484983e3700STom Rini #endif 485983e3700STom Rini 486983e3700STom Rini #endif 487983e3700STom Rini 488983e3700STom Rini int arch_cpu_init_dm(void) 489983e3700STom Rini { 49000bbe96eSSemen Protsenko hw_data_init(); 491983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 492983e3700STom Rini early_system_init(); 493983e3700STom Rini #endif 494983e3700STom Rini return 0; 495983e3700STom Rini } 496