183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2983e3700STom Rini /* 3983e3700STom Rini * board.c 4983e3700STom Rini * 5983e3700STom Rini * Common board functions for AM33XX based boards 6983e3700STom Rini * 7983e3700STom Rini * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8983e3700STom Rini */ 9983e3700STom Rini 10983e3700STom Rini #include <common.h> 11983e3700STom Rini #include <dm.h> 12878d8856SLokesh Vutla #include <debug_uart.h> 13983e3700STom Rini #include <errno.h> 14983e3700STom Rini #include <ns16550.h> 15983e3700STom Rini #include <spl.h> 16983e3700STom Rini #include <asm/arch/cpu.h> 17983e3700STom Rini #include <asm/arch/hardware.h> 18983e3700STom Rini #include <asm/arch/omap.h> 19983e3700STom Rini #include <asm/arch/ddr_defs.h> 20983e3700STom Rini #include <asm/arch/clock.h> 21983e3700STom Rini #include <asm/arch/gpio.h> 220e6e67c6SJean-Jacques Hiblot #include <asm/arch/i2c.h> 23983e3700STom Rini #include <asm/arch/mem.h> 24983e3700STom Rini #include <asm/arch/mmc_host_def.h> 25983e3700STom Rini #include <asm/arch/sys_proto.h> 26983e3700STom Rini #include <asm/io.h> 27983e3700STom Rini #include <asm/emif.h> 28983e3700STom Rini #include <asm/gpio.h> 2900bbe96eSSemen Protsenko #include <asm/omap_common.h> 30983e3700STom Rini #include <i2c.h> 31983e3700STom Rini #include <miiphy.h> 32983e3700STom Rini #include <cpsw.h> 33983e3700STom Rini #include <linux/errno.h> 34983e3700STom Rini #include <linux/compiler.h> 35983e3700STom Rini #include <linux/usb/ch9.h> 36983e3700STom Rini #include <linux/usb/gadget.h> 37983e3700STom Rini #include <linux/usb/musb.h> 38983e3700STom Rini #include <asm/omap_musb.h> 39983e3700STom Rini #include <asm/davinci_rtc.h> 40983e3700STom Rini 41983e3700STom Rini DECLARE_GLOBAL_DATA_PTR; 42983e3700STom Rini 4386277339STom Rini int dram_init(void) 4486277339STom Rini { 4586277339STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 4686277339STom Rini sdram_init(); 4786277339STom Rini #endif 4886277339STom Rini 4986277339STom Rini /* dram_init must store complete ramsize in gd->ram_size */ 5086277339STom Rini gd->ram_size = get_ram_size( 5186277339STom Rini (void *)CONFIG_SYS_SDRAM_BASE, 5286277339STom Rini CONFIG_MAX_RAM_BANK_SIZE); 5386277339STom Rini return 0; 5486277339STom Rini } 5586277339STom Rini 5686277339STom Rini int dram_init_banksize(void) 5786277339STom Rini { 5886277339STom Rini gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 5986277339STom Rini gd->bd->bi_dram[0].size = gd->ram_size; 6086277339STom Rini 6186277339STom Rini return 0; 6286277339STom Rini } 6386277339STom Rini 64983e3700STom Rini #if !CONFIG_IS_ENABLED(OF_CONTROL) 65983e3700STom Rini static const struct ns16550_platdata am33xx_serial[] = { 6617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 6717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 68983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 6917fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 7017fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 71983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 7217fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 7317fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7417fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 7517fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 7717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 7817fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 7917fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 80983e3700STom Rini # endif 81983e3700STom Rini # endif 82983e3700STom Rini }; 83983e3700STom Rini 84983e3700STom Rini U_BOOT_DEVICES(am33xx_uarts) = { 85983e3700STom Rini { "ns16550_serial", &am33xx_serial[0] }, 86983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2 87983e3700STom Rini { "ns16550_serial", &am33xx_serial[1] }, 88983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3 89983e3700STom Rini { "ns16550_serial", &am33xx_serial[2] }, 90983e3700STom Rini { "ns16550_serial", &am33xx_serial[3] }, 91983e3700STom Rini { "ns16550_serial", &am33xx_serial[4] }, 92983e3700STom Rini { "ns16550_serial", &am33xx_serial[5] }, 93983e3700STom Rini # endif 94983e3700STom Rini # endif 95983e3700STom Rini }; 96983e3700STom Rini 970e6e67c6SJean-Jacques Hiblot #ifdef CONFIG_DM_I2C 980e6e67c6SJean-Jacques Hiblot static const struct omap_i2c_platdata am33xx_i2c[] = { 990e6e67c6SJean-Jacques Hiblot { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, 1000e6e67c6SJean-Jacques Hiblot { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, 1010e6e67c6SJean-Jacques Hiblot { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, 1020e6e67c6SJean-Jacques Hiblot }; 1030e6e67c6SJean-Jacques Hiblot 1040e6e67c6SJean-Jacques Hiblot U_BOOT_DEVICES(am33xx_i2c) = { 1050e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[0] }, 1060e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[1] }, 1070e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[2] }, 1080e6e67c6SJean-Jacques Hiblot }; 1090e6e67c6SJean-Jacques Hiblot #endif 1100e6e67c6SJean-Jacques Hiblot 111983e3700STom Rini #ifdef CONFIG_DM_GPIO 112983e3700STom Rini static const struct omap_gpio_platdata am33xx_gpio[] = { 113983e3700STom Rini { 0, AM33XX_GPIO0_BASE }, 114983e3700STom Rini { 1, AM33XX_GPIO1_BASE }, 115983e3700STom Rini { 2, AM33XX_GPIO2_BASE }, 116983e3700STom Rini { 3, AM33XX_GPIO3_BASE }, 117983e3700STom Rini #ifdef CONFIG_AM43XX 118983e3700STom Rini { 4, AM33XX_GPIO4_BASE }, 119983e3700STom Rini { 5, AM33XX_GPIO5_BASE }, 120983e3700STom Rini #endif 121983e3700STom Rini }; 122983e3700STom Rini 123983e3700STom Rini U_BOOT_DEVICES(am33xx_gpios) = { 124983e3700STom Rini { "gpio_omap", &am33xx_gpio[0] }, 125983e3700STom Rini { "gpio_omap", &am33xx_gpio[1] }, 126983e3700STom Rini { "gpio_omap", &am33xx_gpio[2] }, 127983e3700STom Rini { "gpio_omap", &am33xx_gpio[3] }, 128983e3700STom Rini #ifdef CONFIG_AM43XX 129983e3700STom Rini { "gpio_omap", &am33xx_gpio[4] }, 130983e3700STom Rini { "gpio_omap", &am33xx_gpio[5] }, 131983e3700STom Rini #endif 132983e3700STom Rini }; 133983e3700STom Rini #endif 134983e3700STom Rini #endif 135983e3700STom Rini 136983e3700STom Rini #ifndef CONFIG_DM_GPIO 137983e3700STom Rini static const struct gpio_bank gpio_bank_am33xx[] = { 138983e3700STom Rini { (void *)AM33XX_GPIO0_BASE }, 139983e3700STom Rini { (void *)AM33XX_GPIO1_BASE }, 140983e3700STom Rini { (void *)AM33XX_GPIO2_BASE }, 141983e3700STom Rini { (void *)AM33XX_GPIO3_BASE }, 142983e3700STom Rini #ifdef CONFIG_AM43XX 143983e3700STom Rini { (void *)AM33XX_GPIO4_BASE }, 144983e3700STom Rini { (void *)AM33XX_GPIO5_BASE }, 145983e3700STom Rini #endif 146983e3700STom Rini }; 147983e3700STom Rini 148983e3700STom Rini const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 149983e3700STom Rini #endif 150983e3700STom Rini 151d5abcf94SJean-Jacques Hiblot #if defined(CONFIG_MMC_OMAP_HS) 152983e3700STom Rini int cpu_mmc_init(bd_t *bis) 153983e3700STom Rini { 154983e3700STom Rini int ret; 155983e3700STom Rini 156983e3700STom Rini ret = omap_mmc_init(0, 0, 0, -1, -1); 157983e3700STom Rini if (ret) 158983e3700STom Rini return ret; 159983e3700STom Rini 160983e3700STom Rini return omap_mmc_init(1, 0, 0, -1, -1); 161983e3700STom Rini } 162983e3700STom Rini #endif 163983e3700STom Rini 1647619badbSTero Kristo /* 1657619badbSTero Kristo * RTC only with DDR in self-refresh mode magic value, checked against during 1667619badbSTero Kristo * boot to see if we have a valid config. This should be in sync with the value 1677619badbSTero Kristo * that will be in drivers/soc/ti/pm33xx.c. 1687619badbSTero Kristo */ 1697619badbSTero Kristo #define RTC_MAGIC_VAL 0x8cd0 1707619badbSTero Kristo 1717619badbSTero Kristo /* Board type field bit shift for RTC only with DDR in self-refresh mode */ 1727619badbSTero Kristo #define RTC_BOARD_TYPE_SHIFT 16 1737619badbSTero Kristo 174983e3700STom Rini /* AM33XX has two MUSB controllers which can be host or gadget */ 175983e3700STom Rini #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 17619570221SMugunthan V N (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 17719570221SMugunthan V N (!defined(CONFIG_DM_USB)) 178983e3700STom Rini static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 179983e3700STom Rini 180983e3700STom Rini /* USB 2.0 PHY Control */ 181983e3700STom Rini #define CM_PHY_PWRDN (1 << 0) 182983e3700STom Rini #define CM_PHY_OTG_PWRDN (1 << 1) 183983e3700STom Rini #define OTGVDET_EN (1 << 19) 184983e3700STom Rini #define OTGSESSENDEN (1 << 20) 185983e3700STom Rini 186983e3700STom Rini static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 187983e3700STom Rini { 188983e3700STom Rini if (on) { 189983e3700STom Rini clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 190983e3700STom Rini OTGVDET_EN | OTGSESSENDEN); 191983e3700STom Rini } else { 192983e3700STom Rini clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 193983e3700STom Rini } 194983e3700STom Rini } 195983e3700STom Rini 196983e3700STom Rini static struct musb_hdrc_config musb_config = { 197983e3700STom Rini .multipoint = 1, 198983e3700STom Rini .dyn_fifo = 1, 199983e3700STom Rini .num_eps = 16, 200983e3700STom Rini .ram_bits = 12, 201983e3700STom Rini }; 202983e3700STom Rini 203983e3700STom Rini #ifdef CONFIG_AM335X_USB0 2041cac34ceSMugunthan V N static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 205983e3700STom Rini { 206983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 207983e3700STom Rini } 208983e3700STom Rini 209983e3700STom Rini struct omap_musb_board_data otg0_board_data = { 210983e3700STom Rini .set_phy_power = am33xx_otg0_set_phy_power, 211983e3700STom Rini }; 212983e3700STom Rini 213983e3700STom Rini static struct musb_hdrc_platform_data otg0_plat = { 214983e3700STom Rini .mode = CONFIG_AM335X_USB0_MODE, 215983e3700STom Rini .config = &musb_config, 216983e3700STom Rini .power = 50, 217983e3700STom Rini .platform_ops = &musb_dsps_ops, 218983e3700STom Rini .board_data = &otg0_board_data, 219983e3700STom Rini }; 220983e3700STom Rini #endif 221983e3700STom Rini 222983e3700STom Rini #ifdef CONFIG_AM335X_USB1 2231cac34ceSMugunthan V N static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 224983e3700STom Rini { 225983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 226983e3700STom Rini } 227983e3700STom Rini 228983e3700STom Rini struct omap_musb_board_data otg1_board_data = { 229983e3700STom Rini .set_phy_power = am33xx_otg1_set_phy_power, 230983e3700STom Rini }; 231983e3700STom Rini 232983e3700STom Rini static struct musb_hdrc_platform_data otg1_plat = { 233983e3700STom Rini .mode = CONFIG_AM335X_USB1_MODE, 234983e3700STom Rini .config = &musb_config, 235983e3700STom Rini .power = 50, 236983e3700STom Rini .platform_ops = &musb_dsps_ops, 237983e3700STom Rini .board_data = &otg1_board_data, 238983e3700STom Rini }; 239983e3700STom Rini #endif 240983e3700STom Rini 241983e3700STom Rini int arch_misc_init(void) 242983e3700STom Rini { 243983e3700STom Rini #ifdef CONFIG_AM335X_USB0 244983e3700STom Rini musb_register(&otg0_plat, &otg0_board_data, 245983e3700STom Rini (void *)USB0_OTG_BASE); 246983e3700STom Rini #endif 247983e3700STom Rini #ifdef CONFIG_AM335X_USB1 248983e3700STom Rini musb_register(&otg1_plat, &otg1_board_data, 249983e3700STom Rini (void *)USB1_OTG_BASE); 250983e3700STom Rini #endif 251409a81ddSAlexandru Gagniuc return 0; 252409a81ddSAlexandru Gagniuc } 253409a81ddSAlexandru Gagniuc 254409a81ddSAlexandru Gagniuc #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 255409a81ddSAlexandru Gagniuc 256409a81ddSAlexandru Gagniuc int arch_misc_init(void) 257409a81ddSAlexandru Gagniuc { 2583aec2648SMugunthan V N struct udevice *dev; 2593aec2648SMugunthan V N int ret; 2603aec2648SMugunthan V N 2613aec2648SMugunthan V N ret = uclass_first_device(UCLASS_MISC, &dev); 2623aec2648SMugunthan V N if (ret || !dev) 2633aec2648SMugunthan V N return ret; 264ba7916c7SMugunthan V N 265ba7916c7SMugunthan V N #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 266ba7916c7SMugunthan V N ret = usb_ether_init(); 267ba7916c7SMugunthan V N if (ret) { 2689b643e31SMasahiro Yamada pr_err("USB ether init failed\n"); 269ba7916c7SMugunthan V N return ret; 270ba7916c7SMugunthan V N } 271ba7916c7SMugunthan V N #endif 272409a81ddSAlexandru Gagniuc 273983e3700STom Rini return 0; 274983e3700STom Rini } 275983e3700STom Rini 276409a81ddSAlexandru Gagniuc #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 277409a81ddSAlexandru Gagniuc 278983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 2797619badbSTero Kristo 2807619badbSTero Kristo #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 2817619badbSTero Kristo (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 2827619badbSTero Kristo static void rtc32k_unlock(struct davinci_rtc *rtc) 2837619badbSTero Kristo { 2847619badbSTero Kristo /* 2857619badbSTero Kristo * Unlock the RTC's registers. For more details please see the 2867619badbSTero Kristo * RTC_SS section of the TRM. In order to unlock we need to 2877619badbSTero Kristo * write these specific values (keys) in this order. 2887619badbSTero Kristo */ 2897619badbSTero Kristo writel(RTC_KICK0R_WE, &rtc->kick0r); 2907619badbSTero Kristo writel(RTC_KICK1R_WE, &rtc->kick1r); 2917619badbSTero Kristo } 2927619badbSTero Kristo #endif 2937619badbSTero Kristo 2947619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 2957619badbSTero Kristo /* 2967619badbSTero Kristo * Write contents of the RTC_SCRATCH1 register based on board type 2977619badbSTero Kristo * Two things are passed 2987619badbSTero Kristo * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 2997619badbSTero Kristo * control gets to kernel, kernel reads the scratchpad register and gets to 3007619badbSTero Kristo * know that bootloader has rtc_only support. 3017619badbSTero Kristo * 3027619badbSTero Kristo * Second important thing is the board type (16:31). This is needed in the 3037619badbSTero Kristo * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 3047619badbSTero Kristo * identify the board type and we go ahead and copy the board strings to 3057619badbSTero Kristo * am43xx_board_name. 3067619badbSTero Kristo */ 3077619badbSTero Kristo void update_rtc_magic(void) 3087619badbSTero Kristo { 3097619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 3107619badbSTero Kristo u32 magic = RTC_MAGIC_VAL; 3117619badbSTero Kristo 3127619badbSTero Kristo magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 3137619badbSTero Kristo 3147619badbSTero Kristo rtc32k_unlock(rtc); 3157619badbSTero Kristo 3167619badbSTero Kristo /* write magic */ 3177619badbSTero Kristo writel(magic, &rtc->scratch1); 3187619badbSTero Kristo } 3197619badbSTero Kristo #endif 3207619badbSTero Kristo 321983e3700STom Rini /* 322983e3700STom Rini * In the case of non-SPL based booting we'll want to call these 323983e3700STom Rini * functions a tiny bit later as it will require gd to be set and cleared 324983e3700STom Rini * and that's not true in s_init in this case so we cannot do it there. 325983e3700STom Rini */ 326983e3700STom Rini int board_early_init_f(void) 327983e3700STom Rini { 328983e3700STom Rini prcm_init(); 329983e3700STom Rini set_mux_conf_regs(); 3307619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 3317619badbSTero Kristo update_rtc_magic(); 3327619badbSTero Kristo #endif 333983e3700STom Rini return 0; 334983e3700STom Rini } 335983e3700STom Rini 336983e3700STom Rini /* 337983e3700STom Rini * This function is the place to do per-board things such as ramp up the 338983e3700STom Rini * MPU clock frequency. 339983e3700STom Rini */ 340983e3700STom Rini __weak void am33xx_spl_board_init(void) 341983e3700STom Rini { 342983e3700STom Rini } 343983e3700STom Rini 344983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 345983e3700STom Rini static void rtc32k_enable(void) 346983e3700STom Rini { 347983e3700STom Rini struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 348983e3700STom Rini 3497619badbSTero Kristo rtc32k_unlock(rtc); 350983e3700STom Rini 351983e3700STom Rini /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 352983e3700STom Rini writel((1 << 3) | (1 << 6), &rtc->osc); 353983e3700STom Rini } 354983e3700STom Rini #endif 355983e3700STom Rini 356983e3700STom Rini static void uart_soft_reset(void) 357983e3700STom Rini { 358983e3700STom Rini struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 359983e3700STom Rini u32 regval; 360983e3700STom Rini 361983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 362983e3700STom Rini regval |= UART_RESET; 363983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 364983e3700STom Rini while ((readl(&uart_base->uartsyssts) & 365983e3700STom Rini UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 366983e3700STom Rini ; 367983e3700STom Rini 368983e3700STom Rini /* Disable smart idle */ 369983e3700STom Rini regval = readl(&uart_base->uartsyscfg); 370983e3700STom Rini regval |= UART_SMART_IDLE_EN; 371983e3700STom Rini writel(regval, &uart_base->uartsyscfg); 372983e3700STom Rini } 373983e3700STom Rini 374983e3700STom Rini static void watchdog_disable(void) 375983e3700STom Rini { 376983e3700STom Rini struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 377983e3700STom Rini 378983e3700STom Rini writel(0xAAAA, &wdtimer->wdtwspr); 379983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 380983e3700STom Rini ; 381983e3700STom Rini writel(0x5555, &wdtimer->wdtwspr); 382983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0) 383983e3700STom Rini ; 384983e3700STom Rini } 385983e3700STom Rini 3867619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 3877619badbSTero Kristo /* 3887619badbSTero Kristo * Check if we are executing rtc-only + DDR mode, and resume from it if needed 3897619badbSTero Kristo */ 3907619badbSTero Kristo static void rtc_only(void) 3917619badbSTero Kristo { 3927619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 393025a0d40SRuss Dill struct prm_device_inst *prm_device = 394025a0d40SRuss Dill (struct prm_device_inst *)PRM_DEVICE_INST; 395025a0d40SRuss Dill 3967619badbSTero Kristo u32 scratch1; 3977619badbSTero Kristo void (*resume_func)(void); 3987619badbSTero Kristo 3997619badbSTero Kristo scratch1 = readl(&rtc->scratch1); 4007619badbSTero Kristo 4017619badbSTero Kristo /* 4027619badbSTero Kristo * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 4037619badbSTero Kristo * written to this register when we want to wake up from RTC only 4047619badbSTero Kristo * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 4057619badbSTero Kristo * bits 0-15: RTC_MAGIC_VAL 4067619badbSTero Kristo * bits 16-31: board type (needed for sdram_init) 4077619badbSTero Kristo */ 4087619badbSTero Kristo if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 4097619badbSTero Kristo return; 4107619badbSTero Kristo 4117619badbSTero Kristo rtc32k_unlock(rtc); 4127619badbSTero Kristo 4137619badbSTero Kristo /* Clear RTC magic */ 4147619badbSTero Kristo writel(0, &rtc->scratch1); 4157619badbSTero Kristo 4167619badbSTero Kristo /* 4177619badbSTero Kristo * Update board type based on value stored on RTC_SCRATCH1, this 4187619badbSTero Kristo * is done so that we don't need to read the board type from eeprom 4197619badbSTero Kristo * over i2c bus which is expensive 4207619badbSTero Kristo */ 4217619badbSTero Kristo rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 4227619badbSTero Kristo 423025a0d40SRuss Dill /* 424025a0d40SRuss Dill * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 425025a0d40SRuss Dill * are resuming from self-refresh. This avoids an unnecessary re-init 426025a0d40SRuss Dill * of the DDR. The re-init takes time and we would need to wait for 427025a0d40SRuss Dill * it to complete before accessing DDR to avoid L3 NOC errors. 428025a0d40SRuss Dill */ 429025a0d40SRuss Dill writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 430025a0d40SRuss Dill 4317619badbSTero Kristo rtc_only_prcm_init(); 4327619badbSTero Kristo sdram_init(); 4337619badbSTero Kristo 434025a0d40SRuss Dill /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ 435025a0d40SRuss Dill writel(0, &prm_device->emif_ctrl); 436025a0d40SRuss Dill 4377619badbSTero Kristo resume_func = (void *)readl(&rtc->scratch0); 4387619badbSTero Kristo if (resume_func) 4397619badbSTero Kristo resume_func(); 4407619badbSTero Kristo } 4417619badbSTero Kristo #endif 4427619badbSTero Kristo 443983e3700STom Rini void s_init(void) 444983e3700STom Rini { 4457619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 4467619badbSTero Kristo rtc_only(); 4477619badbSTero Kristo #endif 448983e3700STom Rini } 449983e3700STom Rini 450983e3700STom Rini void early_system_init(void) 451983e3700STom Rini { 452983e3700STom Rini /* 453983e3700STom Rini * The ROM will only have set up sufficient pinmux to allow for the 454983e3700STom Rini * first 4KiB NOR to be read, we must finish doing what we know of 455983e3700STom Rini * the NOR mux in this space in order to continue. 456983e3700STom Rini */ 457983e3700STom Rini #ifdef CONFIG_NOR_BOOT 458983e3700STom Rini enable_norboot_pin_mux(); 459983e3700STom Rini #endif 460983e3700STom Rini watchdog_disable(); 461983e3700STom Rini set_uart_mux_conf(); 462983e3700STom Rini setup_early_clocks(); 463983e3700STom Rini uart_soft_reset(); 4644bd754d8SLokesh Vutla #ifdef CONFIG_SPL_BUILD 4654bd754d8SLokesh Vutla /* 4664bd754d8SLokesh Vutla * Save the boot parameters passed from romcode. 4674bd754d8SLokesh Vutla * We cannot delay the saving further than this, 4684bd754d8SLokesh Vutla * to prevent overwrites. 4694bd754d8SLokesh Vutla */ 4704bd754d8SLokesh Vutla save_omap_boot_params(); 4714bd754d8SLokesh Vutla #endif 472878d8856SLokesh Vutla #ifdef CONFIG_DEBUG_UART_OMAP 473878d8856SLokesh Vutla debug_uart_init(); 474878d8856SLokesh Vutla #endif 475*2b30b38bSJean-Jacques Hiblot 476b442e16bSFaiz Abbas #ifdef CONFIG_SPL_BUILD 477b442e16bSFaiz Abbas spl_early_init(); 478b442e16bSFaiz Abbas #endif 479*2b30b38bSJean-Jacques Hiblot 480*2b30b38bSJean-Jacques Hiblot #ifdef CONFIG_TI_I2C_BOARD_DETECT 481*2b30b38bSJean-Jacques Hiblot do_board_detect(); 482*2b30b38bSJean-Jacques Hiblot #endif 483*2b30b38bSJean-Jacques Hiblot 484983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 485983e3700STom Rini /* Enable RTC32K clock */ 486983e3700STom Rini rtc32k_enable(); 487983e3700STom Rini #endif 488983e3700STom Rini } 489983e3700STom Rini 490983e3700STom Rini #ifdef CONFIG_SPL_BUILD 491983e3700STom Rini void board_init_f(ulong dummy) 492983e3700STom Rini { 49300bbe96eSSemen Protsenko hw_data_init(); 494983e3700STom Rini early_system_init(); 495983e3700STom Rini board_early_init_f(); 496983e3700STom Rini sdram_init(); 49786282798SLokesh Vutla /* dram_init must store complete ramsize in gd->ram_size */ 49886282798SLokesh Vutla gd->ram_size = get_ram_size( 49986282798SLokesh Vutla (void *)CONFIG_SYS_SDRAM_BASE, 50086282798SLokesh Vutla CONFIG_MAX_RAM_BANK_SIZE); 501983e3700STom Rini } 502983e3700STom Rini #endif 503983e3700STom Rini 504983e3700STom Rini #endif 505983e3700STom Rini 506983e3700STom Rini int arch_cpu_init_dm(void) 507983e3700STom Rini { 50800bbe96eSSemen Protsenko hw_data_init(); 509983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT 510983e3700STom Rini early_system_init(); 511983e3700STom Rini #endif 512983e3700STom Rini return 0; 513983e3700STom Rini } 514