1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "high_speed_env_spec.h" 14 15 MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = { 16 /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */ 17 { 18 /* PEX: Change of Slew Rate port0 */ 19 SERDES_UNIT_PEX, 0x0, 20 (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21 21 }, { 22 /* PEX: Change PLL BW port0 */ 23 SERDES_UNIT_PEX, 0x0, 24 (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219 25 }, { 26 /* SATA: Slew rate change port 0 */ 27 SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31 28 }, { 29 /* SATA: Slew rate change port 0 */ 30 SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928 31 }, { 32 /* SATA: Slew rate change port 0 */ 33 SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0 34 }, { 35 /* SATA: Slew rate change port 0 */ 36 SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5 37 }, { 38 /* SGMII: FFE setting Port0 */ 39 SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F 40 }, { 41 /* SGMII: SELMUP and SELMUF Port0 */ 42 SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA 43 }, { 44 /* SGMII: Amplitude new setting gen2 Port3 */ 45 SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C 46 }, { 47 /* QSGMII: Amplitude and slew rate change */ 48 SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58 49 }, { 50 /* QSGMII: SELMUP and SELMUF */ 51 SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF 52 }, { 53 /* QSGMII: 0x72e18 */ 54 SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC 55 }, { 56 /* Null terminated */ 57 SERDES_UNIT_UNCONNECTED, 0, 0 58 } 59 }; 60 61 MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = { 62 /* Z1B */ 63 {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111, 64 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 65 0x0030, serdes_change_m_phy}, /* Default */ 66 {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111, 67 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 68 0x0030, serdes_change_m_phy}, /* PEX module */ 69 /* Z1A */ 70 {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000, 71 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, 72 PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */ 73 {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000, 74 {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 75 0x0030, serdes_change_m_phy} /* PEX module - Z1A */ 76 }; 77 78 MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = { 79 /* A0 */ 80 {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111, 81 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 82 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */ 83 {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111, 84 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 85 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */ 86 {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111, 87 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 88 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */ 89 {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111, 90 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 91 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */ 92 {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111, 93 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 94 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */ 95 {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111, 96 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 97 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */ 98 }; 99 100 MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = { 101 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 102 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 103 0x0030, serdes_change_m_phy}, /* Default */ 104 {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111, 105 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 106 0x00f4, serdes_change_m_phy}, /* Switch module */ 107 }; 108 109 MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = { 110 {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000, 111 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 112 0x0010, serdes_change_m_phy}, /* CPU0 */ 113 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 114 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 115 0x0010, serdes_change_m_phy} /* CPU1-3 */ 116 }; 117 118 MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = { 119 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 120 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 121 0x0010, serdes_change_m_phy}, /* CPU0 */ 122 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 123 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 124 0x0010, serdes_change_m_phy} /* CPU1-3 */ 125 }; 126 127 MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = { 128 {MV_PEX_END_POINT, 0x22321111, 0x00000000, 129 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 130 0x0010, serdes_change_m_phy} /* Default */ 131 }; 132 133 MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = { 134 {MV_PEX_END_POINT, 0x23321111, 0x00000000, 135 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 136 0x0010, serdes_change_m_phy} /* Default */ 137 }; 138 139 MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = { 140 {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000, 141 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 142 0x0000, serdes_change_m_phy} /* No PEX in FPGA */ 143 }; 144 145 MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = { 146 {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001, 147 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1}, 148 0x0030, serdes_change_m_phy} /* Default */ 149 }; 150 151 /* 152 * ARMADA-XP CUSTOMER BOARD 153 */ 154 MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = { 155 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 156 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 157 0x00000030, serdes_change_m_phy}, /* Default */ 158 {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111, 159 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 160 0x00000030, serdes_change_m_phy}, /* Switch module */ 161 }; 162 163 MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = { 164 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 165 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 166 0x0030, serdes_change_m_phy} /* Default */ 167 }; 168 169 MV_BIN_SERDES_CFG *serdes_info_tbl[] = { 170 db88f78xx0_serdes_cfg, 171 rd78460_serdes_cfg, 172 db78X60pcac_serdes_cfg, 173 fpga88f78xx0_serdes_cfg, 174 db88f78xx0rev2_serdes_cfg, 175 rd78460nas_serdes_cfg, 176 db78X60amc_serdes_cfg, 177 db78X60pcacrev2_serdes_cfg, 178 rd78460server_rev2_serdes_cfg, 179 rd78460AXP_GP_serdes_cfg, 180 rd78460customer_serdes_cfg 181 }; 182 183 u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E }; 184 u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F }; 185