1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <spl.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #include "high_speed_env_spec.h" 15 #include "board_env_spec.h" 16 17 #define SERDES_VERION "2.1.5" 18 #define ENDED_OK "High speed PHY - Ended Successfully\n" 19 20 static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG; 21 22 extern MV_BIN_SERDES_CFG *serdes_info_tbl[]; 23 24 extern u8 rd78460gp_twsi_dev[]; 25 extern u8 db88f78xx0rev2_twsi_dev[]; 26 27 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs); 28 int pex_local_bus_num_set(u32 pex_if, u32 bus_num); 29 int pex_local_dev_num_set(u32 pex_if, u32 dev_num); 30 31 #define MV_BOARD_PEX_MODULE_ADDR 0x23 32 #define MV_BOARD_PEX_MODULE_ID 1 33 #define MV_BOARD_ETM_MODULE_ID 2 34 35 #define PEX_MODULE_DETECT 1 36 #define ETM_MODULE_DETECT 2 37 38 #define PEX_MODE_GET(satr) ((satr & 0x6) >> 1) 39 #define PEX_CAPABILITY_GET(satr) (satr & 1) 40 #define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9) 41 42 /* Static parametes */ 43 static int config_module; 44 static int switch_module; 45 46 /* Local function */ 47 static u32 board_id_get(void) 48 { 49 #if defined(CONFIG_DB_88F78X60) 50 return DB_88F78XX0_BP_ID; 51 #elif defined(CONFIG_RD_88F78460_SERVER) 52 return RD_78460_SERVER_ID; 53 #elif defined(CONFIG_RD_78460_SERVER_REV2) 54 return RD_78460_SERVER_REV2_ID; 55 #elif defined(CONFIG_DB_78X60_PCAC) 56 return DB_78X60_PCAC_ID; 57 #elif defined(CONFIG_DB_88F78X60_REV2) 58 return DB_88F78XX0_BP_REV2_ID; 59 #elif defined(CONFIG_RD_78460_NAS) 60 return RD_78460_NAS_ID; 61 #elif defined(CONFIG_DB_78X60_AMC) 62 return DB_78X60_AMC_ID; 63 #elif defined(CONFIG_DB_78X60_PCAC_REV2) 64 return DB_78X60_PCAC_REV2_ID; 65 #elif defined(CONFIG_DB_784MP_GP) 66 return DB_784MP_GP_ID; 67 #elif defined(CONFIG_RD_78460_CUSTOMER) 68 return RD_78460_CUSTOMER_ID; 69 #else 70 /* 71 * Return 0 here for custom board as this should not be used 72 * for custom boards. 73 */ 74 return 0; 75 #endif 76 } 77 78 static u8 board_sat_r_get(u8 dev_num, u8 reg) 79 { 80 u8 data; 81 u8 *dev; 82 u32 board_id = board_id_get(); 83 int ret; 84 85 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 86 87 switch (board_id) { 88 case DB_784MP_GP_ID: 89 dev = rd78460gp_twsi_dev; 90 91 break; 92 case DB_88F78XX0_BP_ID: 93 case DB_88F78XX0_BP_REV2_ID: 94 dev = db88f78xx0rev2_twsi_dev; 95 break; 96 97 case DB_78X60_PCAC_ID: 98 case FPGA_88F78XX0_ID: 99 case DB_78X60_PCAC_REV2_ID: 100 case RD_78460_SERVER_REV2_ID: 101 default: 102 return 0; 103 } 104 105 /* Read MPP module ID */ 106 ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1); 107 if (ret) 108 return MV_ERROR; 109 110 return data; 111 } 112 113 static int board_modules_scan(void) 114 { 115 u8 val; 116 u32 board_id = board_id_get(); 117 int ret; 118 119 /* Perform scan only for DB board */ 120 if ((board_id == DB_88F78XX0_BP_ID) || 121 (board_id == DB_88F78XX0_BP_REV2_ID)) { 122 /* reset modules flags */ 123 config_module = 0; 124 125 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 126 127 /* SERDES module (only PEX model is supported now) */ 128 ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1); 129 if (ret) 130 return MV_ERROR; 131 132 if (val == MV_BOARD_PEX_MODULE_ID) 133 config_module = PEX_MODULE_DETECT; 134 if (val == MV_BOARD_ETM_MODULE_ID) 135 config_module = ETM_MODULE_DETECT; 136 } else if (board_id == RD_78460_NAS_ID) { 137 switch_module = 0; 138 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) 139 switch_module = 1; 140 } 141 142 return MV_OK; 143 } 144 145 u32 pex_max_unit_get(void) 146 { 147 /* 148 * TODO: 149 * Right now only MV78460 is supported. Other SoC's might need 150 * a different value here. 151 */ 152 return MV_PEX_MAX_UNIT; 153 } 154 155 u32 pex_max_if_get(void) 156 { 157 /* 158 * TODO: 159 * Right now only MV78460 is supported. Other SoC's might need 160 * a different value here. 161 */ 162 return MV_PEX_MAX_IF; 163 } 164 165 u8 board_cpu_freq_get(void) 166 { 167 u32 sar; 168 u32 sar_msb; 169 170 sar = reg_read(MPP_SAMPLE_AT_RESET(0)); 171 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1)); 172 return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21); 173 } 174 175 __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) 176 { 177 u32 board_id; 178 u32 serdes_cfg_val = 0; /* default */ 179 180 board_id = board_id_get(); 181 182 switch (board_id) { 183 case DB_784MP_GP_ID: 184 serdes_cfg_val = 0; 185 break; 186 } 187 188 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; 189 } 190 191 u16 ctrl_model_get(void) 192 { 193 /* 194 * SoC version can't be autodetected. So we need to rely on a define 195 * from the config system here. 196 */ 197 #ifdef CONFIG_MV78260 198 return MV_78260_DEV_ID; 199 #else 200 return MV_78460_DEV_ID; 201 #endif 202 } 203 204 u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) 205 { 206 if (line_num < 8) 207 return (info->line0_7 >> (line_num << 2)) & 0xF; 208 else 209 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; 210 } 211 212 static int serdes_max_lines_get(void) 213 { 214 switch (ctrl_model_get()) { 215 case MV_78260_DEV_ID: 216 return 12; 217 case MV_78460_DEV_ID: 218 return 16; 219 } 220 221 return 0; 222 } 223 224 int serdes_phy_config(void) 225 { 226 int status = MV_OK; 227 u32 line_cfg; 228 u8 line_num; 229 /* addr/value for each line @ every setup step */ 230 u32 addr[16][11], val[16][11]; 231 u8 pex_unit, pex_line_num; 232 u8 sgmii_port = 0; 233 u32 tmp; 234 u32 in_direct; 235 u8 max_serdes_lines; 236 MV_BIN_SERDES_CFG *info; 237 u8 satr11; 238 u8 sata_port; 239 u8 freq; 240 u8 device_rev; 241 u32 rx_high_imp_mode; 242 u16 ctrl_mode; 243 u32 board_id = board_id_get(); 244 u32 pex_if; 245 u32 pex_if_num; 246 247 /* 248 * Get max. serdes lines count 249 */ 250 max_serdes_lines = serdes_max_lines_get(); 251 if (max_serdes_lines == 0) 252 return MV_OK; 253 254 switch (board_id) { 255 case DB_78X60_AMC_ID: 256 case DB_78X60_PCAC_REV2_ID: 257 case RD_78460_CUSTOMER_ID: 258 case RD_78460_SERVER_ID: 259 case RD_78460_SERVER_REV2_ID: 260 case DB_78X60_PCAC_ID: 261 satr11 = (0x1 << 1) | 1; 262 break; 263 case FPGA_88F78XX0_ID: 264 case RD_78460_NAS_ID: 265 satr11 = (0x0 << 1) | 1; 266 break; 267 case DB_88F78XX0_BP_REV2_ID: 268 case DB_784MP_GP_ID: 269 case DB_88F78XX0_BP_ID: 270 satr11 = board_sat_r_get(1, 1); 271 if ((u8) MV_ERROR == (u8) satr11) 272 return MV_ERROR; 273 break; 274 default: 275 satr11 = 0; 276 } 277 278 board_modules_scan(); 279 memset(addr, 0, sizeof(addr)); 280 memset(val, 0, sizeof(val)); 281 282 /* Check if DRAM is already initialized */ 283 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & 284 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { 285 DEBUG_INIT_S("High speed PHY - Version: "); 286 DEBUG_INIT_S(SERDES_VERION); 287 DEBUG_INIT_S(" - 2nd boot - Skip\n"); 288 return MV_OK; 289 } 290 DEBUG_INIT_S("High speed PHY - Version: "); 291 DEBUG_INIT_S(SERDES_VERION); 292 DEBUG_INIT_S(" (COM-PHY-V20)\n"); 293 294 /* 295 * AVS : disable AVS for frequency less than 1333 296 */ 297 freq = board_cpu_freq_get(); 298 device_rev = mv_ctrl_rev_get(); 299 300 if (device_rev == 2) { /* for B0 only */ 301 u32 cpu_avs; 302 u8 fabric_freq; 303 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG); 304 DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs); 305 cpu_avs &= ~(1 << 9); 306 307 if ((0x4 == freq) || (0xB == freq)) { 308 u32 tmp2; 309 310 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); 311 DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2); 312 /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */ 313 tmp2 |= 0x0FF; 314 reg_write(CPU_AVS_CONTROL0_REG, tmp2); 315 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2); 316 cpu_avs |= (1 << 9); /* cpu avs enable */ 317 cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */ 318 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) & 319 SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET; 320 if ((0xB == freq) && (5 == fabric_freq)) { 321 u32 core_avs; 322 323 core_avs = reg_read(CORE_AVS_CONTROL_0REG); 324 DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs); 325 326 /* 327 * Set core lower limit = 0.9V & 328 * core upper limit = 0.9125V 329 */ 330 core_avs &= ~(0xff); 331 core_avs |= 0x0E; 332 reg_write(CORE_AVS_CONTROL_0REG, core_avs); 333 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs); 334 335 core_avs = reg_read(CORE_AVS_CONTROL_2REG); 336 DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs); 337 core_avs |= (1 << 9); /* core AVS enable */ 338 reg_write(CORE_AVS_CONTROL_2REG, core_avs); 339 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs); 340 341 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG); 342 DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG, 343 tmp2); 344 tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */ 345 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2); 346 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG, 347 tmp2); 348 } 349 } 350 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs); 351 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs); 352 } 353 354 info = board_serdes_cfg_get(PEX_MODE_GET(satr11)); 355 DEBUG_INIT_FULL_S("info->line0_7= 0x"); 356 DEBUG_INIT_FULL_D(info->line0_7, 8); 357 DEBUG_INIT_FULL_S(" info->line8_15= 0x"); 358 DEBUG_INIT_FULL_D(info->line8_15, 8); 359 DEBUG_INIT_FULL_S("\n"); 360 361 if (info == NULL) { 362 DEBUG_INIT_S("Hight speed PHY Error #1\n"); 363 return MV_ERROR; 364 } 365 366 if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */ 367 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n"); 368 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111); 369 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111); 370 info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */ 371 mdelay(100); 372 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */ 373 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */ 374 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */ 375 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */ 376 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */ 377 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */ 378 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */ 379 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */ 380 reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */ 381 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */ 382 reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */ 383 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */ 384 reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */ 385 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */ 386 reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */ 387 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */ 388 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */ 389 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */ 390 reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */ 391 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */ 392 } 393 394 /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */ 395 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n"); 396 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) { 397 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 398 continue; 399 400 /* 1. GLOB_CLK_CTRL Reset and Clock Control */ 401 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25); 402 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25); 403 404 /* 2. GLOB_TEST_CTRL Test Mode Control */ 405 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) { 406 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 407 (0xC2 << 16) | 0x200); 408 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 409 (0xC2 << 16) | 0x200); 410 } 411 412 /* 3. GLOB_CLK_SRC_LO Clock Source Low */ 413 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) { 414 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 415 (0xC3 << 16) | 0x0F); 416 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 417 (0xC3 << 16) | 0x0F); 418 } 419 420 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F); 421 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 422 (0xC5 << 16) | 0x11F); 423 } 424 425 /* 426 * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL, 427 * PU_RX,PU_TX. (bits[12:5]) 428 */ 429 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n"); 430 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 431 line_cfg = get_line_cfg(line_num, info); 432 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) 433 continue; 434 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) 435 continue; 436 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) { 437 switch (line_num) { 438 case 4: 439 case 6: 440 sata_port = 0; 441 break; 442 case 5: 443 sata_port = 1; 444 break; 445 default: 446 DEBUG_INIT_C 447 ("SATA port error for serdes line: ", 448 line_num, 2); 449 return MV_ERROR; 450 } 451 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port)); 452 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 453 tmp &= ~((0x1ff << 5) | 0x7); 454 tmp |= ((info->bus_speed & (1 << line_num)) != 0) ? 455 (0x11 << 5) : 0x0; 456 457 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 458 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 459 } 460 461 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) { 462 /* 463 * 4) Configure the desire PIN_PHY_GEN and do power 464 * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5]) 465 */ 466 tmp = reg_read(SGMII_SERDES_CFG_REG(0)); 467 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp); 468 tmp &= ~((0x1ff << 5) | 0x7); 469 tmp |= 0x660; 470 reg_write(SGMII_SERDES_CFG_REG(0), tmp); 471 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp); 472 continue; 473 } 474 475 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0]) 476 sgmii_port = 0; 477 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1]) 478 sgmii_port = 1; 479 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2]) 480 sgmii_port = 2; 481 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3]) 482 sgmii_port = 3; 483 else 484 continue; 485 486 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port)); 487 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 488 tmp &= ~((0x1ff << 5) | 0x7); 489 tmp |= (((info->bus_speed & (1 << line_num)) != 0) ? 490 (0x88 << 5) : (0x66 << 5)); 491 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 492 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 493 } 494 495 /* Step 3 - QSGMII enable */ 496 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n"); 497 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 498 line_cfg = get_line_cfg(line_num, info); 499 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) { 500 /* QSGMII Active bit set to true */ 501 tmp = reg_read(QSGMII_CONTROL_1_REG); 502 DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp); 503 tmp |= (1 << 30); 504 #ifdef ERRATA_GL_6572255 505 tmp |= (1 << 27); 506 #endif 507 reg_write(QSGMII_CONTROL_1_REG, tmp); 508 DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp); 509 } 510 } 511 512 /* Step 4 - configure SERDES MUXes */ 513 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n"); 514 if (config_module & ETM_MODULE_DETECT) { 515 reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111); 516 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111); 517 } else { 518 reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7); 519 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7); 520 } 521 reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15); 522 DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15); 523 524 /* Step 5: Activate the RX High Impedance Mode */ 525 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n"); 526 rx_high_imp_mode = 0x8080; 527 if (device_rev == 2) /* for B0 only */ 528 rx_high_imp_mode |= 4; 529 530 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 531 /* for each serdes lane */ 532 DEBUG_INIT_FULL_S("SERDES "); 533 DEBUG_INIT_FULL_D_10(line_num, 2); 534 line_cfg = get_line_cfg(line_num, info); 535 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) { 536 DEBUG_INIT_FULL_S(" unconnected ***\n"); 537 continue; 538 } 539 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) { 540 pex_unit = line_num >> 2; 541 pex_line_num = line_num % 4; 542 DEBUG_INIT_FULL_S(" - PEX unit "); 543 DEBUG_INIT_FULL_D_10(pex_unit, 1); 544 DEBUG_INIT_FULL_S(" line= "); 545 DEBUG_INIT_FULL_D_10(pex_line_num, 1); 546 DEBUG_INIT_FULL_S("\n"); 547 548 /* Needed for PEX_PHY_ACCESS_REG macro */ 549 if ((line_num > 7) && 550 (info->pex_mode[3] == PEX_BUS_MODE_X8)) 551 /* lines 8 - 15 are belong to PEX3 in x8 mode */ 552 pex_unit = 3; 553 554 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 555 continue; 556 557 /* 558 * 8) Activate the RX High Impedance Mode field 559 * (bit [2]) in register /PCIe_USB Control (Each MAC 560 * contain different Access to reach its 561 * Serdes-Regfile). 562 * [PEX-Only] Set bit[12]: The analog part latches idle 563 * if PU_TX = 1 and PU_PLL =1. 564 */ 565 566 /* Termination enable */ 567 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) { 568 in_direct = (0x48 << 16) | (pex_line_num << 24) | 569 0x1000 | rx_high_imp_mode; /* x1 */ 570 } else if ((info->pex_mode[pex_unit] == 571 PEX_BUS_MODE_X4) && (pex_line_num == 0)) 572 in_direct = (0x48 << 16) | (pex_line_num << 24) | 573 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */ 574 else 575 in_direct = 0; 576 577 if (in_direct) { 578 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 579 in_direct); 580 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 581 in_direct); 582 } 583 584 continue; 585 } 586 587 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) { 588 /* 589 * port 0 for serdes lines 4,6, and port 1 for 590 * serdes lines 5 591 */ 592 sata_port = line_num & 1; 593 DEBUG_INIT_FULL_S(" - SATA port "); 594 DEBUG_INIT_FULL_D_10(sata_port, 2); 595 DEBUG_INIT_FULL_S("\n"); 596 reg_write(SATA_COMPHY_CTRL_REG(sata_port), 597 rx_high_imp_mode); 598 DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port), 599 rx_high_imp_mode); 600 continue; 601 } 602 603 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) { 604 DEBUG_INIT_FULL_S(" - QSGMII\n"); 605 reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode); 606 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0), 607 rx_high_imp_mode); 608 continue; 609 } 610 611 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0]) 612 sgmii_port = 0; 613 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1]) 614 sgmii_port = 1; 615 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2]) 616 sgmii_port = 2; 617 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3]) 618 sgmii_port = 3; 619 else 620 continue; 621 DEBUG_INIT_FULL_S(" - SGMII port "); 622 DEBUG_INIT_FULL_D_10(sgmii_port, 2); 623 DEBUG_INIT_FULL_S("\n"); 624 reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode); 625 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port), 626 rx_high_imp_mode); 627 } /* for each serdes lane */ 628 629 /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */ 630 DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n"); 631 tmp = reg_read(SOC_CTRL_REG); 632 DEBUG_RD_REG(SOC_CTRL_REG, tmp); 633 tmp &= 0x200; 634 if (info->pex_mode[0] == PEX_BUS_MODE_X1) 635 tmp |= PCIE0_QUADX1_EN; 636 if (info->pex_mode[1] == PEX_BUS_MODE_X1) 637 tmp |= PCIE1_QUADX1_EN; 638 if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >> 639 PEX_CLK_100MHZ_OFFSET) == 0x1) 640 tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK); 641 642 reg_write(SOC_CTRL_REG, tmp); 643 DEBUG_WR_REG(SOC_CTRL_REG, tmp); 644 645 /* 6.2 PCI Express Link Capabilities */ 646 DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n"); 647 648 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 649 line_cfg = get_line_cfg(line_num, info); 650 651 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) { 652 /* 653 * PCI Express Control 654 * 0xX1A00 [0]: 655 * 0x0 X4-Link. 656 * 0x1 X1-Link 657 */ 658 pex_unit = line_num >> 2; 659 pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num); 660 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 661 continue; 662 663 /* set Common Clock Configuration */ 664 tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if)); 665 DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); 666 tmp |= (1 << 6); 667 reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); 668 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); 669 670 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if)); 671 DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp); 672 tmp &= ~(0x3FF); 673 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) 674 tmp |= (0x1 << 4); 675 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) 676 tmp |= (0x4 << 4); 677 if (0 == PEX_CAPABILITY_GET(satr11)) 678 tmp |= 0x1; 679 else 680 tmp |= 0x2; 681 DEBUG_INIT_FULL_S("Step 6.2: PEX "); 682 DEBUG_INIT_FULL_D(pex_if, 1); 683 DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1); 684 reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp); 685 DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp); 686 687 /* 688 * If pex is X4, no need to pass thru the other 689 * 3X1 serdes lines 690 */ 691 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) 692 line_num += 3; 693 } 694 } 695 696 /* 697 * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you 698 * need to config the register SOC_Misc/General Purpose2 699 * (Address= 182F8) 700 */ 701 DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n"); 702 tmp = reg_read(GEN_PURP_RES_2_REG); 703 DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp); 704 705 tmp &= 0xFFFF0000; 706 if (info->pex_mode[0] == PEX_BUS_MODE_X4) 707 tmp |= 0x0000000F; 708 709 if (info->pex_mode[1] == PEX_BUS_MODE_X4) 710 tmp |= 0x000000F0; 711 712 if (info->pex_mode[2] == PEX_BUS_MODE_X4) 713 tmp |= 0x00000F00; 714 715 if (info->pex_mode[3] == PEX_BUS_MODE_X4) 716 tmp |= 0x0000F000; 717 718 reg_write(GEN_PURP_RES_2_REG, tmp); 719 DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp); 720 721 /* Steps 8 , 9 ,10 - use prepared REG addresses and values */ 722 DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n"); 723 724 /* Prepare PHY parameters for each step according to MUX selection */ 725 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 726 /* for each serdes lane */ 727 728 line_cfg = get_line_cfg(line_num, info); 729 730 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) 731 continue; 732 733 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) { 734 pex_unit = line_num >> 2; 735 pex_line_num = line_num % 4; 736 737 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 738 continue; 739 /* 740 * 8) Configure the desire PHY_MODE (bits [7:5]) 741 * and REF_FREF_SEL (bits[4:0]) in the register Power 742 * and PLL Control (Each MAC contain different Access 743 * to reach its Serdes-Regfile). 744 */ 745 if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) && 746 (0 == pex_line_num)) 747 || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) { 748 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 749 (0x01 << 16) | (pex_line_num << 24) | 750 0xFC60); 751 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 752 (0x01 << 16) | (pex_line_num << 24) 753 | 0xFC60); 754 /* 755 * Step 8.1: [PEX-Only] Configure Max PLL Rate 756 * (bit 8 in KVCO Calibration Control and 757 * bits[10:9] in 758 */ 759 /* Use Maximum PLL Rate(Bit 8) */ 760 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 761 (0x02 << 16) | (1 << 31) | 762 (pex_line_num << 24)); /* read command */ 763 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 764 (0x02 << 16) | (1 << 31) | 765 (pex_line_num << 24)); 766 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); 767 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); 768 tmp &= ~(1 << 31); 769 tmp |= (1 << 8); 770 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); 771 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); 772 773 /* Use Maximum PLL Rate(Bits [10:9]) */ 774 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 775 (0x81 << 16) | (1 << 31) | 776 (pex_line_num << 24)); /* read command */ 777 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 778 (0x81 << 16) | (1 << 31) | 779 (pex_line_num << 24)); 780 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); 781 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); 782 tmp &= ~(1 << 31); 783 tmp |= (3 << 9); 784 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); 785 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); 786 } 787 788 continue; 789 } 790 791 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) { 792 /* 793 * Port 0 for serdes lines 4,6, and port 1 for serdes 794 * lines 5 795 */ 796 sata_port = line_num & 1; 797 798 /* 799 * 8) Configure the desire PHY_MODE (bits [7:5]) and 800 * REF_FREF_SEL (bits[4:0]) in the register Power 801 * and PLL Control (Each MAC contain different Access 802 * to reach its Serdes-Regfile). 803 */ 804 reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801); 805 DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801); 806 807 /* 9) Configure the desire SEL_BITS */ 808 reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400); 809 DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400); 810 811 /* 10) Configure the desire REFCLK_SEL */ 812 813 reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400); 814 DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400); 815 816 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */ 817 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port)); 818 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 819 tmp |= 7; 820 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 821 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp); 822 823 continue; 824 } 825 826 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) { 827 /* 828 * 8) Configure the desire PHY_MODE (bits [7:5]) 829 * and REF_FREF_SEL (bits[4:0]) in the register 830 */ 831 reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881); 832 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881); 833 834 /* 835 * 9) Configure the desire SEL_BITS (bits [11:0] 836 * in register 837 */ 838 reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400); 839 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400); 840 841 /* 842 * 10) Configure the desire REFCLK_SEL (bit [10]) 843 * in register 844 */ 845 reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400); 846 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400); 847 848 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */ 849 tmp = reg_read(SGMII_SERDES_CFG_REG(0)); 850 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp); 851 tmp |= 7; 852 reg_write(SGMII_SERDES_CFG_REG(0), tmp); 853 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp); 854 continue; 855 } 856 857 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0]) 858 sgmii_port = 0; 859 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1]) 860 sgmii_port = 1; 861 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2]) 862 sgmii_port = 2; 863 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3]) 864 sgmii_port = 3; 865 else 866 continue; 867 868 /* 869 * 8) Configure the desire PHY_MODE (bits [7:5]) and 870 * REF_FREF_SEL (bits[4:0]) in the register 871 */ 872 reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881); 873 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881); 874 875 /* 9) Configure the desire SEL_BITS (bits [11:0] in register */ 876 reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0); 877 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0); 878 879 /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */ 880 reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400); 881 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400); 882 883 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */ 884 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port)); 885 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 886 tmp |= 7; 887 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 888 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp); 889 890 } /* for each serdes lane */ 891 892 /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */ 893 DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n"); 894 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 895 /* for each serdes lane */ 896 897 line_cfg = get_line_cfg(line_num, info); 898 899 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) 900 continue; 901 902 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) { 903 pex_unit = line_num >> 2; 904 pex_line_num = line_num % 4; 905 if (0 == pex_line_num) { 906 reg_write(PEX_PHY_ACCESS_REG(pex_unit), 907 (0xC1 << 16) | 0x24); 908 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), 909 (0xC1 << 16) | 0x24); 910 } 911 } 912 } 913 914 /*--------------------------------------------------------------*/ 915 /* Step 13: Wait 15ms before checking results */ 916 DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results"); 917 mdelay(15); 918 tmp = 20; 919 while (tmp) { 920 status = MV_OK; 921 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 922 u32 tmp; 923 line_cfg = get_line_cfg(line_num, info); 924 if (line_cfg == 925 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) 926 continue; 927 928 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) 929 continue; 930 931 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) { 932 /* 933 * Port 0 for serdes lines 4,6, and port 1 934 * for serdes lines 5 935 */ 936 sata_port = line_num & 1; 937 938 tmp = 939 reg_read(SATA_LP_PHY_EXT_STAT_REG 940 (sata_port)); 941 DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG 942 (sata_port), tmp); 943 if ((tmp & 0x7) != 0x7) 944 status = MV_ERROR; 945 continue; 946 } 947 948 if (line_cfg == 949 serdes_cfg[line_num][SERDES_UNIT_QSGMII]) { 950 tmp = reg_read(SGMII_SERDES_STAT_REG(0)); 951 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp); 952 if ((tmp & 0x7) != 0x7) 953 status = MV_ERROR; 954 continue; 955 } 956 957 if (line_cfg == 958 serdes_cfg[line_num][SERDES_UNIT_SGMII0]) 959 sgmii_port = 0; 960 else if (line_cfg == 961 serdes_cfg[line_num][SERDES_UNIT_SGMII1]) 962 sgmii_port = 1; 963 else if (line_cfg == 964 serdes_cfg[line_num][SERDES_UNIT_SGMII2]) 965 sgmii_port = 2; 966 else if (line_cfg == 967 serdes_cfg[line_num][SERDES_UNIT_SGMII3]) 968 sgmii_port = 3; 969 else 970 continue; 971 972 tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port)); 973 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp); 974 if ((tmp & 0x7) != 0x7) 975 status = MV_ERROR; 976 } 977 978 if (status == MV_OK) 979 break; 980 mdelay(5); 981 tmp--; 982 } 983 984 /* 985 * Step14 [PEX-Only] In order to configure RC/EP mode please write 986 * to register 0x0060 bits 987 */ 988 DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n"); 989 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) { 990 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 991 continue; 992 tmp = 993 reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit))); 994 DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)), 995 tmp); 996 tmp &= ~(0xf << 20); 997 if (info->pex_type == MV_PEX_ROOT_COMPLEX) 998 tmp |= (0x4 << 20); 999 else 1000 tmp |= (0x1 << 20); 1001 reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)), 1002 tmp); 1003 DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)), 1004 tmp); 1005 } 1006 1007 /* 1008 * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of 1009 * register 0x1a60 1010 */ 1011 DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n"); 1012 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) { 1013 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) 1014 continue; 1015 if (info->pex_type == MV_PEX_END_POINT) { 1016 tmp = 1017 reg_read(PEX_DBG_CTRL_REG 1018 (MV_PEX_UNIT_TO_IF(pex_unit))); 1019 DEBUG_RD_REG(PEX_DBG_CTRL_REG 1020 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp); 1021 tmp &= 0xfff6ffff; 1022 reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)), 1023 tmp); 1024 DEBUG_WR_REG(PEX_DBG_CTRL_REG 1025 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp); 1026 } 1027 } 1028 1029 if (info->serdes_m_phy_change) { 1030 MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change; 1031 u32 bus_speed; 1032 for (line_num = 0; line_num < max_serdes_lines; line_num++) { 1033 line_cfg = get_line_cfg(line_num, info); 1034 if (line_cfg == 1035 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) 1036 continue; 1037 serdes_m_phy_change = info->serdes_m_phy_change; 1038 bus_speed = info->bus_speed & (1 << line_num); 1039 while (serdes_m_phy_change->type != 1040 SERDES_UNIT_UNCONNECTED) { 1041 switch (serdes_m_phy_change->type) { 1042 case SERDES_UNIT_PEX: 1043 if (line_cfg != SERDES_UNIT_PEX) 1044 break; 1045 pex_unit = line_num >> 2; 1046 pex_line_num = line_num % 4; 1047 if (info->pex_mode[pex_unit] == 1048 PEX_BUS_DISABLED) 1049 break; 1050 if ((info->pex_mode[pex_unit] == 1051 PEX_BUS_MODE_X4) && pex_line_num) 1052 break; 1053 1054 if (bus_speed) { 1055 reg_write(PEX_PHY_ACCESS_REG 1056 (pex_unit), 1057 (pex_line_num << 24) | 1058 serdes_m_phy_change->val_hi_speed); 1059 DEBUG_WR_REG(PEX_PHY_ACCESS_REG 1060 (pex_unit), 1061 (pex_line_num << 1062 24) | 1063 serdes_m_phy_change->val_hi_speed); 1064 } else { 1065 reg_write(PEX_PHY_ACCESS_REG 1066 (pex_unit), 1067 (pex_line_num << 24) | 1068 serdes_m_phy_change->val_low_speed); 1069 DEBUG_WR_REG(PEX_PHY_ACCESS_REG 1070 (pex_unit), 1071 (pex_line_num << 1072 24) | 1073 serdes_m_phy_change->val_low_speed); 1074 } 1075 break; 1076 case SERDES_UNIT_SATA: 1077 if (line_cfg != SERDES_UNIT_SATA) 1078 break; 1079 /* 1080 * Port 0 for serdes lines 4,6, and 1081 * port 1 for serdes lines 5 1082 */ 1083 sata_port = line_num & 1; 1084 if (bus_speed) { 1085 reg_write(SATA_BASE_REG 1086 (sata_port) | 1087 serdes_m_phy_change->reg_hi_speed, 1088 serdes_m_phy_change->val_hi_speed); 1089 DEBUG_WR_REG(SATA_BASE_REG 1090 (sata_port) | 1091 serdes_m_phy_change->reg_hi_speed, 1092 serdes_m_phy_change->val_hi_speed); 1093 } else { 1094 reg_write(SATA_BASE_REG 1095 (sata_port) | 1096 serdes_m_phy_change->reg_low_speed, 1097 serdes_m_phy_change->val_low_speed); 1098 DEBUG_WR_REG(SATA_BASE_REG 1099 (sata_port) | 1100 serdes_m_phy_change->reg_low_speed, 1101 serdes_m_phy_change->val_low_speed); 1102 } 1103 break; 1104 case SERDES_UNIT_SGMII0: 1105 case SERDES_UNIT_SGMII1: 1106 case SERDES_UNIT_SGMII2: 1107 case SERDES_UNIT_SGMII3: 1108 if (line_cfg == serdes_cfg[line_num] 1109 [SERDES_UNIT_SGMII0]) 1110 sgmii_port = 0; 1111 else if (line_cfg == 1112 serdes_cfg[line_num] 1113 [SERDES_UNIT_SGMII1]) 1114 sgmii_port = 1; 1115 else if (line_cfg == 1116 serdes_cfg[line_num] 1117 [SERDES_UNIT_SGMII2]) 1118 sgmii_port = 2; 1119 else if (line_cfg == 1120 serdes_cfg[line_num] 1121 [SERDES_UNIT_SGMII3]) 1122 sgmii_port = 3; 1123 else 1124 break; 1125 if (bus_speed) { 1126 reg_write(MV_ETH_REGS_BASE 1127 (sgmii_port) | 1128 serdes_m_phy_change->reg_hi_speed, 1129 serdes_m_phy_change->val_hi_speed); 1130 DEBUG_WR_REG(MV_ETH_REGS_BASE 1131 (sgmii_port) | 1132 serdes_m_phy_change->reg_hi_speed, 1133 serdes_m_phy_change->val_hi_speed); 1134 } else { 1135 reg_write(MV_ETH_REGS_BASE 1136 (sgmii_port) | 1137 serdes_m_phy_change->reg_low_speed, 1138 serdes_m_phy_change->val_low_speed); 1139 DEBUG_WR_REG(MV_ETH_REGS_BASE 1140 (sgmii_port) | 1141 serdes_m_phy_change->reg_low_speed, 1142 serdes_m_phy_change->val_low_speed); 1143 } 1144 break; 1145 case SERDES_UNIT_QSGMII: 1146 if (line_cfg != SERDES_UNIT_QSGMII) 1147 break; 1148 if (bus_speed) { 1149 reg_write 1150 (serdes_m_phy_change->reg_hi_speed, 1151 serdes_m_phy_change->val_hi_speed); 1152 DEBUG_WR_REG 1153 (serdes_m_phy_change->reg_hi_speed, 1154 serdes_m_phy_change->val_hi_speed); 1155 } else { 1156 reg_write 1157 (serdes_m_phy_change->reg_low_speed, 1158 serdes_m_phy_change->val_low_speed); 1159 DEBUG_WR_REG 1160 (serdes_m_phy_change->reg_low_speed, 1161 serdes_m_phy_change->val_low_speed); 1162 } 1163 break; 1164 default: 1165 break; 1166 } 1167 serdes_m_phy_change++; 1168 } 1169 } 1170 } 1171 1172 /* Step 16 [PEX-Only] Training Enable */ 1173 DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable"); 1174 tmp = reg_read(SOC_CTRL_REG); 1175 DEBUG_RD_REG(SOC_CTRL_REG, tmp); 1176 tmp &= ~(0x0F); 1177 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) { 1178 reg_write(PEX_CAUSE_REG(pex_unit), 0); 1179 DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0); 1180 if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED) 1181 tmp |= (0x1 << pex_unit); 1182 } 1183 reg_write(SOC_CTRL_REG, tmp); 1184 DEBUG_WR_REG(SOC_CTRL_REG, tmp); 1185 1186 /* Step 17: Speed change to target speed and width */ 1187 { 1188 u32 tmp_reg, tmp_pex_reg; 1189 u32 addr; 1190 u32 first_busno, next_busno; 1191 u32 max_link_width = 0; 1192 u32 neg_link_width = 0; 1193 pex_if_num = pex_max_if_get(); 1194 mdelay(150); 1195 DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1); 1196 next_busno = 0; 1197 for (pex_if = 0; pex_if < pex_if_num; pex_if++) { 1198 line_num = (pex_if <= 8) ? pex_if : 12; 1199 line_cfg = get_line_cfg(line_num, info); 1200 if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX]) 1201 continue; 1202 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3; 1203 DEBUG_INIT_FULL_S("step 17: PEX"); 1204 DEBUG_INIT_FULL_D(pex_if, 1); 1205 DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1); 1206 1207 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) { 1208 DEBUG_INIT_FULL_C("PEX disabled interface ", 1209 pex_if, 1); 1210 if (pex_if < 8) 1211 pex_if += 3; 1212 continue; 1213 } 1214 first_busno = next_busno; 1215 if ((info->pex_type == MV_PEX_END_POINT) && 1216 (0 == pex_if)) { 1217 if ((pex_if < 8) && (info->pex_mode[pex_unit] == 1218 PEX_BUS_MODE_X4)) 1219 pex_if += 3; 1220 continue; 1221 } 1222 1223 tmp = reg_read(PEX_DBG_STATUS_REG(pex_if)); 1224 DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp); 1225 if ((tmp & 0x7f) == 0x7e) { 1226 next_busno++; 1227 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if)); 1228 max_link_width = tmp; 1229 DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG 1230 (pex_if)), tmp); 1231 max_link_width = ((max_link_width >> 4) & 0x3F); 1232 neg_link_width = 1233 reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if)); 1234 DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)), 1235 neg_link_width); 1236 neg_link_width = ((neg_link_width >> 20) & 0x3F); 1237 if (max_link_width > neg_link_width) { 1238 tmp &= ~(0x3F << 4); 1239 tmp |= (neg_link_width << 4); 1240 reg_write(PEX_LINK_CAPABILITIES_REG 1241 (pex_if), tmp); 1242 DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG 1243 (pex_if)), tmp); 1244 mdelay(1); /* wait 1ms before reading capability for speed */ 1245 DEBUG_INIT_S("PEX"); 1246 DEBUG_INIT_D(pex_if, 1); 1247 DEBUG_INIT_C(": change width to X", 1248 neg_link_width, 1); 1249 } 1250 tmp_pex_reg = 1251 reg_read((PEX_CFG_DIRECT_ACCESS 1252 (pex_if, 1253 PEX_LINK_CAPABILITY_REG))); 1254 DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS 1255 (pex_if, 1256 PEX_LINK_CAPABILITY_REG)), 1257 tmp_pex_reg); 1258 tmp_pex_reg &= (0xF); 1259 if (tmp_pex_reg == 0x2) { 1260 tmp_reg = 1261 (reg_read 1262 (PEX_CFG_DIRECT_ACCESS 1263 (pex_if, 1264 PEX_LINK_CTRL_STAT_REG)) & 1265 0xF0000) >> 16; 1266 DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS 1267 (pex_if, 1268 PEX_LINK_CTRL_STAT_REG), 1269 tmp_pex_reg); 1270 /* check if the link established is GEN1 */ 1271 if (tmp_reg == 0x1) { 1272 pex_local_bus_num_set(pex_if, 1273 first_busno); 1274 pex_local_dev_num_set(pex_if, 1275 1); 1276 1277 DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n"); 1278 /* link is Gen1, check the EP capability */ 1279 addr = 1280 pex_cfg_read(pex_if, 1281 first_busno, 0, 1282 0, 1283 0x34) & 0xFF; 1284 DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x", 1285 addr, 4); 1286 if (addr == 0xff) { 1287 DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.", 1288 pex_if, 1); 1289 continue; 1290 } 1291 while ((pex_cfg_read 1292 (pex_if, first_busno, 0, 1293 0, 1294 addr) & 0xFF) != 1295 0x10) { 1296 addr = 1297 (pex_cfg_read 1298 (pex_if, 1299 first_busno, 0, 0, 1300 addr) & 0xFF00) >> 1301 8; 1302 } 1303 if ((pex_cfg_read 1304 (pex_if, first_busno, 0, 0, 1305 addr + 0xC) & 0xF) >= 1306 0x2) { 1307 tmp = 1308 reg_read 1309 (PEX_LINK_CTRL_STATUS2_REG 1310 (pex_if)); 1311 DEBUG_RD_REG 1312 (PEX_LINK_CTRL_STATUS2_REG 1313 (pex_if), tmp); 1314 tmp &= ~(0x1 | 1 << 1); 1315 tmp |= (1 << 1); 1316 reg_write 1317 (PEX_LINK_CTRL_STATUS2_REG 1318 (pex_if), tmp); 1319 DEBUG_WR_REG 1320 (PEX_LINK_CTRL_STATUS2_REG 1321 (pex_if), tmp); 1322 1323 tmp = 1324 reg_read 1325 (PEX_CTRL_REG 1326 (pex_if)); 1327 DEBUG_RD_REG 1328 (PEX_CTRL_REG 1329 (pex_if), tmp); 1330 tmp |= (1 << 10); 1331 reg_write(PEX_CTRL_REG 1332 (pex_if), 1333 tmp); 1334 DEBUG_WR_REG 1335 (PEX_CTRL_REG 1336 (pex_if), tmp); 1337 mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */ 1338 DEBUG_INIT_FULL_S 1339 ("Gen2 client!\n"); 1340 } else { 1341 DEBUG_INIT_FULL_S 1342 ("GEN1 client!\n"); 1343 } 1344 } 1345 } 1346 } else { 1347 DEBUG_INIT_FULL_S("PEX"); 1348 DEBUG_INIT_FULL_D(pex_if, 1); 1349 DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x"); 1350 DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if), 1351 8); 1352 DEBUG_INIT_FULL_C(") = 0x", tmp, 8); 1353 } 1354 1355 if ((pex_if < 8) && 1356 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) 1357 pex_if += 3; 1358 } 1359 } 1360 1361 /* Step 18: update pex DEVICE ID */ 1362 { 1363 u32 devId; 1364 pex_if_num = pex_max_if_get(); 1365 ctrl_mode = ctrl_model_get(); 1366 for (pex_if = 0; pex_if < pex_if_num; pex_if++) { 1367 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3; 1368 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) { 1369 if ((pex_if < 8) && 1370 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) 1371 pex_if += 3; 1372 continue; 1373 } 1374 1375 devId = reg_read(PEX_CFG_DIRECT_ACCESS( 1376 pex_if, PEX_DEVICE_AND_VENDOR_ID)); 1377 devId &= 0xFFFF; 1378 devId |= ((ctrl_mode << 16) & 0xffff0000); 1379 DEBUG_INIT_FULL_S("Update Device ID PEX"); 1380 DEBUG_INIT_FULL_D(pex_if, 1); 1381 DEBUG_INIT_FULL_D(devId, 8); 1382 DEBUG_INIT_FULL_S("\n"); 1383 reg_write(PEX_CFG_DIRECT_ACCESS 1384 (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId); 1385 if ((pex_if < 8) && 1386 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) 1387 pex_if += 3; 1388 } 1389 DEBUG_INIT_FULL_S("Update PEX Device ID 0x"); 1390 DEBUG_INIT_FULL_D(ctrl_mode, 4); 1391 DEBUG_INIT_FULL_S("0\n"); 1392 } 1393 tmp = reg_read(PEX_DBG_STATUS_REG(0)); 1394 DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp); 1395 1396 DEBUG_INIT_S(ENDED_OK); 1397 return MV_OK; 1398 } 1399 1400 /* PEX configuration space read write */ 1401 1402 /* 1403 * pex_cfg_read - Read from configuration space 1404 * 1405 * DESCRIPTION: 1406 * This function performs a 32 bit read from PEX configuration space. 1407 * It supports both type 0 and type 1 of Configuration Transactions 1408 * (local and over bridge). In order to read from local bus segment, use 1409 * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers 1410 * will result configuration transaction of type 1 (over bridge). 1411 * 1412 * INPUT: 1413 * pex_if - PEX interface number. 1414 * bus - PEX segment bus number. 1415 * dev - PEX device number. 1416 * func - Function number. 1417 * offss - Register offset. 1418 * 1419 * OUTPUT: 1420 * None. 1421 * 1422 * RETURN: 1423 * 32bit register data, 0xffffffff on error 1424 * 1425 */ 1426 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs) 1427 { 1428 u32 pex_data = 0; 1429 u32 local_dev, local_bus; 1430 u32 val; 1431 1432 if (pex_if >= MV_PEX_MAX_IF) 1433 return 0xFFFFFFFF; 1434 1435 if (dev >= MAX_PEX_DEVICES) { 1436 DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev, 1437 1); 1438 return 0xFFFFFFFF; 1439 } 1440 1441 if (func >= MAX_PEX_FUNCS) { 1442 DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func, 1443 1); 1444 return 0xFFFFFFFF; 1445 } 1446 1447 if (bus >= MAX_PEX_BUSSES) { 1448 DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1); 1449 return MV_ERROR; 1450 } 1451 val = reg_read(PEX_STATUS_REG(pex_if)); 1452 1453 local_dev = 1454 ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS); 1455 local_bus = 1456 ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS); 1457 1458 /* Speed up the process. In case on no link, return MV_ERROR */ 1459 if ((dev != local_dev) || (bus != local_bus)) { 1460 pex_data = reg_read(PEX_STATUS_REG(pex_if)); 1461 1462 if ((pex_data & PXSR_DL_DOWN)) 1463 return MV_ERROR; 1464 } 1465 1466 /* 1467 * In PCI Express we have only one device number 1468 * and this number is the first number we encounter else that the 1469 * local_dev spec pex define return on config read/write on any device 1470 */ 1471 if (bus == local_bus) { 1472 if (local_dev == 0) { 1473 /* 1474 * If local dev is 0 then the first number we encounter 1475 * after 0 is 1 1476 */ 1477 if ((dev != 1) && (dev != local_dev)) 1478 return MV_ERROR; 1479 } else { 1480 /* 1481 * If local dev is not 0 then the first number we 1482 * encounter is 0 1483 */ 1484 if ((dev != 0) && (dev != local_dev)) 1485 return MV_ERROR; 1486 } 1487 } 1488 1489 /* Creating PEX address to be passed */ 1490 pex_data = (bus << PXCAR_BUS_NUM_OFFS); 1491 pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS); 1492 pex_data |= (func << PXCAR_FUNC_NUM_OFFS); 1493 pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */ 1494 /* extended register space */ 1495 pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >> 1496 PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); 1497 1498 pex_data |= PXCAR_CONFIG_EN; 1499 1500 /* Write the address to the PEX configuration address register */ 1501 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); 1502 1503 /* 1504 * In order to let the PEX controller absorbed the address of the read 1505 * transaction we perform a validity check that the address was written 1506 */ 1507 if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if))) 1508 return MV_ERROR; 1509 1510 /* cleaning Master Abort */ 1511 reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND), 1512 PXSAC_MABORT); 1513 /* Read the Data returned in the PEX Data register */ 1514 pex_data = reg_read(PEX_CFG_DATA_REG(pex_if)); 1515 1516 DEBUG_INIT_FULL_C(" --> ", pex_data, 4); 1517 1518 return pex_data; 1519 } 1520 1521 /* 1522 * pex_local_bus_num_set - Set PEX interface local bus number. 1523 * 1524 * DESCRIPTION: 1525 * This function sets given PEX interface its local bus number. 1526 * Note: In case the PEX interface is PEX-X, the information is read-only. 1527 * 1528 * INPUT: 1529 * pex_if - PEX interface number. 1530 * bus_num - Bus number. 1531 * 1532 * OUTPUT: 1533 * None. 1534 * 1535 * RETURN: 1536 * MV_NOT_ALLOWED in case PEX interface is PEX-X. 1537 * MV_BAD_PARAM on bad parameters , 1538 * otherwise MV_OK 1539 * 1540 */ 1541 int pex_local_bus_num_set(u32 pex_if, u32 bus_num) 1542 { 1543 u32 val; 1544 1545 if (bus_num >= MAX_PEX_BUSSES) { 1546 DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n", 1547 bus_num, 4); 1548 return MV_ERROR; 1549 } 1550 1551 val = reg_read(PEX_STATUS_REG(pex_if)); 1552 val &= ~PXSR_PEX_BUS_NUM_MASK; 1553 val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; 1554 reg_write(PEX_STATUS_REG(pex_if), val); 1555 1556 return MV_OK; 1557 } 1558 1559 /* 1560 * pex_local_dev_num_set - Set PEX interface local device number. 1561 * 1562 * DESCRIPTION: 1563 * This function sets given PEX interface its local device number. 1564 * Note: In case the PEX interface is PEX-X, the information is read-only. 1565 * 1566 * INPUT: 1567 * pex_if - PEX interface number. 1568 * dev_num - Device number. 1569 * 1570 * OUTPUT: 1571 * None. 1572 * 1573 * RETURN: 1574 * MV_NOT_ALLOWED in case PEX interface is PEX-X. 1575 * MV_BAD_PARAM on bad parameters , 1576 * otherwise MV_OK 1577 * 1578 */ 1579 int pex_local_dev_num_set(u32 pex_if, u32 dev_num) 1580 { 1581 u32 val; 1582 1583 if (pex_if >= MV_PEX_MAX_IF) 1584 return MV_BAD_PARAM; 1585 1586 val = reg_read(PEX_STATUS_REG(pex_if)); 1587 val &= ~PXSR_PEX_DEV_NUM_MASK; 1588 val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; 1589 reg_write(PEX_STATUS_REG(pex_if), val); 1590 1591 return MV_OK; 1592 } 1593