1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _SYS_ENV_LIB_H 7 #define _SYS_ENV_LIB_H 8 9 #include "../../../drivers/ddr/marvell/a38x/ddr3_init.h" 10 11 /* Serdes definitions */ 12 #define COMMON_PHY_BASE_ADDR 0x18300 13 14 #define DEVICE_CONFIGURATION_REG0 0x18284 15 #define DEVICE_CONFIGURATION_REG1 0x18288 16 #define COMMON_PHY_CONFIGURATION1_REG 0x18300 17 #define COMMON_PHY_CONFIGURATION2_REG 0x18304 18 #define COMMON_PHY_CONFIGURATION4_REG 0x1830c 19 #define COMMON_PHY_STATUS1_REG 0x18318 20 #define COMMON_PHYS_SELECTORS_REG 0x183fc 21 #define SOC_CONTROL_REG1 0x18204 22 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 23 #define GBE_CONFIGURATION_REG 0x18460 24 #define DEVICE_SAMPLE_AT_RESET1_REG 0x18600 25 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 26 #define DEV_ID_REG 0x18238 27 28 #define CORE_PLL_PARAMETERS_REG 0xe42e0 29 #define CORE_PLL_CONFIG_REG 0xe42e4 30 31 #define QSGMII_CONTROL_REG1 0x18494 32 33 #define DEV_ID_REG_DEVICE_ID_OFFS 16 34 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000 35 36 #define SAR_DEV_ID_OFFS 27 37 #define SAR_DEV_ID_MASK 0x7 38 39 #define POWER_AND_PLL_CTRL_REG 0xa0004 40 #define CALIBRATION_CTRL_REG 0xa0008 41 #define DFE_REG0 0xa001c 42 #define DFE_REG3 0xa0028 43 #define RESET_DFE_REG 0xa0148 44 #define LOOPBACK_REG 0xa008c 45 #define SYNC_PATTERN_REG 0xa0090 46 #define INTERFACE_REG 0xa0094 47 #define ISOLATE_REG 0xa0098 48 #define MISC_REG 0xa013c 49 #define GLUE_REG 0xa0140 50 #define GENERATION_DIVIDER_FORCE_REG 0xa0144 51 #define PCIE_REG0 0xa0120 52 #define LANE_ALIGN_REG0 0xa0124 53 #define SQUELCH_FFE_SETTING_REG 0xa0018 54 #define G1_SETTINGS_0_REG 0xa0034 55 #define G1_SETTINGS_1_REG 0xa0038 56 #define G1_SETTINGS_3_REG 0xa0440 57 #define G1_SETTINGS_4_REG 0xa0444 58 #define G2_SETTINGS_0_REG 0xa003c 59 #define G2_SETTINGS_1_REG 0xa0040 60 #define G2_SETTINGS_2_REG 0xa00f8 61 #define G2_SETTINGS_3_REG 0xa0448 62 #define G2_SETTINGS_4_REG 0xa044c 63 #define G3_SETTINGS_0_REG 0xa0044 64 #define G3_SETTINGS_1_REG 0xa0048 65 #define G3_SETTINGS_3_REG 0xa0450 66 #define G3_SETTINGS_4_REG 0xa0454 67 #define VTHIMPCAL_CTRL_REG 0xa0104 68 #define REF_REG0 0xa0134 69 #define CAL_REG6 0xa0168 70 #define RX_REG2 0xa0184 71 #define RX_REG3 0xa0188 72 #define PCIE_REG1 0xa0288 73 #define PCIE_REG3 0xa0290 74 #define LANE_CFG1_REG 0xa0604 75 #define LANE_CFG4_REG 0xa0620 76 #define LANE_CFG5_REG 0xa0624 77 #define GLOBAL_CLK_CTRL 0xa0704 78 #define GLOBAL_MISC_CTRL 0xa0718 79 #define GLOBAL_CLK_SRC_HI 0xa0710 80 81 #define GLOBAL_CLK_CTRL 0xa0704 82 #define GLOBAL_MISC_CTRL 0xa0718 83 #define GLOBAL_PM_CTRL 0xa0740 84 85 /* SATA registers */ 86 #define SATA_CTRL_REG_IND_ADDR 0xa80a0 87 #define SATA_CTRL_REG_IND_DATA 0xa80a4 88 89 #define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178 90 #define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8 91 #define SATA_VENDOR_PORT_0_REG_DATA 0xa817c 92 #define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc 93 94 /* Reference clock values and mask */ 95 #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0 96 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1 97 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2 98 #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3 99 #define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7 100 #define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc 101 #define LANE_CFG4_REG_25MHZ_VAL 0x200 102 #define LANE_CFG4_REG_40MHZ_VAL 0x300 103 104 #define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f)) 105 #define GLOBAL_PM_CTRL_REG_MASK (~(0xff)) 106 #define LANE_CFG4_REG_MASK (~(0x1f00)) 107 108 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 109 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 110 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 111 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 112 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) 113 114 #define MAX_SELECTOR_VAL 10 115 116 /* TWSI addresses */ 117 /* starting from A38x A0, i2c address of EEPROM is 0x57 */ 118 #ifdef CONFIG_ARMADA_39X 119 #define EEPROM_I2C_ADDR 0x50 120 #else 121 #define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \ 122 MV_88F68XX_Z1_ID ? 0x50 : 0x57) 123 #endif 124 #define RD_GET_MODE_ADDR 0x4c 125 #define DB_GET_MODE_SLM1363_ADDR 0x25 126 #define DB_GET_MODE_SLM1364_ADDR 0x24 127 #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56 128 129 /* DB-BP Board 'SatR' mapping */ 130 #define SATR_DB_LANE1_MAX_OPTIONS 7 131 #define SATR_DB_LANE1_CFG_MASK 0x7 132 #define SATR_DB_LANE1_CFG_OFFSET 0 133 #define SATR_DB_LANE2_MAX_OPTIONS 4 134 #define SATR_DB_LANE2_CFG_MASK 0x38 135 #define SATR_DB_LANE2_CFG_OFFSET 3 136 137 /* GP Board 'SatR' mapping */ 138 #define SATR_GP_LANE1_CFG_MASK 0x4 139 #define SATR_GP_LANE1_CFG_OFFSET 2 140 #define SATR_GP_LANE2_CFG_MASK 0x8 141 #define SATR_GP_LANE2_CFG_OFFSET 3 142 143 /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */ 144 #define MPP_CTRL_REG 0x18000 145 #define MPP_SET_MASK (~(0xffff)) 146 #define MPP_SET_DATA (0x1111) 147 #define MPP_UART1_SET_MASK (~(0xff000)) 148 #define MPP_UART1_SET_DATA (0x66000) 149 150 #define AVS_DEBUG_CNTR_REG 0xe4124 151 #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073 152 153 #define AVS_ENABLED_CONTROL 0xe4130 154 #define AVS_LOW_VDD_LIMIT_OFFS 4 155 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) 156 #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) 157 158 #define AVS_HIGH_VDD_LIMIT_OFFS 12 159 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) 160 #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) 161 162 /* Board ID numbers */ 163 #define MARVELL_BOARD_ID_MASK 0x10 164 /* Customer boards for A38x */ 165 #define A38X_CUSTOMER_BOARD_ID_BASE 0x0 166 #define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0) 167 #define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1) 168 #define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2) 169 #define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \ 170 A38X_CUSTOMER_BOARD_ID_BASE) 171 172 /* Marvell boards for A38x */ 173 #define A38X_MARVELL_BOARD_ID_BASE 0x10 174 #define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0) 175 #define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1) 176 #define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2) 177 #define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3) 178 #define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4) 179 #define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5) 180 #define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6) 181 #define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7) 182 #define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \ 183 A38X_MARVELL_BOARD_ID_BASE) 184 185 /* Customer boards for A39x */ 186 #define A39X_CUSTOMER_BOARD_ID_BASE 0x20 187 #define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0) 188 #define A39X_CUSTOMER_BOARD_ID1 (A39X_CUSTOMER_BOARD_ID_BASE + 1) 189 #define A39X_MV_MAX_CUSTOMER_BOARD_ID (A39X_CUSTOMER_BOARD_ID_BASE + 2) 190 #define A39X_MV_CUSTOMER_BOARD_NUM (A39X_MV_MAX_CUSTOMER_BOARD_ID - \ 191 A39X_CUSTOMER_BOARD_ID_BASE) 192 193 /* Marvell boards for A39x */ 194 #define A39X_MARVELL_BOARD_ID_BASE 0x30 195 #define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0) 196 #define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1) 197 #define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2) 198 #define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \ 199 A39X_MARVELL_BOARD_ID_BASE) 200 201 #ifdef CONFIG_ARMADA_38X 202 #define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE 203 #define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0 204 #define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1 205 #define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID 206 #define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM 207 #define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE 208 #define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID 209 #define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM 210 #define MV_DEFAULT_BOARD_ID DB_68XX_ID 211 #define MV_DEFAULT_DEVICE_ID MV_6811 212 #elif defined(CONFIG_ARMADA_39X) 213 #define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE 214 #define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0 215 #define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1 216 #define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID 217 #define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM 218 #define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE 219 #define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID 220 #define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM 221 #define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID 222 #define MV_DEFAULT_DEVICE_ID MV_6920 223 #endif 224 225 #define MV_INVALID_BOARD_ID 0xffffffff 226 227 /* device revesion */ 228 #define DEV_VERSION_ID_REG 0x1823c 229 #define REVISON_ID_OFFS 8 230 #define REVISON_ID_MASK 0xf00 231 232 /* A38x revisions */ 233 #define MV_88F68XX_Z1_ID 0x0 234 #define MV_88F68XX_A0_ID 0x4 235 /* A39x revisions */ 236 #define MV_88F69XX_Z1_ID 0x2 237 238 #define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 239 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 240 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 241 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 242 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) 243 244 #define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8) 245 #define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \ 246 (MPP_REG_NUM(GPIO_NUM) * 8))); 247 #define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32) 248 #define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32) 249 250 /* device ID */ 251 /* Armada 38x Family */ 252 #define MV_6810_DEV_ID 0x6810 253 #define MV_6811_DEV_ID 0x6811 254 #define MV_6820_DEV_ID 0x6820 255 #define MV_6828_DEV_ID 0x6828 256 /* Armada 39x Family */ 257 #define MV_6920_DEV_ID 0x6920 258 #define MV_6928_DEV_ID 0x6928 259 260 enum { 261 MV_6810, 262 MV_6820, 263 MV_6811, 264 MV_6828, 265 MV_NONE, 266 MV_6920, 267 MV_6928, 268 MV_MAX_DEV_ID, 269 }; 270 271 #define MV_6820_INDEX 0 272 #define MV_6810_INDEX 1 273 #define MV_6811_INDEX 2 274 #define MV_6828_INDEX 3 275 276 #define MV_6920_INDEX 0 277 #define MV_6928_INDEX 1 278 279 #ifdef CONFIG_ARMADA_38X 280 #define MAX_DEV_ID_NUM 4 281 #else 282 #define MAX_DEV_ID_NUM 2 283 #endif 284 285 #define MV_6820_INDEX 0 286 #define MV_6810_INDEX 1 287 #define MV_6811_INDEX 2 288 #define MV_6828_INDEX 3 289 #define MV_6920_INDEX 0 290 #define MV_6928_INDEX 1 291 292 enum unit_id { 293 PEX_UNIT_ID, 294 ETH_GIG_UNIT_ID, 295 USB3H_UNIT_ID, 296 USB3D_UNIT_ID, 297 SATA_UNIT_ID, 298 QSGMII_UNIT_ID, 299 XAUI_UNIT_ID, 300 RXAUI_UNIT_ID, 301 MAX_UNITS_ID 302 }; 303 304 struct board_wakeup_gpio { 305 u32 board_id; 306 int gpio_num; 307 }; 308 309 enum suspend_wakeup_status { 310 SUSPEND_WAKEUP_DISABLED, 311 SUSPEND_WAKEUP_ENABLED, 312 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED, 313 }; 314 315 /* 316 * GPIO status indication for Suspend Wakeup: 317 * If suspend to RAM is supported and GPIO inidcation is implemented, 318 * set the gpio number 319 * If suspend to RAM is supported but GPIO indication is not implemented 320 * set '-2' 321 * If suspend to RAM is not supported set '-1' 322 */ 323 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT 324 #ifdef CONFIG_ARMADA_38X 325 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 326 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 327 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 328 }; 329 #else 330 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 331 {A39X_CUSTOMER_BOARD_ID0, -1 }, \ 332 {A39X_CUSTOMER_BOARD_ID0, -1 }, \ 333 }; 334 #endif /* CONFIG_ARMADA_38X */ 335 336 #else 337 338 #ifdef CONFIG_ARMADA_38X 339 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 340 {RD_NAS_68XX_ID, -2 }, \ 341 {DB_68XX_ID, -1 }, \ 342 {RD_AP_68XX_ID, -2 }, \ 343 {DB_AP_68XX_ID, -2 }, \ 344 {DB_GP_68XX_ID, -2 }, \ 345 {DB_BP_6821_ID, -2 }, \ 346 {DB_AMC_6820_ID, -2 }, \ 347 }; 348 #else 349 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 350 {A39X_RD_69XX_ID, -1 }, \ 351 {A39X_DB_69XX_ID, -1 }, \ 352 }; 353 #endif /* CONFIG_ARMADA_38X */ 354 #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 355 356 u32 mv_board_tclk_get(void); 357 u32 mv_board_id_get(void); 358 u32 mv_board_id_index_get(u32 board_id); 359 u32 sys_env_unit_max_num_get(enum unit_id unit); 360 enum suspend_wakeup_status sys_env_suspend_wakeup_check(void); 361 u8 sys_env_device_rev_get(void); 362 u32 sys_env_device_id_get(void); 363 u16 sys_env_model_get(void); 364 struct dlb_config *sys_env_dlb_config_ptr_get(void); 365 u32 sys_env_get_cs_ena_from_reg(void); 366 367 #endif /* _SYS_ENV_LIB_H */ 368