1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _HIGH_SPEED_ENV_SPEC_H 8 #define _HIGH_SPEED_ENV_SPEC_H 9 10 #include "seq_exec.h" 11 12 /* 13 * For setting or clearing a certain bit (bit is a number between 0 and 31) 14 * in the data 15 */ 16 #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) 17 #define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit)))) 18 19 #define MAX_SERDES_LANES 7 /* as in a39x */ 20 21 /* Serdes revision */ 22 /* Serdes revision 1.2 (for A38x-Z1) */ 23 #define MV_SERDES_REV_1_2 0x0 24 /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */ 25 #define MV_SERDES_REV_2_1 0x1 26 #define MV_SERDES_REV_NA 0xff 27 28 #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane)) 29 30 #define PEX_X4_ENABLE_OFFS \ 31 (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31) 32 33 /* Serdes lane types */ 34 enum serdes_type { 35 PEX0, 36 PEX1, 37 PEX2, 38 PEX3, 39 SATA0, 40 SATA1, 41 SATA2, 42 SATA3, 43 SGMII0, 44 SGMII1, 45 SGMII2, 46 QSGMII, 47 USB3_HOST0, 48 USB3_HOST1, 49 USB3_DEVICE, 50 SGMII3, 51 XAUI, 52 RXAUI, 53 DEFAULT_SERDES, 54 LAST_SERDES_TYPE 55 }; 56 57 /* Serdes baud rates */ 58 enum serdes_speed { 59 SERDES_SPEED_1_25_GBPS, 60 SERDES_SPEED_1_5_GBPS, 61 SERDES_SPEED_2_5_GBPS, 62 SERDES_SPEED_3_GBPS, 63 SERDES_SPEED_3_125_GBPS, 64 SERDES_SPEED_5_GBPS, 65 SERDES_SPEED_6_GBPS, 66 SERDES_SPEED_6_25_GBPS, 67 LAST_SERDES_SPEED 68 }; 69 70 /* Serdes modes */ 71 enum serdes_mode { 72 PEX_ROOT_COMPLEX_X1, 73 PEX_ROOT_COMPLEX_X4, 74 PEX_END_POINT_X1, 75 PEX_END_POINT_X4, 76 77 SERDES_DEFAULT_MODE, /* not pex */ 78 79 SERDES_LAST_MODE 80 }; 81 82 struct serdes_map { 83 enum serdes_type serdes_type; 84 enum serdes_speed serdes_speed; 85 enum serdes_mode serdes_mode; 86 int swap_rx; 87 int swap_tx; 88 }; 89 90 /* Serdes ref clock options */ 91 enum ref_clock { 92 REF_CLOCK_25MHZ, 93 REF_CLOCK_100MHZ, 94 REF_CLOCK_40MHZ, 95 REF_CLOCK_UNSUPPORTED 96 }; 97 98 /* Serdes sequences */ 99 enum serdes_seq { 100 SATA_PORT_0_ONLY_POWER_UP_SEQ, 101 SATA_PORT_1_ONLY_POWER_UP_SEQ, 102 SATA_POWER_UP_SEQ, 103 SATA_1_5_SPEED_CONFIG_SEQ, 104 SATA_3_SPEED_CONFIG_SEQ, 105 SATA_6_SPEED_CONFIG_SEQ, 106 SATA_ELECTRICAL_CONFIG_SEQ, 107 SATA_TX_CONFIG_SEQ1, 108 SATA_PORT_0_ONLY_TX_CONFIG_SEQ, 109 SATA_PORT_1_ONLY_TX_CONFIG_SEQ, 110 SATA_TX_CONFIG_SEQ2, 111 112 SGMII_POWER_UP_SEQ, 113 SGMII_1_25_SPEED_CONFIG_SEQ, 114 SGMII_3_125_SPEED_CONFIG_SEQ, 115 SGMII_ELECTRICAL_CONFIG_SEQ, 116 SGMII_TX_CONFIG_SEQ1, 117 SGMII_TX_CONFIG_SEQ2, 118 119 PEX_POWER_UP_SEQ, 120 PEX_2_5_SPEED_CONFIG_SEQ, 121 PEX_5_SPEED_CONFIG_SEQ, 122 PEX_ELECTRICAL_CONFIG_SEQ, 123 PEX_TX_CONFIG_SEQ1, 124 PEX_TX_CONFIG_SEQ2, 125 PEX_TX_CONFIG_SEQ3, 126 PEX_BY_4_CONFIG_SEQ, 127 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ, 128 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ, 129 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ, 130 131 USB3_POWER_UP_SEQ, 132 USB3_HOST_SPEED_CONFIG_SEQ, 133 USB3_DEVICE_SPEED_CONFIG_SEQ, 134 USB3_ELECTRICAL_CONFIG_SEQ, 135 USB3_TX_CONFIG_SEQ1, 136 USB3_TX_CONFIG_SEQ2, 137 USB3_TX_CONFIG_SEQ3, 138 USB3_DEVICE_CONFIG_SEQ, 139 140 USB2_POWER_UP_SEQ, 141 142 SERDES_POWER_DOWN_SEQ, 143 144 SGMII3_POWER_UP_SEQ, 145 SGMII3_1_25_SPEED_CONFIG_SEQ, 146 SGMII3_TX_CONFIG_SEQ1, 147 SGMII3_TX_CONFIG_SEQ2, 148 149 QSGMII_POWER_UP_SEQ, 150 QSGMII_5_SPEED_CONFIG_SEQ, 151 QSGMII_ELECTRICAL_CONFIG_SEQ, 152 QSGMII_TX_CONFIG_SEQ1, 153 QSGMII_TX_CONFIG_SEQ2, 154 155 XAUI_POWER_UP_SEQ, 156 XAUI_3_125_SPEED_CONFIG_SEQ, 157 XAUI_ELECTRICAL_CONFIG_SEQ, 158 XAUI_TX_CONFIG_SEQ1, 159 XAUI_TX_CONFIG_SEQ2, 160 161 RXAUI_POWER_UP_SEQ, 162 RXAUI_6_25_SPEED_CONFIG_SEQ, 163 RXAUI_ELECTRICAL_CONFIG_SEQ, 164 RXAUI_TX_CONFIG_SEQ1, 165 RXAUI_TX_CONFIG_SEQ2, 166 167 SERDES_LAST_SEQ 168 }; 169 170 /* The different sequence types for PEX and USB3 */ 171 enum { 172 PEX, 173 USB3, 174 LAST_PEX_USB_SEQ_TYPE 175 }; 176 177 enum { 178 PEXSERDES_SPEED_2_5_GBPS, 179 PEXSERDES_SPEED_5_GBPS, 180 USB3SERDES_SPEED_5_GBPS_HOST, 181 USB3SERDES_SPEED_5_GBPS_DEVICE, 182 LAST_PEX_USB_SPEED_SEQ_TYPE 183 }; 184 185 /* The different sequence types for SATA and SGMII */ 186 enum { 187 SATA, 188 SGMII, 189 SGMII_3_125, 190 LAST_SATA_SGMII_SEQ_TYPE 191 }; 192 193 enum { 194 QSGMII_SEQ_IDX, 195 LAST_QSGMII_SEQ_TYPE 196 }; 197 198 enum { 199 XAUI_SEQ_IDX, 200 RXAUI_SEQ_IDX, 201 LAST_XAUI_RXAUI_SEQ_TYPE 202 }; 203 204 enum { 205 SATASERDES_SPEED_1_5_GBPS, 206 SATASERDES_SPEED_3_GBPS, 207 SATASERDES_SPEED_6_GBPS, 208 SGMIISERDES_SPEED_1_25_GBPS, 209 SGMIISERDES_SPEED_3_125_GBPS, 210 LAST_SATA_SGMII_SPEED_SEQ_TYPE 211 }; 212 213 extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 214 extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 215 216 u8 hws_ctrl_serdes_rev_get(void); 217 int mv_update_serdes_select_phy_mode_seq(void); 218 int hws_board_topology_load(struct serdes_map *serdes_map_array); 219 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, 220 enum serdes_speed baud_rate); 221 int hws_serdes_seq_init(void); 222 int hws_serdes_seq_db_init(void); 223 int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map); 224 int hws_ctrl_high_speed_serdes_phy_config(void); 225 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, 226 enum serdes_type serdes_type, 227 enum serdes_speed baud_rate, 228 enum serdes_mode serdes_mode, 229 enum ref_clock ref_clock); 230 int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up, 231 enum serdes_type serdes_type, 232 enum serdes_speed baud_rate, 233 enum serdes_mode serdes_mode, 234 enum ref_clock ref_clock); 235 u32 hws_serdes_silicon_ref_clock_get(void); 236 int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type, 237 enum ref_clock *ref_clock); 238 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, 239 enum ref_clock ref_clock); 240 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_config_map); 241 u32 hws_serdes_get_phy_selector_val(int serdes_num, 242 enum serdes_type serdes_type); 243 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type); 244 u32 hws_serdes_get_max_lane(void); 245 int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset, 246 u32 *unit_base_reg, u32 *unit_offset); 247 int hws_pex_tx_config_seq(struct serdes_map *serdes_map); 248 u32 hws_get_physical_serdes_num(u32 serdes_num); 249 int hws_is_serdes_active(u8 lane_num); 250 251 #endif /* _HIGH_SPEED_ENV_SPEC_H */ 252