1*edb47025SStefan Roese /* 2*edb47025SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*edb47025SStefan Roese * 4*edb47025SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*edb47025SStefan Roese */ 6*edb47025SStefan Roese 7*edb47025SStefan Roese #ifndef _HIGH_SPEED_ENV_SPEC_H 8*edb47025SStefan Roese #define _HIGH_SPEED_ENV_SPEC_H 9*edb47025SStefan Roese 10*edb47025SStefan Roese #include "seq_exec.h" 11*edb47025SStefan Roese 12*edb47025SStefan Roese /* 13*edb47025SStefan Roese * For setting or clearing a certain bit (bit is a number between 0 and 31) 14*edb47025SStefan Roese * in the data 15*edb47025SStefan Roese */ 16*edb47025SStefan Roese #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) 17*edb47025SStefan Roese #define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit)))) 18*edb47025SStefan Roese 19*edb47025SStefan Roese #define MAX_SERDES_LANES 7 /* as in a39x */ 20*edb47025SStefan Roese 21*edb47025SStefan Roese /* Serdes revision */ 22*edb47025SStefan Roese /* Serdes revision 1.2 (for A38x-Z1) */ 23*edb47025SStefan Roese #define MV_SERDES_REV_1_2 0x0 24*edb47025SStefan Roese /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */ 25*edb47025SStefan Roese #define MV_SERDES_REV_2_1 0x1 26*edb47025SStefan Roese #define MV_SERDES_REV_NA 0xff 27*edb47025SStefan Roese 28*edb47025SStefan Roese #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane)) 29*edb47025SStefan Roese 30*edb47025SStefan Roese #define PEX_X4_ENABLE_OFFS \ 31*edb47025SStefan Roese (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31) 32*edb47025SStefan Roese 33*edb47025SStefan Roese /* Serdes lane types */ 34*edb47025SStefan Roese enum serdes_type { 35*edb47025SStefan Roese PEX0, 36*edb47025SStefan Roese PEX1, 37*edb47025SStefan Roese PEX2, 38*edb47025SStefan Roese PEX3, 39*edb47025SStefan Roese SATA0, 40*edb47025SStefan Roese SATA1, 41*edb47025SStefan Roese SATA2, 42*edb47025SStefan Roese SATA3, 43*edb47025SStefan Roese SGMII0, 44*edb47025SStefan Roese SGMII1, 45*edb47025SStefan Roese SGMII2, 46*edb47025SStefan Roese QSGMII, 47*edb47025SStefan Roese USB3_HOST0, 48*edb47025SStefan Roese USB3_HOST1, 49*edb47025SStefan Roese USB3_DEVICE, 50*edb47025SStefan Roese SGMII3, 51*edb47025SStefan Roese XAUI, 52*edb47025SStefan Roese RXAUI, 53*edb47025SStefan Roese DEFAULT_SERDES, 54*edb47025SStefan Roese LAST_SERDES_TYPE 55*edb47025SStefan Roese }; 56*edb47025SStefan Roese 57*edb47025SStefan Roese /* Serdes baud rates */ 58*edb47025SStefan Roese enum serdes_speed { 59*edb47025SStefan Roese SERDES_SPEED_1_25_GBPS, 60*edb47025SStefan Roese SERDES_SPEED_1_5_GBPS, 61*edb47025SStefan Roese SERDES_SPEED_2_5_GBPS, 62*edb47025SStefan Roese SERDES_SPEED_3_GBPS, 63*edb47025SStefan Roese SERDES_SPEED_3_125_GBPS, 64*edb47025SStefan Roese SERDES_SPEED_5_GBPS, 65*edb47025SStefan Roese SERDES_SPEED_6_GBPS, 66*edb47025SStefan Roese SERDES_SPEED_6_25_GBPS, 67*edb47025SStefan Roese LAST_SERDES_SPEED 68*edb47025SStefan Roese }; 69*edb47025SStefan Roese 70*edb47025SStefan Roese /* Serdes modes */ 71*edb47025SStefan Roese enum serdes_mode { 72*edb47025SStefan Roese PEX_ROOT_COMPLEX_X1, 73*edb47025SStefan Roese PEX_ROOT_COMPLEX_X4, 74*edb47025SStefan Roese PEX_END_POINT_X1, 75*edb47025SStefan Roese PEX_END_POINT_X4, 76*edb47025SStefan Roese 77*edb47025SStefan Roese SERDES_DEFAULT_MODE, /* not pex */ 78*edb47025SStefan Roese 79*edb47025SStefan Roese SERDES_LAST_MODE 80*edb47025SStefan Roese }; 81*edb47025SStefan Roese 82*edb47025SStefan Roese struct serdes_map { 83*edb47025SStefan Roese enum serdes_type serdes_type; 84*edb47025SStefan Roese enum serdes_speed serdes_speed; 85*edb47025SStefan Roese enum serdes_mode serdes_mode; 86*edb47025SStefan Roese int swap_rx; 87*edb47025SStefan Roese int swap_tx; 88*edb47025SStefan Roese }; 89*edb47025SStefan Roese 90*edb47025SStefan Roese /* Serdes ref clock options */ 91*edb47025SStefan Roese enum ref_clock { 92*edb47025SStefan Roese REF_CLOCK_25MHZ, 93*edb47025SStefan Roese REF_CLOCK_100MHZ, 94*edb47025SStefan Roese REF_CLOCK_40MHZ, 95*edb47025SStefan Roese REF_CLOCK_UNSUPPORTED 96*edb47025SStefan Roese }; 97*edb47025SStefan Roese 98*edb47025SStefan Roese /* Serdes sequences */ 99*edb47025SStefan Roese enum serdes_seq { 100*edb47025SStefan Roese SATA_PORT_0_ONLY_POWER_UP_SEQ, 101*edb47025SStefan Roese SATA_PORT_1_ONLY_POWER_UP_SEQ, 102*edb47025SStefan Roese SATA_POWER_UP_SEQ, 103*edb47025SStefan Roese SATA_1_5_SPEED_CONFIG_SEQ, 104*edb47025SStefan Roese SATA_3_SPEED_CONFIG_SEQ, 105*edb47025SStefan Roese SATA_6_SPEED_CONFIG_SEQ, 106*edb47025SStefan Roese SATA_ELECTRICAL_CONFIG_SEQ, 107*edb47025SStefan Roese SATA_TX_CONFIG_SEQ1, 108*edb47025SStefan Roese SATA_PORT_0_ONLY_TX_CONFIG_SEQ, 109*edb47025SStefan Roese SATA_PORT_1_ONLY_TX_CONFIG_SEQ, 110*edb47025SStefan Roese SATA_TX_CONFIG_SEQ2, 111*edb47025SStefan Roese 112*edb47025SStefan Roese SGMII_POWER_UP_SEQ, 113*edb47025SStefan Roese SGMII_1_25_SPEED_CONFIG_SEQ, 114*edb47025SStefan Roese SGMII_3_125_SPEED_CONFIG_SEQ, 115*edb47025SStefan Roese SGMII_ELECTRICAL_CONFIG_SEQ, 116*edb47025SStefan Roese SGMII_TX_CONFIG_SEQ1, 117*edb47025SStefan Roese SGMII_TX_CONFIG_SEQ2, 118*edb47025SStefan Roese 119*edb47025SStefan Roese PEX_POWER_UP_SEQ, 120*edb47025SStefan Roese PEX_2_5_SPEED_CONFIG_SEQ, 121*edb47025SStefan Roese PEX_5_SPEED_CONFIG_SEQ, 122*edb47025SStefan Roese PEX_ELECTRICAL_CONFIG_SEQ, 123*edb47025SStefan Roese PEX_TX_CONFIG_SEQ1, 124*edb47025SStefan Roese PEX_TX_CONFIG_SEQ2, 125*edb47025SStefan Roese PEX_TX_CONFIG_SEQ3, 126*edb47025SStefan Roese PEX_BY_4_CONFIG_SEQ, 127*edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_25MHZ_SEQ, 128*edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_100MHZ_SEQ, 129*edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_40MHZ_SEQ, 130*edb47025SStefan Roese 131*edb47025SStefan Roese USB3_POWER_UP_SEQ, 132*edb47025SStefan Roese USB3_HOST_SPEED_CONFIG_SEQ, 133*edb47025SStefan Roese USB3_DEVICE_SPEED_CONFIG_SEQ, 134*edb47025SStefan Roese USB3_ELECTRICAL_CONFIG_SEQ, 135*edb47025SStefan Roese USB3_TX_CONFIG_SEQ1, 136*edb47025SStefan Roese USB3_TX_CONFIG_SEQ2, 137*edb47025SStefan Roese USB3_TX_CONFIG_SEQ3, 138*edb47025SStefan Roese USB3_DEVICE_CONFIG_SEQ, 139*edb47025SStefan Roese 140*edb47025SStefan Roese USB2_POWER_UP_SEQ, 141*edb47025SStefan Roese 142*edb47025SStefan Roese SERDES_POWER_DOWN_SEQ, 143*edb47025SStefan Roese 144*edb47025SStefan Roese SGMII3_POWER_UP_SEQ, 145*edb47025SStefan Roese SGMII3_1_25_SPEED_CONFIG_SEQ, 146*edb47025SStefan Roese SGMII3_TX_CONFIG_SEQ1, 147*edb47025SStefan Roese SGMII3_TX_CONFIG_SEQ2, 148*edb47025SStefan Roese 149*edb47025SStefan Roese QSGMII_POWER_UP_SEQ, 150*edb47025SStefan Roese QSGMII_5_SPEED_CONFIG_SEQ, 151*edb47025SStefan Roese QSGMII_ELECTRICAL_CONFIG_SEQ, 152*edb47025SStefan Roese QSGMII_TX_CONFIG_SEQ1, 153*edb47025SStefan Roese QSGMII_TX_CONFIG_SEQ2, 154*edb47025SStefan Roese 155*edb47025SStefan Roese XAUI_POWER_UP_SEQ, 156*edb47025SStefan Roese XAUI_3_125_SPEED_CONFIG_SEQ, 157*edb47025SStefan Roese XAUI_ELECTRICAL_CONFIG_SEQ, 158*edb47025SStefan Roese XAUI_TX_CONFIG_SEQ1, 159*edb47025SStefan Roese XAUI_TX_CONFIG_SEQ2, 160*edb47025SStefan Roese 161*edb47025SStefan Roese RXAUI_POWER_UP_SEQ, 162*edb47025SStefan Roese RXAUI_6_25_SPEED_CONFIG_SEQ, 163*edb47025SStefan Roese RXAUI_ELECTRICAL_CONFIG_SEQ, 164*edb47025SStefan Roese RXAUI_TX_CONFIG_SEQ1, 165*edb47025SStefan Roese RXAUI_TX_CONFIG_SEQ2, 166*edb47025SStefan Roese 167*edb47025SStefan Roese SERDES_LAST_SEQ 168*edb47025SStefan Roese }; 169*edb47025SStefan Roese 170*edb47025SStefan Roese /* The different sequence types for PEX and USB3 */ 171*edb47025SStefan Roese enum { 172*edb47025SStefan Roese PEX, 173*edb47025SStefan Roese USB3, 174*edb47025SStefan Roese LAST_PEX_USB_SEQ_TYPE 175*edb47025SStefan Roese }; 176*edb47025SStefan Roese 177*edb47025SStefan Roese enum { 178*edb47025SStefan Roese PEXSERDES_SPEED_2_5_GBPS, 179*edb47025SStefan Roese PEXSERDES_SPEED_5_GBPS, 180*edb47025SStefan Roese USB3SERDES_SPEED_5_GBPS_HOST, 181*edb47025SStefan Roese USB3SERDES_SPEED_5_GBPS_DEVICE, 182*edb47025SStefan Roese LAST_PEX_USB_SPEED_SEQ_TYPE 183*edb47025SStefan Roese }; 184*edb47025SStefan Roese 185*edb47025SStefan Roese /* The different sequence types for SATA and SGMII */ 186*edb47025SStefan Roese enum { 187*edb47025SStefan Roese SATA, 188*edb47025SStefan Roese SGMII, 189*edb47025SStefan Roese SGMII_3_125, 190*edb47025SStefan Roese LAST_SATA_SGMII_SEQ_TYPE 191*edb47025SStefan Roese }; 192*edb47025SStefan Roese 193*edb47025SStefan Roese enum { 194*edb47025SStefan Roese QSGMII_SEQ_IDX, 195*edb47025SStefan Roese LAST_QSGMII_SEQ_TYPE 196*edb47025SStefan Roese }; 197*edb47025SStefan Roese 198*edb47025SStefan Roese enum { 199*edb47025SStefan Roese XAUI_SEQ_IDX, 200*edb47025SStefan Roese RXAUI_SEQ_IDX, 201*edb47025SStefan Roese LAST_XAUI_RXAUI_SEQ_TYPE 202*edb47025SStefan Roese }; 203*edb47025SStefan Roese 204*edb47025SStefan Roese enum { 205*edb47025SStefan Roese SATASERDES_SPEED_1_5_GBPS, 206*edb47025SStefan Roese SATASERDES_SPEED_3_GBPS, 207*edb47025SStefan Roese SATASERDES_SPEED_6_GBPS, 208*edb47025SStefan Roese SGMIISERDES_SPEED_1_25_GBPS, 209*edb47025SStefan Roese SGMIISERDES_SPEED_3_125_GBPS, 210*edb47025SStefan Roese LAST_SATA_SGMII_SPEED_SEQ_TYPE 211*edb47025SStefan Roese }; 212*edb47025SStefan Roese 213*edb47025SStefan Roese extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 214*edb47025SStefan Roese extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 215*edb47025SStefan Roese 216*edb47025SStefan Roese u8 hws_ctrl_serdes_rev_get(void); 217*edb47025SStefan Roese int mv_update_serdes_select_phy_mode_seq(void); 218*edb47025SStefan Roese int hws_board_topology_load(struct serdes_map *serdes_map_array); 219*edb47025SStefan Roese enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, 220*edb47025SStefan Roese enum serdes_speed baud_rate); 221*edb47025SStefan Roese int hws_serdes_seq_init(void); 222*edb47025SStefan Roese int hws_serdes_seq_db_init(void); 223*edb47025SStefan Roese int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map); 224*edb47025SStefan Roese int hws_ctrl_high_speed_serdes_phy_config(void); 225*edb47025SStefan Roese int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, 226*edb47025SStefan Roese enum serdes_type serdes_type, 227*edb47025SStefan Roese enum serdes_speed baud_rate, 228*edb47025SStefan Roese enum serdes_mode serdes_mode, 229*edb47025SStefan Roese enum ref_clock ref_clock); 230*edb47025SStefan Roese int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up, 231*edb47025SStefan Roese enum serdes_type serdes_type, 232*edb47025SStefan Roese enum serdes_speed baud_rate, 233*edb47025SStefan Roese enum serdes_mode serdes_mode, 234*edb47025SStefan Roese enum ref_clock ref_clock); 235*edb47025SStefan Roese u32 hws_serdes_silicon_ref_clock_get(void); 236*edb47025SStefan Roese int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type, 237*edb47025SStefan Roese enum ref_clock *ref_clock); 238*edb47025SStefan Roese int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, 239*edb47025SStefan Roese enum ref_clock ref_clock); 240*edb47025SStefan Roese int hws_update_serdes_phy_selectors(struct serdes_map *serdes_config_map); 241*edb47025SStefan Roese u32 hws_serdes_get_phy_selector_val(int serdes_num, 242*edb47025SStefan Roese enum serdes_type serdes_type); 243*edb47025SStefan Roese u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type); 244*edb47025SStefan Roese u32 hws_serdes_get_max_lane(void); 245*edb47025SStefan Roese int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset, 246*edb47025SStefan Roese u32 *unit_base_reg, u32 *unit_offset); 247*edb47025SStefan Roese int hws_pex_tx_config_seq(struct serdes_map *serdes_map); 248*edb47025SStefan Roese u32 hws_get_physical_serdes_num(u32 serdes_num); 249*edb47025SStefan Roese int hws_is_serdes_active(u8 lane_num); 250*edb47025SStefan Roese 251*edb47025SStefan Roese #endif /* _HIGH_SPEED_ENV_SPEC_H */ 252