1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "high_speed_env_spec.h" 14 #include "sys_env_lib.h" 15 #include "ctrl_pex.h" 16 17 #if defined(CONFIG_ARMADA_38X) 18 #elif defined(CONFIG_ARMADA_39X) 19 #else 20 #error "No device is defined" 21 #endif 22 23 24 /* 25 * serdes_seq_db - holds all serdes sequences, their size and the 26 * relevant index in the data array initialized in serdes_seq_init 27 */ 28 struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ]; 29 30 #define SERDES_VERSION "2.0" 31 #define ENDED_OK "High speed PHY - Ended Successfully\n" 32 33 #define LINK_WAIT_CNTR 100 34 #define LINK_WAIT_SLEEP 100 35 36 #define MAX_UNIT_NUMB 4 37 #define TOPOLOGY_TEST_OK 0 38 #define WRONG_NUMBER_OF_UNITS 1 39 #define SERDES_ALREADY_IN_USE 2 40 #define UNIT_NUMBER_VIOLATION 3 41 42 /* 43 * serdes_lane_in_use_count contains the exact amount of serdes lanes 44 * needed per type 45 */ 46 u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = { 47 /* 0 1 2 3 */ 48 { 1, 1, 1, 1 }, /* PEX */ 49 { 1, 1, 1, 1 }, /* ETH_GIG */ 50 { 1, 1, 0, 0 }, /* USB3H */ 51 { 1, 1, 1, 0 }, /* USB3D */ 52 { 1, 1, 1, 1 }, /* SATA */ 53 { 1, 0, 0, 0 }, /* QSGMII */ 54 { 4, 0, 0, 0 }, /* XAUI */ 55 { 2, 0, 0, 0 } /* RXAUI */ 56 }; 57 58 /* 59 * serdes_unit_count count unit number. 60 * (i.e a single XAUI is counted as 1 unit) 61 */ 62 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 }; 63 64 /* Selector mapping for A380-A0 and A390-Z1 */ 65 u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = { 66 /* 0 1 2 3 4 5 6 */ 67 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */ 68 { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */ 69 { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */ 70 { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */ 71 { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */ 72 { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */ 73 { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */ 74 { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */ 75 { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */ 76 { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */ 77 { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */ 78 { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */ 79 { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */ 80 { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */ 81 { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */ 82 #ifdef CONFIG_ARMADA_39X 83 { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */ 84 { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */ 85 { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */ 86 #endif 87 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */ 88 }; 89 90 /* Selector mapping for PEX by 4 confiuration */ 91 u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 }; 92 93 static const char *const serdes_type_to_string[] = { 94 "PCIe0", 95 "PCIe1", 96 "PCIe2", 97 "PCIe3", 98 "SATA0", 99 "SATA1", 100 "SATA2", 101 "SATA3", 102 "SGMII0", 103 "SGMII1", 104 "SGMII2", 105 "QSGMII", 106 "USB3 HOST0", 107 "USB3 HOST1", 108 "USB3 DEVICE", 109 "SGMII3", 110 "XAUI", 111 "RXAUI", 112 "DEFAULT SERDES", 113 "LAST_SERDES_TYPE" 114 }; 115 116 struct serdes_unit_data { 117 u8 serdes_unit_id; 118 u8 serdes_unit_num; 119 }; 120 121 static struct serdes_unit_data serdes_type_to_unit_info[] = { 122 {PEX_UNIT_ID, 0,}, 123 {PEX_UNIT_ID, 1,}, 124 {PEX_UNIT_ID, 2,}, 125 {PEX_UNIT_ID, 3,}, 126 {SATA_UNIT_ID, 0,}, 127 {SATA_UNIT_ID, 1,}, 128 {SATA_UNIT_ID, 2,}, 129 {SATA_UNIT_ID, 3,}, 130 {ETH_GIG_UNIT_ID, 0,}, 131 {ETH_GIG_UNIT_ID, 1,}, 132 {ETH_GIG_UNIT_ID, 2,}, 133 {QSGMII_UNIT_ID, 0,}, 134 {USB3H_UNIT_ID, 0,}, 135 {USB3H_UNIT_ID, 1,}, 136 {USB3D_UNIT_ID, 0,}, 137 {ETH_GIG_UNIT_ID, 3,}, 138 {XAUI_UNIT_ID, 0,}, 139 {RXAUI_UNIT_ID, 0,}, 140 }; 141 142 /* Sequences DB */ 143 144 /* 145 * SATA and SGMII 146 */ 147 148 struct op_params sata_port0_power_up_params[] = { 149 /* 150 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 151 * num_of_loops 152 */ 153 /* Access to reg 0x48(OOB param 1) */ 154 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0}, 155 /* OOB Com_wake and Com_reset spacing upper limit data */ 156 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0}, 157 /* Access to reg 0xa(PHY Control) */ 158 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0}, 159 /* Rx clk and Tx clk select non-inverted mode */ 160 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0}, 161 /* Power Down Sata addr */ 162 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0}, 163 /* Power Down Sata Port 0 */ 164 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0}, 165 }; 166 167 struct op_params sata_port1_power_up_params[] = { 168 /* 169 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 170 * num_of_loops 171 */ 172 /* Access to reg 0x48(OOB param 1) */ 173 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0}, 174 /* OOB Com_wake and Com_reset spacing upper limit data */ 175 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0}, 176 /* Access to reg 0xa(PHY Control) */ 177 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0}, 178 /* Rx clk and Tx clk select non-inverted mode */ 179 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0}, 180 /* Power Down Sata addr */ 181 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0}, 182 /* Power Down Sata Port 1 */ 183 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0}, 184 }; 185 186 /* SATA and SGMII - power up seq */ 187 struct op_params sata_and_sgmii_power_up_params[] = { 188 /* 189 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 190 * wait_time, num_of_loops 191 */ 192 /* Power Up */ 193 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002}, 194 0, 0}, 195 /* Unreset */ 196 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0}, 197 /* Phy Selector */ 198 {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0}, 199 /* Ref clock source select */ 200 {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0} 201 }; 202 203 /* SATA and SGMII - speed config seq */ 204 struct op_params sata_and_sgmii_speed_config_params[] = { 205 /* 206 * unit_base_reg, unit_offset, mask, SATA data, 207 * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops 208 */ 209 /* Baud Rate */ 210 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, 211 {0x8800000, 0x19800000, 0x22000000}, 0, 0}, 212 /* Select Baud Rate for SATA only */ 213 {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0}, 214 /* Phy Gen RX and TX */ 215 {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0}, 216 /* Bus Width */ 217 {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0} 218 }; 219 220 /* SATA and SGMII - TX config seq */ 221 struct op_params sata_and_sgmii_tx_config_params1[] = { 222 /* 223 * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data, 224 * wait_time, num_of_loops 225 */ 226 {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0}, 227 /* Sft Reset pulse */ 228 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0}, 229 /* Sft Reset pulse */ 230 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0}, 231 /* Power up PLL, RX and TX */ 232 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000}, 233 0, 0} 234 }; 235 236 struct op_params sata_port0_tx_config_params[] = { 237 /* 238 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 239 * num_of_loops 240 */ 241 /* Power Down Sata addr */ 242 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0}, 243 /* Power Down Sata Port 0 */ 244 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0}, 245 /* Regret bit addr */ 246 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0}, 247 /* Regret bit data */ 248 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0} 249 }; 250 251 struct op_params sata_port1_tx_config_params[] = { 252 /* 253 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 254 * num_of_loops 255 */ 256 /* Power Down Sata addr */ 257 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0}, 258 /* Power Down Sata Port 1 */ 259 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0}, 260 /* Regret bit addr */ 261 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0}, 262 /* Regret bit data */ 263 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0} 264 }; 265 266 struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = { 267 /* 268 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 269 * wait_time, num_of_loops 270 */ 271 /* Wait for PHY power up sequence to finish */ 272 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000}, 273 /* Wait for PHY power up sequence to finish */ 274 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000} 275 }; 276 277 struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = { 278 /* 279 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 280 * wait_time, num_of_loops 281 */ 282 /* Wait for PHY power up sequence to finish */ 283 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000}, 284 /* Assert Rx Init for SGMII */ 285 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000}, 286 0, 0}, 287 /* Assert Rx Init for SATA */ 288 {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0}, 289 /* Wait for PHY power up sequence to finish */ 290 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}, 291 /* De-assert Rx Init for SGMII */ 292 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0}, 293 /* De-assert Rx Init for SATA */ 294 {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0}, 295 /* os_ph_offset_force (align 90) */ 296 {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0}, 297 /* Set os_ph_valid */ 298 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0}, 299 /* Unset os_ph_valid */ 300 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0}, 301 }; 302 303 struct op_params sata_electrical_config_serdes_rev1_params[] = { 304 /* 305 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 306 * num_of_loops 307 */ 308 /* enable SSC and DFE update enable */ 309 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0}, 310 /* tximpcal_th and rximpcal_th */ 311 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0}, 312 /* SQ_THRESH and FFE Setting */ 313 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0}, 314 /* G1_TX SLEW, EMPH1 and AMP */ 315 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0}, 316 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 317 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0}, 318 /* G2_TX SLEW, EMPH1 and AMP */ 319 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0}, 320 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 321 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0}, 322 /* G3_TX SLEW, EMPH1 and AMP */ 323 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0}, 324 /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 325 {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0}, 326 /* Cal rxclkalign90 ext enable and Cal os ph ext */ 327 {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0}, 328 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */ 329 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0}, 330 }; 331 332 struct op_params sata_electrical_config_serdes_rev2_params[] = { 333 /* 334 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 335 * num_of_loops 336 */ 337 /* SQ_THRESH and FFE Setting */ 338 {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0}, 339 /* enable SSC and DFE update enable */ 340 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0}, 341 /* G1_TX SLEW, EMPH1 and AMP */ 342 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0}, 343 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 344 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 345 /* G2_TX SLEW, EMPH1 and AMP */ 346 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0}, 347 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 348 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 349 /* G3_TX SLEW, EMPH1 and AMP */ 350 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0}, 351 /* 352 * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3, 353 * DC wander calibration dis 354 */ 355 {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0}, 356 /* Bit[12]=0x0 idle_sync_en */ 357 {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0}, 358 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */ 359 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0}, 360 /* tximpcal_th and rximpcal_th */ 361 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 362 /* DFE_STEP_FINE_FX[3:0] =0xa */ 363 {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0}, 364 /* DFE_EN and Dis Update control from pin disable */ 365 {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0}, 366 /* FFE Force FFE_REs and cap settings for Gen1 */ 367 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 368 /* FFE Force FFE_REs and cap settings for Gen2 */ 369 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0}, 370 /* FE Force FFE_REs=4 and cap settings for Gen3n */ 371 {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 372 /* Set DFE Gen 3 Resolution to 3 */ 373 {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0}, 374 }; 375 376 struct op_params sgmii_electrical_config_serdes_rev1_params[] = { 377 /* 378 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G), 379 * wait_time, num_of_loops 380 */ 381 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 382 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0}, 383 /* SQ_THRESH and FFE Setting */ 384 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0}, 385 /* tximpcal_th and rximpcal_th */ 386 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0}, 387 }; 388 389 struct op_params sgmii_electrical_config_serdes_rev2_params[] = { 390 /* 391 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G), 392 * wait_time, num_of_loops 393 */ 394 /* Set Slew_rate, Emph and Amp */ 395 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0}, 396 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 397 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0}, 398 /* DTL_FLOOP_EN */ 399 {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0}, 400 /* G1 FFE Setting Force, RES and CAP */ 401 {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0}, 402 /* tximpcal_th and rximpcal_th */ 403 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0}, 404 }; 405 406 /* 407 * PEX and USB3 408 */ 409 410 /* PEX and USB3 - power up seq for Serdes Rev 1.2 */ 411 struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = { 412 /* 413 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 414 * wait_time, num_of_loops 415 */ 416 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806, 417 {0x4471804, 0x4479804}, 0, 0}, 418 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0}, 419 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0}, 420 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0}, 421 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0}, 422 /* Ref clock source select */ 423 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0} 424 }; 425 426 /* PEX and USB3 - power up seq for Serdes Rev 2.1 */ 427 struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = { 428 /* 429 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 430 * wait_time, num_of_loops 431 */ 432 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806, 433 {0x4471804, 0x4479804}, 0, 0}, 434 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0}, 435 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0}, 436 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0}, 437 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0}, 438 {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0}, 439 /* Ref clock source select */ 440 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0} 441 }; 442 443 /* PEX and USB3 - speed config seq */ 444 struct op_params pex_and_usb3_speed_config_params[] = { 445 /* 446 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 447 * wait_time, num_of_loops 448 */ 449 /* Maximal PHY Generation Setting */ 450 {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400}, 451 0, 0}, 452 }; 453 454 struct op_params usb3_electrical_config_serdes_rev1_params[] = { 455 /* Spread Spectrum Clock Enable */ 456 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0}, 457 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */ 458 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0}, 459 /* tximpcal_th and rximpcal_th */ 460 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0}, 461 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 462 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 463 /* FFE Setting Force, RES and CAP */ 464 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0}, 465 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */ 466 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0}, 467 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */ 468 {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0}, 469 /* vco_cal_vth_sel */ 470 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0}, 471 }; 472 473 struct op_params usb3_electrical_config_serdes_rev2_params[] = { 474 /* Spread Spectrum Clock Enable */ 475 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0}, 476 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */ 477 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0}, 478 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 479 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 480 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */ 481 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0}, 482 /* vco_cal_vth_sel */ 483 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0}, 484 /* Spread Spectrum Clock Enable */ 485 {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0}, 486 }; 487 488 /* PEX and USB3 - TX config seq */ 489 490 /* 491 * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run 492 * one by one on the lane. 493 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run 494 * by setting each sequence for all 4 lanes. 495 */ 496 struct op_params pex_and_usb3_tx_config_params1[] = { 497 /* 498 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 499 * wait_time, num_of_loops 500 */ 501 {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0}, 502 /* 10ms delay */ 503 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}, 504 /* os_ph_offset_force (align 90) */ 505 {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0}, 506 /* Set os_ph_valid */ 507 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0}, 508 /* Unset os_ph_valid */ 509 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0}, 510 }; 511 512 struct op_params pex_and_usb3_tx_config_params2[] = { 513 /* 514 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 515 * wait_time, num_of_loops 516 */ 517 /* Sft Reset pulse */ 518 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0}, 519 }; 520 521 struct op_params pex_and_usb3_tx_config_params3[] = { 522 /* 523 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 524 * wait_time, num_of_loops 525 */ 526 /* Sft Reset pulse */ 527 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0}, 528 /* 10ms delay */ 529 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0} 530 }; 531 532 /* PEX by 4 config seq */ 533 struct op_params pex_by4_config_params[] = { 534 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ 535 {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, 536 /* Lane Alignement enable */ 537 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, 538 /* Max PLL phy config */ 539 {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, 540 0, 0}, 541 /* Max PLL pipe config */ 542 {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0}, 543 }; 544 545 /* USB3 device donfig seq */ 546 struct op_params usb3_device_config_params[] = { 547 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ 548 {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0} 549 }; 550 551 /* PEX - electrical configuration seq Rev 1.2 */ 552 struct op_params pex_electrical_config_serdes_rev1_params[] = { 553 /* 554 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 555 * num_of_loops 556 */ 557 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */ 558 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0}, 559 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 560 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 561 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 562 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 563 /* CFG_DFE_EN_SEL */ 564 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0}, 565 /* FFE Setting Force, RES and CAP */ 566 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0}, 567 /* tximpcal_th and rximpcal_th */ 568 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 569 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */ 570 {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0}, 571 }; 572 573 /* PEX - electrical configuration seq Rev 2.1 */ 574 struct op_params pex_electrical_config_serdes_rev2_params[] = { 575 /* 576 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 577 * num_of_loops 578 */ 579 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */ 580 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0}, 581 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 582 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 583 /* G1 FFE Setting Force, RES and CAP */ 584 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 585 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 586 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 587 /* G2 FFE Setting Force, RES and CAP */ 588 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0}, 589 /* G2 DFE resolution value */ 590 {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0}, 591 /* DFE resolution force */ 592 {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0}, 593 /* Tx amplitude for Tx Margin 0 */ 594 {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0}, 595 /* Tx_Emph value for -3.5d_b and -6d_b */ 596 {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0}, 597 /* CFG_DFE_EN_SEL */ 598 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0}, 599 /* tximpcal_th and rximpcal_th */ 600 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 601 }; 602 603 /* PEX - configuration seq for REF_CLOCK_25MHz */ 604 struct op_params pex_config_ref_clock25_m_hz[] = { 605 /* 606 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 607 * num_of_loops 608 */ 609 /* Bits[4:0]=0x2 - REF_FREF_SEL */ 610 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0}, 611 /* Bit[10]=0x1 - REFCLK_SEL */ 612 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0}, 613 /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */ 614 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0}, 615 }; 616 617 /* PEX - configuration seq for REF_CLOCK_40MHz */ 618 struct op_params pex_config_ref_clock40_m_hz[] = { 619 /* 620 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 621 * num_of_loops 622 */ 623 /* Bits[4:0]=0x3 - REF_FREF_SEL */ 624 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0}, 625 /* Bits[10]=0x1 - REFCLK_SEL */ 626 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0}, 627 /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */ 628 {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0}, 629 }; 630 631 /* PEX - configuration seq for REF_CLOCK_100MHz */ 632 struct op_params pex_config_ref_clock100_m_hz[] = { 633 /* 634 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 635 * num_of_loops 636 */ 637 /* Bits[4:0]=0x0 - REF_FREF_SEL */ 638 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0}, 639 /* Bit[10]=0x0 - REFCLK_SEL */ 640 {MISC_REG, 0x800, 0x400, {0x0}, 0, 0}, 641 /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */ 642 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0}, 643 }; 644 645 /* 646 * USB2 647 */ 648 649 struct op_params usb2_power_up_params[] = { 650 /* 651 * unit_base_reg, unit_offset, mask, USB2 data, wait_time, 652 * num_of_loops 653 */ 654 /* Init phy 0 */ 655 {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 656 /* Init phy 1 */ 657 {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 658 /* Init phy 2 */ 659 {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 660 /* Phy offset 0x0 - PLL_CONTROL0 */ 661 {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0}, 662 {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 663 {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 664 {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 665 /* Phy offset 0x1 - PLL_CONTROL1 */ 666 {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0}, 667 /* Phy0 register 3 - TX Channel control 0 */ 668 {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 669 /* Phy0 register 3 - TX Channel control 0 */ 670 {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 671 /* Phy0 register 3 - TX Channel control 0 */ 672 {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 673 /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ 674 {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, 675 /* check REG_SQCAL_DONE is set */ 676 {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, 677 /* check PLL_READY is set */ 678 {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} 679 }; 680 681 /* 682 * QSGMII 683 */ 684 685 /* QSGMII - power up seq */ 686 struct op_params qsgmii_port_power_up_params[] = { 687 /* 688 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 689 * num_of_loops 690 */ 691 /* Connect the QSGMII to Gigabit Ethernet units */ 692 {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0}, 693 /* Power Up */ 694 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0}, 695 /* Unreset */ 696 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0}, 697 /* Phy Selector */ 698 {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0}, 699 /* Ref clock source select */ 700 {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0} 701 }; 702 703 /* QSGMII - speed config seq */ 704 struct op_params qsgmii_port_speed_config_params[] = { 705 /* 706 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 707 * num_of_loops 708 */ 709 /* Baud Rate */ 710 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0}, 711 /* Phy Gen RX and TX */ 712 {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0}, 713 /* Bus Width */ 714 {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0} 715 }; 716 717 /* QSGMII - Select electrical param seq */ 718 struct op_params qsgmii_port_electrical_config_params[] = { 719 /* 720 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 721 * num_of_loops 722 */ 723 /* Slew rate and emphasis */ 724 {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0} 725 }; 726 727 /* QSGMII - TX config seq */ 728 struct op_params qsgmii_port_tx_config_params1[] = { 729 /* 730 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 731 * num_of_loops 732 */ 733 {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0}, 734 /* Sft Reset pulse */ 735 {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0}, 736 /* Sft Reset pulse */ 737 {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0}, 738 /* Lane align */ 739 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0}, 740 /* Power up PLL, RX and TX */ 741 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0}, 742 /* Tx driver output idle */ 743 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0} 744 }; 745 746 struct op_params qsgmii_port_tx_config_params2[] = { 747 /* 748 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 749 * num_of_loops 750 */ 751 /* Wait for PHY power up sequence to finish */ 752 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000}, 753 /* Assert Rx Init and Tx driver output valid */ 754 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0}, 755 /* Wait for PHY power up sequence to finish */ 756 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000}, 757 /* De-assert Rx Init */ 758 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0} 759 }; 760 761 /* SERDES_POWER_DOWN */ 762 struct op_params serdes_power_down_params[] = { 763 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)}, 764 0, 0}, 765 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0} 766 }; 767 768 /* 769 * hws_ctrl_serdes_rev_get 770 * 771 * DESCRIPTION: Get the Serdes revision number 772 * 773 * INPUT: config_field - Field description enum 774 * 775 * OUTPUT: None 776 * 777 * RETURN: 778 * 8bit Serdes revision number 779 */ 780 u8 hws_ctrl_serdes_rev_get(void) 781 { 782 #ifdef CONFIG_ARMADA_38X 783 /* for A38x-Z1 */ 784 if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID) 785 return MV_SERDES_REV_1_2; 786 #endif 787 788 /* for A39x-Z1, A38x-A0 */ 789 return MV_SERDES_REV_2_1; 790 } 791 792 u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id, 793 enum serdes_mode serdes_mode) 794 { 795 u32 test_result = 0; 796 u8 serd_max_num, unit_numb; 797 enum unit_id unit_id; 798 799 if (serdes_type > RXAUI) { 800 printf("%s: Warning: Wrong serdes type %s serdes#%d\n", 801 __func__, serdes_type_to_string[serdes_type], serdes_id); 802 return MV_FAIL; 803 } 804 805 unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id; 806 unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num; 807 serd_max_num = sys_env_unit_max_num_get(unit_id); 808 809 /* if didn't exceed amount of required Serdes lanes for current type */ 810 if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) { 811 /* update amount of required Serdes lanes for current type */ 812 serdes_lane_in_use_count[unit_id][unit_numb]--; 813 814 /* 815 * If reached the exact amount of required Serdes lanes for 816 * current type 817 */ 818 if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) { 819 if (((serdes_type <= PEX3)) && 820 ((serdes_mode == PEX_END_POINT_X4) || 821 (serdes_mode == PEX_ROOT_COMPLEX_X4))) { 822 /* PCiex4 uses 2 SerDes */ 823 serdes_unit_count[PEX_UNIT_ID] += 2; 824 } else { 825 serdes_unit_count[unit_id]++; 826 } 827 828 /* test SoC unit count limitation */ 829 if (serdes_unit_count[unit_id] > serd_max_num) { 830 test_result = WRONG_NUMBER_OF_UNITS; 831 } else if (unit_numb >= serd_max_num) { 832 /* test SoC unit number limitation */ 833 test_result = UNIT_NUMBER_VIOLATION; 834 } 835 } 836 } else { 837 test_result = SERDES_ALREADY_IN_USE; 838 } 839 840 if (test_result == SERDES_ALREADY_IN_USE) { 841 printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n", 842 __func__, serdes_id, 843 serdes_type_to_string[serdes_type]); 844 return MV_FAIL; 845 } else if (test_result == WRONG_NUMBER_OF_UNITS) { 846 printf("%s: Warning: serdes lane %d is set to type %s.\n", 847 __func__, serdes_id, 848 serdes_type_to_string[serdes_type]); 849 printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n", 850 __func__, serd_max_num); 851 return MV_FAIL; 852 } else if (test_result == UNIT_NUMBER_VIOLATION) { 853 printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n", 854 __func__, serdes_id, 855 serdes_type_to_string[serdes_type], 856 serd_max_num); 857 return MV_FAIL; 858 } 859 860 return MV_OK; 861 } 862 863 void hws_serdes_xaui_topology_verify(void) 864 { 865 /* 866 * If XAUI is in use - serdes_lane_in_use_count has to be = 0; 867 * if it is not in use hast be = 4 868 */ 869 if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) && 870 (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) { 871 printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n", 872 __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]); 873 printf("%s: XAUI has to be defined on 4 lanes\n", __func__); 874 } 875 876 /* 877 * If RXAUI is in use - serdes_lane_in_use_count has to be = 0; 878 * if it is not in use hast be = 2 879 */ 880 if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) && 881 (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) { 882 printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n", 883 __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]); 884 printf("%s: RXAUI has to be defined on 2 lanes\n", __func__); 885 } 886 } 887 888 int hws_serdes_seq_db_init(void) 889 { 890 u8 serdes_rev = hws_ctrl_serdes_rev_get(); 891 892 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n"); 893 894 if (serdes_rev == MV_SERDES_REV_NA) { 895 printf("hws_serdes_seq_db_init: serdes revision number is not supported\n"); 896 return MV_NOT_SUPPORTED; 897 } 898 899 /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */ 900 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr = 901 sata_port0_power_up_params; 902 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size = 903 sizeof(sata_port0_power_up_params) / sizeof(struct op_params); 904 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA; 905 906 /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */ 907 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr = 908 sata_port1_power_up_params; 909 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size = 910 sizeof(sata_port1_power_up_params) / sizeof(struct op_params); 911 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA; 912 913 /* SATA_POWER_UP_SEQ sequence init */ 914 serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr = 915 sata_and_sgmii_power_up_params; 916 serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size = 917 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params); 918 serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA; 919 920 /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */ 921 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr = 922 sata_and_sgmii_speed_config_params; 923 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size = 924 sizeof(sata_and_sgmii_speed_config_params) / 925 sizeof(struct op_params); 926 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 927 928 /* SATA_3_SPEED_CONFIG_SEQ sequence init */ 929 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr = 930 sata_and_sgmii_speed_config_params; 931 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size = 932 sizeof(sata_and_sgmii_speed_config_params) / 933 sizeof(struct op_params); 934 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 935 936 /* SATA_6_SPEED_CONFIG_SEQ sequence init */ 937 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr = 938 sata_and_sgmii_speed_config_params; 939 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size = 940 sizeof(sata_and_sgmii_speed_config_params) / 941 sizeof(struct op_params); 942 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 943 944 /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */ 945 if (serdes_rev == MV_SERDES_REV_1_2) { 946 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 947 sata_electrical_config_serdes_rev1_params; 948 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 949 sizeof(sata_electrical_config_serdes_rev1_params) / 950 sizeof(struct op_params); 951 } else { 952 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 953 sata_electrical_config_serdes_rev2_params; 954 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 955 sizeof(sata_electrical_config_serdes_rev2_params) / 956 sizeof(struct op_params); 957 } 958 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA; 959 960 /* SATA_TX_CONFIG_SEQ sequence init */ 961 serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr = 962 sata_and_sgmii_tx_config_params1; 963 serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size = 964 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params); 965 serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA; 966 967 /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */ 968 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr = 969 sata_port0_tx_config_params; 970 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size = 971 sizeof(sata_port0_tx_config_params) / sizeof(struct op_params); 972 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA; 973 974 /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */ 975 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr = 976 sata_port1_tx_config_params; 977 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size = 978 sizeof(sata_port1_tx_config_params) / sizeof(struct op_params); 979 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA; 980 981 /* SATA_TX_CONFIG_SEQ2 sequence init */ 982 if (serdes_rev == MV_SERDES_REV_1_2) { 983 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr = 984 sata_and_sgmii_tx_config_serdes_rev1_params2; 985 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size = 986 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) / 987 sizeof(struct op_params); 988 } else { 989 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr = 990 sata_and_sgmii_tx_config_serdes_rev2_params2; 991 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size = 992 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) / 993 sizeof(struct op_params); 994 } 995 serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA; 996 997 /* SGMII_POWER_UP_SEQ sequence init */ 998 serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr = 999 sata_and_sgmii_power_up_params; 1000 serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size = 1001 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params); 1002 serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII; 1003 1004 /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */ 1005 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr = 1006 sata_and_sgmii_speed_config_params; 1007 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size = 1008 sizeof(sata_and_sgmii_speed_config_params) / 1009 sizeof(struct op_params); 1010 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII; 1011 1012 /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */ 1013 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr = 1014 sata_and_sgmii_speed_config_params; 1015 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size = 1016 sizeof(sata_and_sgmii_speed_config_params) / 1017 sizeof(struct op_params); 1018 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125; 1019 1020 /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1021 if (serdes_rev == MV_SERDES_REV_1_2) { 1022 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1023 sgmii_electrical_config_serdes_rev1_params; 1024 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1025 sizeof(sgmii_electrical_config_serdes_rev1_params) / 1026 sizeof(struct op_params); 1027 } else { 1028 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1029 sgmii_electrical_config_serdes_rev2_params; 1030 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1031 sizeof(sgmii_electrical_config_serdes_rev2_params) / 1032 sizeof(struct op_params); 1033 } 1034 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII; 1035 1036 /* SGMII_TX_CONFIG_SEQ sequence init */ 1037 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr = 1038 sata_and_sgmii_tx_config_params1; 1039 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size = 1040 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params); 1041 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII; 1042 1043 /* SGMII_TX_CONFIG_SEQ sequence init */ 1044 if (serdes_rev == MV_SERDES_REV_1_2) { 1045 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr = 1046 sata_and_sgmii_tx_config_serdes_rev1_params2; 1047 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1048 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) / 1049 sizeof(struct op_params); 1050 } else { 1051 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr = 1052 sata_and_sgmii_tx_config_serdes_rev2_params2; 1053 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1054 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) / 1055 sizeof(struct op_params); 1056 } 1057 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII; 1058 1059 /* PEX_POWER_UP_SEQ sequence init */ 1060 if (serdes_rev == MV_SERDES_REV_1_2) { 1061 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr = 1062 pex_and_usb3_power_up_serdes_rev1_params; 1063 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size = 1064 sizeof(pex_and_usb3_power_up_serdes_rev1_params) / 1065 sizeof(struct op_params); 1066 } else { 1067 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr = 1068 pex_and_usb3_power_up_serdes_rev2_params; 1069 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size = 1070 sizeof(pex_and_usb3_power_up_serdes_rev2_params) / 1071 sizeof(struct op_params); 1072 } 1073 serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX; 1074 1075 /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */ 1076 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr = 1077 pex_and_usb3_speed_config_params; 1078 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1079 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1080 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx = 1081 PEXSERDES_SPEED_2_5_GBPS; 1082 1083 /* PEX_5_SPEED_CONFIG_SEQ sequence init */ 1084 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr = 1085 pex_and_usb3_speed_config_params; 1086 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1087 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1088 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx = 1089 PEXSERDES_SPEED_5_GBPS; 1090 1091 /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1092 if (serdes_rev == MV_SERDES_REV_1_2) { 1093 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1094 pex_electrical_config_serdes_rev1_params; 1095 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1096 sizeof(pex_electrical_config_serdes_rev1_params) / 1097 sizeof(struct op_params); 1098 } else { 1099 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1100 pex_electrical_config_serdes_rev2_params; 1101 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1102 sizeof(pex_electrical_config_serdes_rev2_params) / 1103 sizeof(struct op_params); 1104 } 1105 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX; 1106 1107 /* PEX_TX_CONFIG_SEQ1 sequence init */ 1108 serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr = 1109 pex_and_usb3_tx_config_params1; 1110 serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size = 1111 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params); 1112 serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX; 1113 1114 /* PEX_TX_CONFIG_SEQ2 sequence init */ 1115 serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr = 1116 pex_and_usb3_tx_config_params2; 1117 serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size = 1118 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params); 1119 serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX; 1120 1121 /* PEX_TX_CONFIG_SEQ3 sequence init */ 1122 serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr = 1123 pex_and_usb3_tx_config_params3; 1124 serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size = 1125 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params); 1126 serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX; 1127 1128 /* PEX_BY_4_CONFIG_SEQ sequence init */ 1129 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr = 1130 pex_by4_config_params; 1131 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size = 1132 sizeof(pex_by4_config_params) / sizeof(struct op_params); 1133 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX; 1134 1135 /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */ 1136 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr = 1137 pex_config_ref_clock25_m_hz; 1138 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size = 1139 sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params); 1140 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX; 1141 1142 /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */ 1143 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr = 1144 pex_config_ref_clock40_m_hz; 1145 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size = 1146 sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params); 1147 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX; 1148 1149 /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */ 1150 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr = 1151 pex_config_ref_clock100_m_hz; 1152 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size = 1153 sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params); 1154 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX; 1155 1156 /* USB3_POWER_UP_SEQ sequence init */ 1157 if (serdes_rev == MV_SERDES_REV_1_2) { 1158 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr = 1159 pex_and_usb3_power_up_serdes_rev1_params; 1160 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size = 1161 sizeof(pex_and_usb3_power_up_serdes_rev1_params) / 1162 sizeof(struct op_params); 1163 } else { 1164 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr = 1165 pex_and_usb3_power_up_serdes_rev2_params; 1166 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size = 1167 sizeof(pex_and_usb3_power_up_serdes_rev2_params) / 1168 sizeof(struct op_params); 1169 } 1170 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3; 1171 1172 /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */ 1173 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr = 1174 pex_and_usb3_speed_config_params; 1175 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size = 1176 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1177 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx = 1178 USB3SERDES_SPEED_5_GBPS_HOST; 1179 1180 /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */ 1181 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr = 1182 pex_and_usb3_speed_config_params; 1183 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size = 1184 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1185 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx = 1186 USB3SERDES_SPEED_5_GBPS_DEVICE; 1187 1188 /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1189 if (serdes_rev == MV_SERDES_REV_1_2) { 1190 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1191 usb3_electrical_config_serdes_rev1_params; 1192 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1193 sizeof(usb3_electrical_config_serdes_rev1_params) / 1194 sizeof(struct op_params); 1195 } else { 1196 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1197 usb3_electrical_config_serdes_rev2_params; 1198 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1199 sizeof(usb3_electrical_config_serdes_rev2_params) / 1200 sizeof(struct op_params); 1201 } 1202 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3; 1203 1204 /* USB3_TX_CONFIG_SEQ sequence init */ 1205 serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr = 1206 pex_and_usb3_tx_config_params1; 1207 serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size = 1208 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params); 1209 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3; 1210 1211 /* USB3_TX_CONFIG_SEQ sequence init */ 1212 serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr = 1213 pex_and_usb3_tx_config_params2; 1214 serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size = 1215 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params); 1216 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3; 1217 1218 /* USB3_TX_CONFIG_SEQ sequence init */ 1219 serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr = 1220 pex_and_usb3_tx_config_params3; 1221 serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size = 1222 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params); 1223 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3; 1224 1225 /* USB2_POWER_UP_SEQ sequence init */ 1226 serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params; 1227 serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size = 1228 sizeof(usb2_power_up_params) / sizeof(struct op_params); 1229 serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0; 1230 1231 /* USB3_DEVICE_CONFIG_SEQ sequence init */ 1232 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr = 1233 usb3_device_config_params; 1234 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size = 1235 sizeof(usb3_device_config_params) / sizeof(struct op_params); 1236 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */ 1237 1238 /* SERDES_POWER_DOWN_SEQ sequence init */ 1239 serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr = 1240 serdes_power_down_params; 1241 serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size = 1242 sizeof(serdes_power_down_params) / 1243 sizeof(struct op_params); 1244 serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL; 1245 1246 if (serdes_rev == MV_SERDES_REV_2_1) { 1247 /* QSGMII_POWER_UP_SEQ sequence init */ 1248 serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr = 1249 qsgmii_port_power_up_params; 1250 serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size = 1251 sizeof(qsgmii_port_power_up_params) / 1252 sizeof(struct op_params); 1253 serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx = 1254 QSGMII_SEQ_IDX; 1255 1256 /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */ 1257 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr = 1258 qsgmii_port_speed_config_params; 1259 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1260 sizeof(qsgmii_port_speed_config_params) / 1261 sizeof(struct op_params); 1262 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx = 1263 QSGMII_SEQ_IDX; 1264 1265 /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1266 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1267 qsgmii_port_electrical_config_params; 1268 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1269 sizeof(qsgmii_port_electrical_config_params) / 1270 sizeof(struct op_params); 1271 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = 1272 QSGMII_SEQ_IDX; 1273 1274 /* QSGMII_TX_CONFIG_SEQ sequence init */ 1275 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr = 1276 qsgmii_port_tx_config_params1; 1277 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size = 1278 sizeof(qsgmii_port_tx_config_params1) / 1279 sizeof(struct op_params); 1280 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx = 1281 QSGMII_SEQ_IDX; 1282 1283 /* QSGMII_TX_CONFIG_SEQ sequence init */ 1284 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr = 1285 qsgmii_port_tx_config_params2; 1286 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1287 sizeof(qsgmii_port_tx_config_params2) / 1288 sizeof(struct op_params); 1289 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx = 1290 QSGMII_SEQ_IDX; 1291 } 1292 1293 return MV_OK; 1294 } 1295 1296 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, 1297 enum serdes_speed baud_rate) 1298 { 1299 enum serdes_seq seq_id = SERDES_LAST_SEQ; 1300 1301 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n"); 1302 switch (serdes_type) { 1303 case PEX0: 1304 case PEX1: 1305 case PEX2: 1306 case PEX3: 1307 if (baud_rate == SERDES_SPEED_2_5_GBPS) 1308 seq_id = PEX_2_5_SPEED_CONFIG_SEQ; 1309 else if (baud_rate == SERDES_SPEED_5_GBPS) 1310 seq_id = PEX_5_SPEED_CONFIG_SEQ; 1311 break; 1312 case USB3_HOST0: 1313 case USB3_HOST1: 1314 if (baud_rate == SERDES_SPEED_5_GBPS) 1315 seq_id = USB3_HOST_SPEED_CONFIG_SEQ; 1316 break; 1317 case USB3_DEVICE: 1318 if (baud_rate == SERDES_SPEED_5_GBPS) 1319 seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ; 1320 break; 1321 case SATA0: 1322 case SATA1: 1323 case SATA2: 1324 case SATA3: 1325 if (baud_rate == SERDES_SPEED_1_5_GBPS) 1326 seq_id = SATA_1_5_SPEED_CONFIG_SEQ; 1327 else if (baud_rate == SERDES_SPEED_3_GBPS) 1328 seq_id = SATA_3_SPEED_CONFIG_SEQ; 1329 else if (baud_rate == SERDES_SPEED_6_GBPS) 1330 seq_id = SATA_6_SPEED_CONFIG_SEQ; 1331 break; 1332 case SGMII0: 1333 case SGMII1: 1334 case SGMII2: 1335 #ifdef CONFIG_ARMADA_39X 1336 case SGMII3: 1337 #endif 1338 if (baud_rate == SERDES_SPEED_1_25_GBPS) 1339 seq_id = SGMII_1_25_SPEED_CONFIG_SEQ; 1340 else if (baud_rate == SERDES_SPEED_3_125_GBPS) 1341 seq_id = SGMII_3_125_SPEED_CONFIG_SEQ; 1342 break; 1343 case QSGMII: 1344 seq_id = QSGMII_5_SPEED_CONFIG_SEQ; 1345 break; 1346 #ifdef CONFIG_ARMADA_39X 1347 case XAUI: 1348 seq_id = XAUI_3_125_SPEED_CONFIG_SEQ; 1349 break; 1350 case RXAUI: 1351 seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ; 1352 break; 1353 #endif 1354 default: 1355 return SERDES_LAST_SEQ; 1356 } 1357 1358 return seq_id; 1359 } 1360 1361 static void print_topology_details(const struct serdes_map *serdes_map, 1362 u8 count) 1363 { 1364 u32 lane_num; 1365 1366 DEBUG_INIT_S("board SerDes lanes topology details:\n"); 1367 1368 DEBUG_INIT_S(" | Lane # | Speed | Type |\n"); 1369 DEBUG_INIT_S(" --------------------------------\n"); 1370 for (lane_num = 0; lane_num < count; lane_num++) { 1371 if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES) 1372 continue; 1373 DEBUG_INIT_S(" | "); 1374 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1); 1375 DEBUG_INIT_S(" | "); 1376 DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2); 1377 DEBUG_INIT_S(" | "); 1378 DEBUG_INIT_S((char *) 1379 serdes_type_to_string[serdes_map[lane_num]. 1380 serdes_type]); 1381 DEBUG_INIT_S("\t|\n"); 1382 } 1383 DEBUG_INIT_S(" --------------------------------\n"); 1384 } 1385 1386 int hws_pre_serdes_init_config(void) 1387 { 1388 u32 data; 1389 1390 /* 1391 * Configure Core PLL 1392 */ 1393 /* 1394 * set PLL parameters 1395 * bits[2:0] =0x3 (Core-PLL Kdiv) 1396 * bits[20:12]=0x9f (Core-PLL Ndiv) 1397 * bits[24:21]=0x7(Core-PLL VCO Band) 1398 * bits[28:25]=0x1(Core-PLL Rlf) 1399 * bits[31:29]=0x2(Core-PLL charge-pump adjust) 1400 */ 1401 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003); 1402 1403 /* Enable PLL Configuration */ 1404 data = reg_read(CORE_PLL_CONFIG_REG); 1405 data = SET_BIT(data, 9); 1406 reg_write(CORE_PLL_CONFIG_REG, data); 1407 1408 return MV_OK; 1409 } 1410 1411 int serdes_phy_config(void) 1412 { 1413 struct serdes_map *serdes_map; 1414 u8 serdes_count; 1415 1416 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n"); 1417 1418 DEBUG_INIT_S("High speed PHY - Version: "); 1419 DEBUG_INIT_S(SERDES_VERSION); 1420 DEBUG_INIT_S("\n"); 1421 1422 /* Init serdes sequences DB */ 1423 if (hws_serdes_seq_init() != MV_OK) { 1424 printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n"); 1425 return MV_FAIL; 1426 } 1427 1428 /* Board topology load */ 1429 DEBUG_INIT_FULL_S 1430 ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n"); 1431 CHECK_STATUS(hws_board_topology_load(&serdes_map, &serdes_count)); 1432 if (serdes_count > hws_serdes_get_max_lane()) { 1433 printf("Error: too many serdes lanes specified by board\n"); 1434 return MV_FAIL; 1435 } 1436 1437 /* print topology */ 1438 print_topology_details(serdes_map, serdes_count); 1439 CHECK_STATUS(hws_pre_serdes_init_config()); 1440 1441 /* Power-Up sequence */ 1442 DEBUG_INIT_FULL_S 1443 ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n"); 1444 1445 CHECK_STATUS(hws_power_up_serdes_lanes(serdes_map, serdes_count)); 1446 1447 DEBUG_INIT_FULL_S 1448 ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n"); 1449 1450 DEBUG_INIT_S(ENDED_OK); 1451 1452 return MV_OK; 1453 } 1454 1455 int serdes_polarity_config(u32 serdes_num, int is_rx) 1456 { 1457 u32 data; 1458 u32 reg_addr; 1459 u8 bit_off = (is_rx) ? 11 : 10; 1460 1461 reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG; 1462 data = reg_read(reg_addr); 1463 data = SET_BIT(data, bit_off); 1464 reg_write(reg_addr, data); 1465 1466 return MV_OK; 1467 } 1468 1469 int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count) 1470 { 1471 u32 serdes_id, serdes_lane_num; 1472 enum ref_clock ref_clock; 1473 enum serdes_type serdes_type; 1474 enum serdes_speed serdes_speed; 1475 enum serdes_mode serdes_mode; 1476 int serdes_rx_polarity_swap; 1477 int serdes_tx_polarity_swap; 1478 int is_pex_enabled = 0; 1479 1480 /* 1481 * is_pex_enabled: 1482 * Flag which indicates that one of the Serdes is of PEX. 1483 * In this case, PEX unit will be initialized after Serdes power-up 1484 */ 1485 1486 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n"); 1487 1488 /* COMMON PHYS SELECTORS register configuration */ 1489 DEBUG_INIT_FULL_S 1490 ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n"); 1491 CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_map, count)); 1492 1493 /* per Serdes Power Up */ 1494 for (serdes_id = 0; serdes_id < count; serdes_id++) { 1495 DEBUG_INIT_FULL_S 1496 ("calling serdes_power_up_ctrl: serdes lane number "); 1497 DEBUG_INIT_FULL_D_10(serdes_lane_num, 1); 1498 DEBUG_INIT_FULL_S("\n"); 1499 1500 serdes_lane_num = hws_get_physical_serdes_num(serdes_id); 1501 serdes_type = serdes_map[serdes_id].serdes_type; 1502 serdes_speed = serdes_map[serdes_id].serdes_speed; 1503 serdes_mode = serdes_map[serdes_id].serdes_mode; 1504 serdes_rx_polarity_swap = serdes_map[serdes_id].swap_rx; 1505 serdes_tx_polarity_swap = serdes_map[serdes_id].swap_tx; 1506 1507 /* serdes lane is not in use */ 1508 if (serdes_type == DEFAULT_SERDES) 1509 continue; 1510 else if (serdes_type <= PEX3) /* PEX type */ 1511 is_pex_enabled = 1; 1512 1513 ref_clock = hws_serdes_get_ref_clock_val(serdes_type); 1514 if (ref_clock == REF_CLOCK_UNSUPPORTED) { 1515 DEBUG_INIT_S 1516 ("hws_power_up_serdes_lanes: unsupported ref clock\n"); 1517 return MV_NOT_SUPPORTED; 1518 } 1519 CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num, 1520 1, 1521 serdes_type, 1522 serdes_speed, 1523 serdes_mode, ref_clock)); 1524 1525 /* RX Polarity config */ 1526 if (serdes_rx_polarity_swap) 1527 CHECK_STATUS(serdes_polarity_config 1528 (serdes_lane_num, 1)); 1529 1530 /* TX Polarity config */ 1531 if (serdes_tx_polarity_swap) 1532 CHECK_STATUS(serdes_polarity_config 1533 (serdes_lane_num, 0)); 1534 } 1535 1536 if (is_pex_enabled) { 1537 /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode. 1538 After finish the Power_up sequence for all lanes, 1539 the lanes should be released from reset state. */ 1540 CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count)); 1541 1542 /* PEX configuration */ 1543 CHECK_STATUS(hws_pex_config(serdes_map, count)); 1544 } 1545 1546 /* USB2 configuration */ 1547 DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n"); 1548 CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ)); 1549 1550 DEBUG_INIT_FULL_S 1551 ("### hws_power_up_serdes_lanes ended successfully ###\n"); 1552 1553 return MV_OK; 1554 } 1555 1556 int ctrl_high_speed_serdes_phy_config(void) 1557 { 1558 return hws_ctrl_high_speed_serdes_phy_config(); 1559 } 1560 1561 static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type) 1562 { 1563 u32 reg_data; 1564 1565 /* WA for A380 Z1 relevant for lanes 3,4,5 only */ 1566 if (serdes_num >= 3) { 1567 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); 1568 /* set delay on pipe - 1569 * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1. 1570 * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0. 1571 * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1. 1572 * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0. 1573 * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1. 1574 * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0. 1575 */ 1576 if (serdes_type == PEX) 1577 reg_data |= 1 << (7 + (serdes_num - 3)); 1578 if (serdes_type == USB3) { 1579 /* USB3 */ 1580 reg_data &= ~(1 << (7 + (serdes_num - 3))); 1581 } 1582 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); 1583 } 1584 1585 return MV_OK; 1586 } 1587 1588 /* 1589 * hws_serdes_pex_ref_clock_satr_get - 1590 * 1591 * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG 1592 * and check: 1593 * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31] 1594 * for PEX#3. 1595 * If bit=0 --> REF_CLOCK_100MHz 1596 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0 1597 * --> REF_CLOCK_25MHz 1598 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1 1599 * --> REF_CLOCK_40MHz 1600 * 1601 * INPUT: serdes_type - Type of Serdes 1602 * 1603 * OUTPUT: pex_satr - Return the REF_CLOCK value: 1604 * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz 1605 * 1606 * RETURNS: MV_OK - for success 1607 * MV_BAD_PARAM - for fail 1608 */ 1609 int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr) 1610 { 1611 u32 data, reg_satr1; 1612 1613 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); 1614 1615 switch (serdes_type) { 1616 case PEX0: 1617 data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1); 1618 break; 1619 case PEX1: 1620 data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1); 1621 break; 1622 case PEX2: 1623 data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1); 1624 break; 1625 case PEX3: 1626 data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1); 1627 break; 1628 default: 1629 printf("%s: Error: SerDes type %d is not supported\n", 1630 __func__, serdes_type); 1631 return MV_BAD_PARAM; 1632 } 1633 1634 *pex_satr = data; 1635 1636 return MV_OK; 1637 } 1638 1639 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type) 1640 { 1641 u32 pex_satr; 1642 enum ref_clock ref_clock; 1643 1644 DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n"); 1645 1646 if (serdes_type >= LAST_SERDES_TYPE) 1647 return REF_CLOCK_UNSUPPORTED; 1648 1649 /* read ref clock from S@R */ 1650 ref_clock = hws_serdes_silicon_ref_clock_get(); 1651 1652 if (serdes_type > PEX3) { 1653 /* for all Serdes types but PCIe */ 1654 return ref_clock; 1655 } 1656 1657 /* for PCIe, need also to check PCIe S@R */ 1658 CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get 1659 (serdes_type, &pex_satr)); 1660 1661 if (pex_satr == 0) { 1662 return REF_CLOCK_100MHZ; 1663 } else if (pex_satr == 1) { 1664 /* value of 1 means we can use ref clock from SoC (as other Serdes types) */ 1665 return ref_clock; 1666 } else { 1667 printf 1668 ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n", 1669 __func__, serdes_type); 1670 return REF_CLOCK_UNSUPPORTED; 1671 } 1672 } 1673 1674 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, 1675 enum serdes_type serdes_type, 1676 enum serdes_speed baud_rate, 1677 enum serdes_mode serdes_mode, enum ref_clock ref_clock) 1678 { 1679 u32 sata_idx, pex_idx, sata_port; 1680 enum serdes_seq speed_seq_id; 1681 u32 reg_data; 1682 int is_pex_by1; 1683 1684 DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n"); 1685 1686 if (serdes_power_up == 1) { /* Serdes power up */ 1687 DEBUG_INIT_FULL_S 1688 ("serdes_power_up_ctrl: executing power up.. "); 1689 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2); 1690 DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2); 1691 1692 DEBUG_INIT_FULL_S("Going access 1"); 1693 1694 /* Getting the Speed Select sequence id */ 1695 speed_seq_id = 1696 serdes_type_and_speed_to_speed_seq(serdes_type, 1697 baud_rate); 1698 if (speed_seq_id == SERDES_LAST_SEQ) { 1699 printf 1700 ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n", 1701 serdes_type, baud_rate); 1702 1703 return MV_BAD_PARAM; 1704 } 1705 1706 /* Executing power up, ref clock set, speed config and TX config */ 1707 switch (serdes_type) { 1708 case PEX0: 1709 case PEX1: 1710 case PEX2: 1711 case PEX3: 1712 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) { 1713 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a 1714 (serdes_num, PEX)); 1715 } 1716 1717 is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) || 1718 (serdes_mode == PEX_END_POINT_X1); 1719 pex_idx = serdes_type - PEX0; 1720 1721 if ((is_pex_by1 == 1) || (serdes_type == PEX0)) { 1722 /* For PEX by 4, init only the PEX 0 */ 1723 reg_data = reg_read(SOC_CONTROL_REG1); 1724 if (is_pex_by1 == 1) 1725 reg_data |= 0x4000; 1726 else 1727 reg_data &= ~0x4000; 1728 reg_write(SOC_CONTROL_REG1, reg_data); 1729 1730 reg_data = 1731 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1732 0x6c)); 1733 reg_data &= ~0x3f0; 1734 if (is_pex_by1 == 1) 1735 reg_data |= 0x10; 1736 else 1737 reg_data |= 0x40; 1738 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), 1739 reg_data); 1740 1741 reg_data = 1742 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1743 0x6c)); 1744 reg_data &= ~0xf; 1745 reg_data |= 0x2; 1746 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), 1747 reg_data); 1748 1749 reg_data = 1750 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1751 0x70)); 1752 reg_data &= ~0x40; 1753 reg_data |= 0x40; 1754 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), 1755 reg_data); 1756 } 1757 1758 CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ)); 1759 if (is_pex_by1 == 0) { 1760 /* 1761 * for PEX by 4 - use the PEX index as the 1762 * seq array index 1763 */ 1764 serdes_seq_db[PEX_BY_4_CONFIG_SEQ]. 1765 data_arr_idx = pex_idx; 1766 CHECK_STATUS(mv_seq_exec 1767 (serdes_num, PEX_BY_4_CONFIG_SEQ)); 1768 } 1769 1770 CHECK_STATUS(hws_ref_clock_set 1771 (serdes_num, serdes_type, ref_clock)); 1772 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1773 CHECK_STATUS(mv_seq_exec 1774 (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ)); 1775 1776 if (is_pex_by1 == 1) { 1777 CHECK_STATUS(mv_seq_exec 1778 (serdes_num, PEX_TX_CONFIG_SEQ2)); 1779 CHECK_STATUS(mv_seq_exec 1780 (serdes_num, PEX_TX_CONFIG_SEQ3)); 1781 CHECK_STATUS(mv_seq_exec 1782 (serdes_num, PEX_TX_CONFIG_SEQ1)); 1783 } 1784 udelay(20); 1785 1786 break; 1787 case USB3_HOST0: 1788 case USB3_HOST1: 1789 case USB3_DEVICE: 1790 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) { 1791 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a 1792 (serdes_num, USB3)); 1793 } 1794 CHECK_STATUS(mv_seq_exec 1795 (serdes_num, USB3_POWER_UP_SEQ)); 1796 CHECK_STATUS(hws_ref_clock_set 1797 (serdes_num, serdes_type, ref_clock)); 1798 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1799 if (serdes_type == USB3_DEVICE) { 1800 CHECK_STATUS(mv_seq_exec 1801 (serdes_num, 1802 USB3_DEVICE_CONFIG_SEQ)); 1803 } 1804 CHECK_STATUS(mv_seq_exec 1805 (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ)); 1806 CHECK_STATUS(mv_seq_exec 1807 (serdes_num, USB3_TX_CONFIG_SEQ1)); 1808 CHECK_STATUS(mv_seq_exec 1809 (serdes_num, USB3_TX_CONFIG_SEQ2)); 1810 CHECK_STATUS(mv_seq_exec 1811 (serdes_num, USB3_TX_CONFIG_SEQ3)); 1812 1813 udelay(10000); 1814 break; 1815 case SATA0: 1816 case SATA1: 1817 case SATA2: 1818 case SATA3: 1819 sata_idx = ((serdes_type == SATA0) || 1820 (serdes_type == SATA1)) ? 0 : 1; 1821 sata_port = ((serdes_type == SATA0) || 1822 (serdes_type == SATA2)) ? 0 : 1; 1823 1824 CHECK_STATUS(mv_seq_exec 1825 (sata_idx, (sata_port == 0) ? 1826 SATA_PORT_0_ONLY_POWER_UP_SEQ : 1827 SATA_PORT_1_ONLY_POWER_UP_SEQ)); 1828 CHECK_STATUS(mv_seq_exec 1829 (serdes_num, SATA_POWER_UP_SEQ)); 1830 CHECK_STATUS(hws_ref_clock_set 1831 (serdes_num, serdes_type, ref_clock)); 1832 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1833 CHECK_STATUS(mv_seq_exec 1834 (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ)); 1835 CHECK_STATUS(mv_seq_exec 1836 (serdes_num, SATA_TX_CONFIG_SEQ1)); 1837 CHECK_STATUS(mv_seq_exec 1838 (sata_idx, (sata_port == 0) ? 1839 SATA_PORT_0_ONLY_TX_CONFIG_SEQ : 1840 SATA_PORT_1_ONLY_TX_CONFIG_SEQ)); 1841 CHECK_STATUS(mv_seq_exec 1842 (serdes_num, SATA_TX_CONFIG_SEQ2)); 1843 1844 udelay(10000); 1845 break; 1846 case SGMII0: 1847 case SGMII1: 1848 case SGMII2: 1849 CHECK_STATUS(mv_seq_exec 1850 (serdes_num, SGMII_POWER_UP_SEQ)); 1851 CHECK_STATUS(hws_ref_clock_set 1852 (serdes_num, serdes_type, ref_clock)); 1853 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1854 CHECK_STATUS(mv_seq_exec 1855 (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ)); 1856 CHECK_STATUS(mv_seq_exec 1857 (serdes_num, SGMII_TX_CONFIG_SEQ1)); 1858 CHECK_STATUS(mv_seq_exec 1859 (serdes_num, SGMII_TX_CONFIG_SEQ2)); 1860 1861 /* GBE configuration */ 1862 reg_data = reg_read(GBE_CONFIGURATION_REG); 1863 /* write the SGMII index */ 1864 reg_data |= 0x1 << (serdes_type - SGMII0); 1865 reg_write(GBE_CONFIGURATION_REG, reg_data); 1866 1867 break; 1868 case QSGMII: 1869 if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1) 1870 return MV_NOT_SUPPORTED; 1871 1872 CHECK_STATUS(mv_seq_exec 1873 (serdes_num, QSGMII_POWER_UP_SEQ)); 1874 CHECK_STATUS(hws_ref_clock_set 1875 (serdes_num, serdes_type, ref_clock)); 1876 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1877 CHECK_STATUS(mv_seq_exec 1878 (serdes_num, 1879 QSGMII_ELECTRICAL_CONFIG_SEQ)); 1880 CHECK_STATUS(mv_seq_exec 1881 (serdes_num, QSGMII_TX_CONFIG_SEQ1)); 1882 CHECK_STATUS(mv_seq_exec 1883 (serdes_num, QSGMII_TX_CONFIG_SEQ2)); 1884 break; 1885 case SGMII3: 1886 case XAUI: 1887 case RXAUI: 1888 CHECK_STATUS(serdes_power_up_ctrl_ext 1889 (serdes_num, serdes_power_up, serdes_type, 1890 baud_rate, serdes_mode, ref_clock)); 1891 break; 1892 default: 1893 DEBUG_INIT_S 1894 ("serdes_power_up_ctrl: bad serdes_type parameter\n"); 1895 return MV_BAD_PARAM; 1896 } 1897 } else { /* Serdes power down */ 1898 DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. "); 1899 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1); 1900 1901 CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ)); 1902 } 1903 1904 DEBUG_INIT_FULL_C( 1905 "serdes_power_up_ctrl ended successfully for serdes ", 1906 serdes_num, 2); 1907 1908 return MV_OK; 1909 } 1910 1911 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count) 1912 { 1913 u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0; 1914 enum serdes_type serdes_type; 1915 enum serdes_mode serdes_mode; 1916 u8 select_bit_off; 1917 int is_pex_x4 = 0; 1918 int updated_topology_print = 0; 1919 1920 DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n"); 1921 DEBUG_INIT_FULL_S 1922 ("Updating the COMMON PHYS SELECTORS register with the serdes types\n"); 1923 1924 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) 1925 select_bit_off = 3; 1926 else 1927 select_bit_off = 4; 1928 1929 /* 1930 * Updating bits 0-17 in the COMMON PHYS SELECTORS register 1931 * according to the serdes types 1932 */ 1933 for (idx = 0; idx < count; idx++) { 1934 serdes_type = serdes_map[idx].serdes_type; 1935 serdes_mode = serdes_map[idx].serdes_mode; 1936 serdes_lane_hw_num = hws_get_physical_serdes_num(idx); 1937 1938 lane_data = 1939 hws_serdes_get_phy_selector_val(serdes_lane_hw_num, 1940 serdes_type); 1941 1942 if (serdes_type == DEFAULT_SERDES) 1943 continue; 1944 1945 if (hws_serdes_topology_verify 1946 (serdes_type, idx, serdes_mode) != MV_OK) { 1947 serdes_map[idx].serdes_type = 1948 DEFAULT_SERDES; 1949 printf("%s: SerDes lane #%d is disabled\n", __func__, 1950 serdes_lane_hw_num); 1951 updated_topology_print = 1; 1952 continue; 1953 } 1954 1955 /* 1956 * Checking if the board topology configuration includes 1957 * PEXx4 - for the next step 1958 */ 1959 if ((serdes_mode == PEX_END_POINT_X4) || 1960 (serdes_mode == PEX_ROOT_COMPLEX_X4)) { 1961 /* update lane data to the 3 next SERDES lanes */ 1962 lane_data = 1963 common_phys_selectors_pex_by4_lanes 1964 [serdes_lane_hw_num]; 1965 if (serdes_type == PEX0) 1966 is_pex_x4 = 1; 1967 } 1968 1969 if (lane_data == NA) { 1970 printf 1971 ("%s: Warning: SerDes lane #%d and type %d are not supported together\n", 1972 __func__, serdes_lane_hw_num, serdes_mode); 1973 serdes_map[idx].serdes_type = DEFAULT_SERDES; 1974 printf("%s: SerDes lane #%d is disabled\n", __func__, 1975 serdes_lane_hw_num); 1976 continue; 1977 } 1978 1979 /* 1980 * Updating the data that will be written to 1981 * COMMON_PHYS_SELECTORS_REG 1982 */ 1983 reg_data |= (lane_data << 1984 (select_bit_off * serdes_lane_hw_num)); 1985 } 1986 1987 /* 1988 * Check that number of used lanes for XAUI and RXAUI 1989 * (if used) is right 1990 */ 1991 hws_serdes_xaui_topology_verify(); 1992 1993 /* Print topology */ 1994 if (updated_topology_print) 1995 print_topology_details(serdes_map, count); 1996 1997 /* 1998 * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS 1999 * register for PEXx4 mode 2000 */ 2001 reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0; 2002 2003 /* Updating the COMMON PHYS SELECTORS register */ 2004 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data); 2005 2006 return MV_OK; 2007 } 2008 2009 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, 2010 enum ref_clock ref_clock) 2011 { 2012 u32 data1 = 0, data2 = 0, data3 = 0, reg_data; 2013 2014 DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n"); 2015 2016 if (hws_is_serdes_active(serdes_num) != 1) { 2017 printf("%s: SerDes lane #%d is not Active\n", __func__, 2018 serdes_num); 2019 return MV_BAD_PARAM; 2020 } 2021 2022 switch (serdes_type) { 2023 case PEX0: 2024 case PEX1: 2025 case PEX2: 2026 case PEX3: 2027 switch (ref_clock) { 2028 case REF_CLOCK_25MHZ: 2029 CHECK_STATUS(mv_seq_exec 2030 (serdes_num, 2031 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ)); 2032 return MV_OK; 2033 case REF_CLOCK_100MHZ: 2034 CHECK_STATUS(mv_seq_exec 2035 (serdes_num, 2036 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ)); 2037 return MV_OK; 2038 #ifdef CONFIG_ARMADA_39X 2039 case REF_CLOCK_40MHZ: 2040 CHECK_STATUS(mv_seq_exec 2041 (serdes_num, 2042 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ)); 2043 return MV_OK; 2044 #endif 2045 default: 2046 printf 2047 ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n", 2048 __func__, ref_clock, serdes_num, serdes_type); 2049 return MV_BAD_PARAM; 2050 } 2051 case USB3_HOST0: 2052 case USB3_HOST1: 2053 case USB3_DEVICE: 2054 if (ref_clock == REF_CLOCK_25MHZ) { 2055 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2; 2056 data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL; 2057 data3 = LANE_CFG4_REG_25MHZ_VAL; 2058 } else if (ref_clock == REF_CLOCK_40MHZ) { 2059 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2060 data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL; 2061 data3 = LANE_CFG4_REG_40MHZ_VAL; 2062 } else { 2063 printf 2064 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2065 serdes_type); 2066 return MV_BAD_PARAM; 2067 } 2068 break; 2069 case SATA0: 2070 case SATA1: 2071 case SATA2: 2072 case SATA3: 2073 case SGMII0: 2074 case SGMII1: 2075 case SGMII2: 2076 case QSGMII: 2077 if (ref_clock == REF_CLOCK_25MHZ) { 2078 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1; 2079 } else if (ref_clock == REF_CLOCK_40MHZ) { 2080 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2081 } else { 2082 printf 2083 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2084 serdes_type); 2085 return MV_BAD_PARAM; 2086 } 2087 break; 2088 #ifdef CONFIG_ARMADA_39X 2089 case SGMII3: 2090 case XAUI: 2091 case RXAUI: 2092 if (ref_clock == REF_CLOCK_25MHZ) { 2093 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1; 2094 } else if (ref_clock == REF_CLOCK_40MHZ) { 2095 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2096 } else { 2097 printf 2098 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2099 serdes_type); 2100 return MV_BAD_PARAM; 2101 } 2102 break; 2103 #endif 2104 default: 2105 DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n"); 2106 return MV_BAD_PARAM; 2107 } 2108 2109 /* 2110 * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and 2111 * offset 2112 */ 2113 reg_data = reg_read(POWER_AND_PLL_CTRL_REG + 2114 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2115 reg_data &= POWER_AND_PLL_CTRL_REG_MASK; 2116 reg_data |= data1; 2117 reg_write(POWER_AND_PLL_CTRL_REG + 2118 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2119 2120 if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) || 2121 (serdes_type == USB3_DEVICE)) { 2122 reg_data = reg_read(GLOBAL_PM_CTRL + 2123 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2124 reg_data &= GLOBAL_PM_CTRL_REG_MASK; 2125 reg_data |= data2; 2126 reg_write(GLOBAL_PM_CTRL + 2127 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2128 2129 reg_data = reg_read(LANE_CFG4_REG + 2130 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2131 reg_data &= LANE_CFG4_REG_MASK; 2132 reg_data |= data3; 2133 reg_write(LANE_CFG4_REG + 2134 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2135 } 2136 2137 return MV_OK; 2138 } 2139 2140 /* 2141 * hws_pex_tx_config_seq - 2142 * 2143 * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode 2144 * INPUT: serdes_map - The board topology map 2145 * OUTPUT: None 2146 * RETURNS: MV_OK - for success 2147 * MV_BAD_PARAM - for fail 2148 */ 2149 int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count) 2150 { 2151 enum serdes_mode serdes_mode; 2152 u32 serdes_lane_id, serdes_lane_hw_num; 2153 2154 DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n"); 2155 2156 /* 2157 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 2158 * configurations should run by setting each sequence for 2159 * all 4 lanes. 2160 */ 2161 2162 /* relese pipe soft reset for all lanes */ 2163 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2164 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2165 serdes_lane_hw_num = 2166 hws_get_physical_serdes_num(serdes_lane_id); 2167 2168 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2169 (serdes_mode == PEX_END_POINT_X4)) { 2170 CHECK_STATUS(mv_seq_exec 2171 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1)); 2172 } 2173 } 2174 2175 /* set phy soft reset for all lanes */ 2176 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2177 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2178 serdes_lane_hw_num = 2179 hws_get_physical_serdes_num(serdes_lane_id); 2180 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2181 (serdes_mode == PEX_END_POINT_X4)) { 2182 CHECK_STATUS(mv_seq_exec 2183 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2)); 2184 } 2185 } 2186 2187 /* set phy soft reset for all lanes */ 2188 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2189 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2190 serdes_lane_hw_num = 2191 hws_get_physical_serdes_num(serdes_lane_id); 2192 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2193 (serdes_mode == PEX_END_POINT_X4)) { 2194 CHECK_STATUS(mv_seq_exec 2195 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3)); 2196 } 2197 } 2198 2199 return MV_OK; 2200 } 2201