1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "high_speed_env_spec.h" 14 #include "sys_env_lib.h" 15 #include "ctrl_pex.h" 16 17 #if defined(CONFIG_ARMADA_38X) 18 #elif defined(CONFIG_ARMADA_39X) 19 #else 20 #error "No device is defined" 21 #endif 22 23 24 /* 25 * serdes_seq_db - holds all serdes sequences, their size and the 26 * relevant index in the data array initialized in serdes_seq_init 27 */ 28 struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ]; 29 30 #define SERDES_VERION "2.0" 31 #define ENDED_OK "High speed PHY - Ended Successfully\n" 32 33 #define LINK_WAIT_CNTR 100 34 #define LINK_WAIT_SLEEP 100 35 36 #define MAX_UNIT_NUMB 4 37 #define TOPOLOGY_TEST_OK 0 38 #define WRONG_NUMBER_OF_UNITS 1 39 #define SERDES_ALREADY_IN_USE 2 40 #define UNIT_NUMBER_VIOLATION 3 41 42 /* 43 * serdes_lane_in_use_count contains the exact amount of serdes lanes 44 * needed per type 45 */ 46 u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = { 47 /* 0 1 2 3 */ 48 { 1, 1, 1, 1 }, /* PEX */ 49 { 1, 1, 1, 1 }, /* ETH_GIG */ 50 { 1, 1, 0, 0 }, /* USB3H */ 51 { 1, 1, 1, 0 }, /* USB3D */ 52 { 1, 1, 1, 1 }, /* SATA */ 53 { 1, 0, 0, 0 }, /* QSGMII */ 54 { 4, 0, 0, 0 }, /* XAUI */ 55 { 2, 0, 0, 0 } /* RXAUI */ 56 }; 57 58 /* 59 * serdes_unit_count count unit number. 60 * (i.e a single XAUI is counted as 1 unit) 61 */ 62 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 }; 63 64 /* Selector mapping for A380-A0 and A390-Z1 */ 65 u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = { 66 /* 0 1 2 3 4 5 6 */ 67 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */ 68 { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */ 69 { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */ 70 { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */ 71 { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */ 72 { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */ 73 { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */ 74 { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */ 75 { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */ 76 { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */ 77 { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */ 78 { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */ 79 { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */ 80 { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */ 81 { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */ 82 #ifdef CONFIG_ARMADA_39X 83 { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */ 84 { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */ 85 { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */ 86 #endif 87 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */ 88 }; 89 90 /* Selector mapping for PEX by 4 confiuration */ 91 u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 }; 92 93 static const char *const serdes_type_to_string[] = { 94 "PCIe0", 95 "PCIe1", 96 "PCIe2", 97 "PCIe3", 98 "SATA0", 99 "SATA1", 100 "SATA2", 101 "SATA3", 102 "SGMII0", 103 "SGMII1", 104 "SGMII2", 105 "QSGMII", 106 "USB3 HOST0", 107 "USB3 HOST1", 108 "USB3 DEVICE", 109 "SGMII3", 110 "XAUI", 111 "RXAUI", 112 "DEFAULT SERDES", 113 "LAST_SERDES_TYPE" 114 }; 115 116 struct serdes_unit_data { 117 u8 serdes_unit_id; 118 u8 serdes_unit_num; 119 }; 120 121 static struct serdes_unit_data serdes_type_to_unit_info[] = { 122 {PEX_UNIT_ID, 0,}, 123 {PEX_UNIT_ID, 1,}, 124 {PEX_UNIT_ID, 2,}, 125 {PEX_UNIT_ID, 3,}, 126 {SATA_UNIT_ID, 0,}, 127 {SATA_UNIT_ID, 1,}, 128 {SATA_UNIT_ID, 2,}, 129 {SATA_UNIT_ID, 3,}, 130 {ETH_GIG_UNIT_ID, 0,}, 131 {ETH_GIG_UNIT_ID, 1,}, 132 {ETH_GIG_UNIT_ID, 2,}, 133 {QSGMII_UNIT_ID, 0,}, 134 {USB3H_UNIT_ID, 0,}, 135 {USB3H_UNIT_ID, 1,}, 136 {USB3D_UNIT_ID, 0,}, 137 {ETH_GIG_UNIT_ID, 3,}, 138 {XAUI_UNIT_ID, 0,}, 139 {RXAUI_UNIT_ID, 0,}, 140 }; 141 142 /* Sequences DB */ 143 144 /* 145 * SATA and SGMII 146 */ 147 148 struct op_params sata_port0_power_up_params[] = { 149 /* 150 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 151 * num_of_loops 152 */ 153 /* Access to reg 0x48(OOB param 1) */ 154 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0}, 155 /* OOB Com_wake and Com_reset spacing upper limit data */ 156 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0}, 157 /* Access to reg 0xa(PHY Control) */ 158 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0}, 159 /* Rx clk and Tx clk select non-inverted mode */ 160 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0}, 161 /* Power Down Sata addr */ 162 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0}, 163 /* Power Down Sata Port 0 */ 164 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0}, 165 }; 166 167 struct op_params sata_port1_power_up_params[] = { 168 /* 169 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 170 * num_of_loops 171 */ 172 /* Access to reg 0x48(OOB param 1) */ 173 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0}, 174 /* OOB Com_wake and Com_reset spacing upper limit data */ 175 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0}, 176 /* Access to reg 0xa(PHY Control) */ 177 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0}, 178 /* Rx clk and Tx clk select non-inverted mode */ 179 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0}, 180 /* Power Down Sata addr */ 181 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0}, 182 /* Power Down Sata Port 1 */ 183 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0}, 184 }; 185 186 /* SATA and SGMII - power up seq */ 187 struct op_params sata_and_sgmii_power_up_params[] = { 188 /* 189 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 190 * wait_time, num_of_loops 191 */ 192 /* Power Up */ 193 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002}, 194 0, 0}, 195 /* Unreset */ 196 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0}, 197 /* Phy Selector */ 198 {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0}, 199 /* Ref clock source select */ 200 {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0} 201 }; 202 203 /* SATA and SGMII - speed config seq */ 204 struct op_params sata_and_sgmii_speed_config_params[] = { 205 /* 206 * unit_base_reg, unit_offset, mask, SATA data, 207 * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops 208 */ 209 /* Baud Rate */ 210 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, 211 {0x8800000, 0x19800000, 0x22000000}, 0, 0}, 212 /* Select Baud Rate for SATA only */ 213 {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0}, 214 /* Phy Gen RX and TX */ 215 {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0}, 216 /* Bus Width */ 217 {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0} 218 }; 219 220 /* SATA and SGMII - TX config seq */ 221 struct op_params sata_and_sgmii_tx_config_params1[] = { 222 /* 223 * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data, 224 * wait_time, num_of_loops 225 */ 226 {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0}, 227 /* Sft Reset pulse */ 228 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0}, 229 /* Sft Reset pulse */ 230 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0}, 231 /* Power up PLL, RX and TX */ 232 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000}, 233 0, 0} 234 }; 235 236 struct op_params sata_port0_tx_config_params[] = { 237 /* 238 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 239 * num_of_loops 240 */ 241 /* Power Down Sata addr */ 242 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0}, 243 /* Power Down Sata Port 0 */ 244 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0}, 245 /* Regret bit addr */ 246 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0}, 247 /* Regret bit data */ 248 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0} 249 }; 250 251 struct op_params sata_port1_tx_config_params[] = { 252 /* 253 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 254 * num_of_loops 255 */ 256 /* Power Down Sata addr */ 257 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0}, 258 /* Power Down Sata Port 1 */ 259 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0}, 260 /* Regret bit addr */ 261 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0}, 262 /* Regret bit data */ 263 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0} 264 }; 265 266 struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = { 267 /* 268 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 269 * wait_time, num_of_loops 270 */ 271 /* Wait for PHY power up sequence to finish */ 272 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000}, 273 /* Wait for PHY power up sequence to finish */ 274 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000} 275 }; 276 277 struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = { 278 /* 279 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 280 * wait_time, num_of_loops 281 */ 282 /* Wait for PHY power up sequence to finish */ 283 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000}, 284 /* Assert Rx Init for SGMII */ 285 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000}, 286 0, 0}, 287 /* Assert Rx Init for SATA */ 288 {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0}, 289 /* Wait for PHY power up sequence to finish */ 290 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}, 291 /* De-assert Rx Init for SGMII */ 292 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0}, 293 /* De-assert Rx Init for SATA */ 294 {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0}, 295 /* os_ph_offset_force (align 90) */ 296 {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0}, 297 /* Set os_ph_valid */ 298 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0}, 299 /* Unset os_ph_valid */ 300 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0}, 301 }; 302 303 struct op_params sata_electrical_config_serdes_rev1_params[] = { 304 /* 305 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 306 * num_of_loops 307 */ 308 /* enable SSC and DFE update enable */ 309 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0}, 310 /* tximpcal_th and rximpcal_th */ 311 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0}, 312 /* SQ_THRESH and FFE Setting */ 313 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0}, 314 /* G1_TX SLEW, EMPH1 and AMP */ 315 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0}, 316 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 317 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0}, 318 /* G2_TX SLEW, EMPH1 and AMP */ 319 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0}, 320 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 321 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0}, 322 /* G3_TX SLEW, EMPH1 and AMP */ 323 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0}, 324 /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 325 {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0}, 326 /* Cal rxclkalign90 ext enable and Cal os ph ext */ 327 {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0}, 328 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */ 329 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0}, 330 }; 331 332 struct op_params sata_electrical_config_serdes_rev2_params[] = { 333 /* 334 * unit_base_reg, unit_offset, mask, SATA data, wait_time, 335 * num_of_loops 336 */ 337 /* SQ_THRESH and FFE Setting */ 338 {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0}, 339 /* enable SSC and DFE update enable */ 340 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0}, 341 /* G1_TX SLEW, EMPH1 and AMP */ 342 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0}, 343 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 344 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 345 /* G2_TX SLEW, EMPH1 and AMP */ 346 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0}, 347 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 348 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 349 /* G3_TX SLEW, EMPH1 and AMP */ 350 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0}, 351 /* 352 * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3, 353 * DC wander calibration dis 354 */ 355 {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0}, 356 /* Bit[12]=0x0 idle_sync_en */ 357 {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0}, 358 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */ 359 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0}, 360 /* tximpcal_th and rximpcal_th */ 361 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 362 /* DFE_STEP_FINE_FX[3:0] =0xa */ 363 {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0}, 364 /* DFE_EN and Dis Update control from pin disable */ 365 {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0}, 366 /* FFE Force FFE_REs and cap settings for Gen1 */ 367 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 368 /* FFE Force FFE_REs and cap settings for Gen2 */ 369 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0}, 370 /* FE Force FFE_REs=4 and cap settings for Gen3n */ 371 {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 372 /* Set DFE Gen 3 Resolution to 3 */ 373 {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0}, 374 }; 375 376 struct op_params sgmii_electrical_config_serdes_rev1_params[] = { 377 /* 378 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G), 379 * wait_time, num_of_loops 380 */ 381 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 382 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0}, 383 /* SQ_THRESH and FFE Setting */ 384 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0}, 385 /* tximpcal_th and rximpcal_th */ 386 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0}, 387 }; 388 389 struct op_params sgmii_electrical_config_serdes_rev2_params[] = { 390 /* 391 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G), 392 * wait_time, num_of_loops 393 */ 394 /* Set Slew_rate, Emph and Amp */ 395 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0}, 396 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 397 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0}, 398 /* DTL_FLOOP_EN */ 399 {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0}, 400 /* G1 FFE Setting Force, RES and CAP */ 401 {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0}, 402 /* tximpcal_th and rximpcal_th */ 403 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0}, 404 }; 405 406 /* 407 * PEX and USB3 408 */ 409 410 /* PEX and USB3 - power up seq for Serdes Rev 1.2 */ 411 struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = { 412 /* 413 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 414 * wait_time, num_of_loops 415 */ 416 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806, 417 {0x4471804, 0x4479804}, 0, 0}, 418 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0}, 419 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0}, 420 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0}, 421 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0}, 422 /* Ref clock source select */ 423 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0} 424 }; 425 426 /* PEX and USB3 - power up seq for Serdes Rev 2.1 */ 427 struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = { 428 /* 429 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 430 * wait_time, num_of_loops 431 */ 432 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806, 433 {0x4471804, 0x4479804}, 0, 0}, 434 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0}, 435 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0}, 436 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0}, 437 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0}, 438 {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0}, 439 /* Ref clock source select */ 440 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0} 441 }; 442 443 /* PEX and USB3 - speed config seq */ 444 struct op_params pex_and_usb3_speed_config_params[] = { 445 /* 446 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 447 * wait_time, num_of_loops 448 */ 449 /* Maximal PHY Generation Setting */ 450 {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400}, 451 0, 0}, 452 }; 453 454 struct op_params usb3_electrical_config_serdes_rev1_params[] = { 455 /* Spread Spectrum Clock Enable */ 456 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0}, 457 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */ 458 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0}, 459 /* tximpcal_th and rximpcal_th */ 460 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0}, 461 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 462 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 463 /* FFE Setting Force, RES and CAP */ 464 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0}, 465 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */ 466 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0}, 467 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */ 468 {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0}, 469 /* vco_cal_vth_sel */ 470 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0}, 471 }; 472 473 struct op_params usb3_electrical_config_serdes_rev2_params[] = { 474 /* Spread Spectrum Clock Enable */ 475 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0}, 476 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */ 477 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0}, 478 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 479 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0}, 480 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */ 481 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0}, 482 /* vco_cal_vth_sel */ 483 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0}, 484 /* Spread Spectrum Clock Enable */ 485 {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0}, 486 }; 487 488 /* PEX and USB3 - TX config seq */ 489 490 /* 491 * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run 492 * one by one on the lane. 493 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run 494 * by setting each sequence for all 4 lanes. 495 */ 496 struct op_params pex_and_usb3_tx_config_params1[] = { 497 /* 498 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 499 * wait_time, num_of_loops 500 */ 501 {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0}, 502 /* 10ms delay */ 503 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}, 504 /* os_ph_offset_force (align 90) */ 505 {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0}, 506 /* Set os_ph_valid */ 507 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0}, 508 /* Unset os_ph_valid */ 509 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0}, 510 }; 511 512 struct op_params pex_and_usb3_tx_config_params2[] = { 513 /* 514 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 515 * wait_time, num_of_loops 516 */ 517 /* Sft Reset pulse */ 518 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0}, 519 }; 520 521 struct op_params pex_and_usb3_tx_config_params3[] = { 522 /* 523 * unit_base_reg, unit_offset, mask, PEX data, USB3 data, 524 * wait_time, num_of_loops 525 */ 526 /* Sft Reset pulse */ 527 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0}, 528 /* 10ms delay */ 529 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0} 530 }; 531 532 /* PEX by 4 config seq */ 533 struct op_params pex_by4_config_params[] = { 534 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ 535 {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, 536 /* Lane Alignement enable */ 537 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, 538 /* Max PLL phy config */ 539 {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, 540 0, 0}, 541 /* Max PLL pipe config */ 542 {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0}, 543 }; 544 545 /* USB3 device donfig seq */ 546 struct op_params usb3_device_config_params[] = { 547 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ 548 {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0} 549 }; 550 551 /* PEX - electrical configuration seq Rev 1.2 */ 552 struct op_params pex_electrical_config_serdes_rev1_params[] = { 553 /* 554 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 555 * num_of_loops 556 */ 557 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */ 558 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0}, 559 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 560 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 561 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 562 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 563 /* CFG_DFE_EN_SEL */ 564 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0}, 565 /* FFE Setting Force, RES and CAP */ 566 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0}, 567 /* tximpcal_th and rximpcal_th */ 568 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 569 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */ 570 {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0}, 571 }; 572 573 /* PEX - electrical configuration seq Rev 2.1 */ 574 struct op_params pex_electrical_config_serdes_rev2_params[] = { 575 /* 576 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 577 * num_of_loops 578 */ 579 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */ 580 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0}, 581 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 582 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 583 /* G1 FFE Setting Force, RES and CAP */ 584 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0}, 585 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */ 586 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0}, 587 /* G2 FFE Setting Force, RES and CAP */ 588 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0}, 589 /* G2 DFE resolution value */ 590 {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0}, 591 /* DFE resolution force */ 592 {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0}, 593 /* Tx amplitude for Tx Margin 0 */ 594 {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0}, 595 /* Tx_Emph value for -3.5d_b and -6d_b */ 596 {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0}, 597 /* CFG_DFE_EN_SEL */ 598 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0}, 599 /* tximpcal_th and rximpcal_th */ 600 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, 601 }; 602 603 /* PEX - configuration seq for REF_CLOCK_25MHz */ 604 struct op_params pex_config_ref_clock25_m_hz[] = { 605 /* 606 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 607 * num_of_loops 608 */ 609 /* Bits[4:0]=0x2 - REF_FREF_SEL */ 610 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0}, 611 /* Bit[10]=0x1 - REFCLK_SEL */ 612 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0}, 613 /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */ 614 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0}, 615 }; 616 617 /* PEX - configuration seq for REF_CLOCK_40MHz */ 618 struct op_params pex_config_ref_clock40_m_hz[] = { 619 /* 620 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 621 * num_of_loops 622 */ 623 /* Bits[4:0]=0x3 - REF_FREF_SEL */ 624 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0}, 625 /* Bits[10]=0x1 - REFCLK_SEL */ 626 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0}, 627 /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */ 628 {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0}, 629 }; 630 631 /* PEX - configuration seq for REF_CLOCK_100MHz */ 632 struct op_params pex_config_ref_clock100_m_hz[] = { 633 /* 634 * unit_base_reg, unit_offset, mask, PEX data, wait_time, 635 * num_of_loops 636 */ 637 /* Bits[4:0]=0x0 - REF_FREF_SEL */ 638 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0}, 639 /* Bit[10]=0x0 - REFCLK_SEL */ 640 {MISC_REG, 0x800, 0x400, {0x0}, 0, 0}, 641 /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */ 642 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0}, 643 }; 644 645 /* 646 * USB2 647 */ 648 649 struct op_params usb2_power_up_params[] = { 650 /* 651 * unit_base_reg, unit_offset, mask, USB2 data, wait_time, 652 * num_of_loops 653 */ 654 /* Init phy 0 */ 655 {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 656 /* Init phy 1 */ 657 {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 658 /* Init phy 2 */ 659 {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0}, 660 /* Phy offset 0x0 - PLL_CONTROL0 */ 661 {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0}, 662 {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 663 {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 664 {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0}, 665 /* Phy offset 0x1 - PLL_CONTROL1 */ 666 {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0}, 667 /* Phy0 register 3 - TX Channel control 0 */ 668 {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 669 /* Phy0 register 3 - TX Channel control 0 */ 670 {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 671 /* Phy0 register 3 - TX Channel control 0 */ 672 {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, 673 /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ 674 {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, 675 /* check REG_SQCAL_DONE is set */ 676 {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, 677 /* check PLL_READY is set */ 678 {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} 679 }; 680 681 /* 682 * QSGMII 683 */ 684 685 /* QSGMII - power up seq */ 686 struct op_params qsgmii_port_power_up_params[] = { 687 /* 688 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 689 * num_of_loops 690 */ 691 /* Connect the QSGMII to Gigabit Ethernet units */ 692 {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0}, 693 /* Power Up */ 694 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0}, 695 /* Unreset */ 696 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0}, 697 /* Phy Selector */ 698 {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0}, 699 /* Ref clock source select */ 700 {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0} 701 }; 702 703 /* QSGMII - speed config seq */ 704 struct op_params qsgmii_port_speed_config_params[] = { 705 /* 706 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 707 * num_of_loops 708 */ 709 /* Baud Rate */ 710 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0}, 711 /* Phy Gen RX and TX */ 712 {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0}, 713 /* Bus Width */ 714 {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0} 715 }; 716 717 /* QSGMII - Select electrical param seq */ 718 struct op_params qsgmii_port_electrical_config_params[] = { 719 /* 720 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 721 * num_of_loops 722 */ 723 /* Slew rate and emphasis */ 724 {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0} 725 }; 726 727 /* QSGMII - TX config seq */ 728 struct op_params qsgmii_port_tx_config_params1[] = { 729 /* 730 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 731 * num_of_loops 732 */ 733 {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0}, 734 /* Sft Reset pulse */ 735 {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0}, 736 /* Sft Reset pulse */ 737 {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0}, 738 /* Lane align */ 739 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0}, 740 /* Power up PLL, RX and TX */ 741 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0}, 742 /* Tx driver output idle */ 743 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0} 744 }; 745 746 struct op_params qsgmii_port_tx_config_params2[] = { 747 /* 748 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time, 749 * num_of_loops 750 */ 751 /* Wait for PHY power up sequence to finish */ 752 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000}, 753 /* Assert Rx Init and Tx driver output valid */ 754 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0}, 755 /* Wait for PHY power up sequence to finish */ 756 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000}, 757 /* De-assert Rx Init */ 758 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0} 759 }; 760 761 /* SERDES_POWER_DOWN */ 762 struct op_params serdes_power_down_params[] = { 763 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)}, 764 0, 0}, 765 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0} 766 }; 767 768 /* 769 * hws_ctrl_serdes_rev_get 770 * 771 * DESCRIPTION: Get the Serdes revision number 772 * 773 * INPUT: config_field - Field description enum 774 * 775 * OUTPUT: None 776 * 777 * RETURN: 778 * 8bit Serdes revision number 779 */ 780 u8 hws_ctrl_serdes_rev_get(void) 781 { 782 #ifdef CONFIG_ARMADA_38X 783 /* for A38x-Z1 */ 784 if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID) 785 return MV_SERDES_REV_1_2; 786 #endif 787 788 /* for A39x-Z1, A38x-A0 */ 789 return MV_SERDES_REV_2_1; 790 } 791 792 u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id, 793 enum serdes_mode serdes_mode) 794 { 795 u32 test_result = 0; 796 u8 serd_max_num, unit_numb; 797 enum unit_id unit_id; 798 799 if (serdes_type > RXAUI) { 800 printf("%s: Warning: Wrong serdes type %s serdes#%d\n", 801 __func__, serdes_type_to_string[serdes_type], serdes_id); 802 return MV_FAIL; 803 } 804 805 unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id; 806 unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num; 807 serd_max_num = sys_env_unit_max_num_get(unit_id); 808 809 /* if didn't exceed amount of required Serdes lanes for current type */ 810 if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) { 811 /* update amount of required Serdes lanes for current type */ 812 serdes_lane_in_use_count[unit_id][unit_numb]--; 813 814 /* 815 * If reached the exact amount of required Serdes lanes for 816 * current type 817 */ 818 if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) { 819 if (((serdes_type <= PEX3)) && 820 ((serdes_mode == PEX_END_POINT_X4) || 821 (serdes_mode == PEX_ROOT_COMPLEX_X4))) { 822 /* PCiex4 uses 2 SerDes */ 823 serdes_unit_count[PEX_UNIT_ID] += 2; 824 } else { 825 serdes_unit_count[unit_id]++; 826 } 827 828 /* test SoC unit count limitation */ 829 if (serdes_unit_count[unit_id] > serd_max_num) { 830 test_result = WRONG_NUMBER_OF_UNITS; 831 } else if (unit_numb >= serd_max_num) { 832 /* test SoC unit number limitation */ 833 test_result = UNIT_NUMBER_VIOLATION; 834 } 835 } 836 } else { 837 test_result = SERDES_ALREADY_IN_USE; 838 if (test_result == SERDES_ALREADY_IN_USE) { 839 printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n", 840 __func__, serdes_id, 841 serdes_type_to_string[serdes_type]); 842 return MV_FAIL; 843 } else if (test_result == WRONG_NUMBER_OF_UNITS) { 844 printf("%s: Warning: serdes lane %d is set to type %s.\n", 845 __func__, serdes_id, 846 serdes_type_to_string[serdes_type]); 847 printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n", 848 __func__, serd_max_num); 849 return MV_FAIL; 850 } else if (test_result == UNIT_NUMBER_VIOLATION) { 851 printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n", 852 __func__, serdes_id, 853 serdes_type_to_string[serdes_type], 854 serd_max_num); 855 return MV_FAIL; 856 } 857 } 858 859 return MV_OK; 860 } 861 862 void hws_serdes_xaui_topology_verify(void) 863 { 864 /* 865 * If XAUI is in use - serdes_lane_in_use_count has to be = 0; 866 * if it is not in use hast be = 4 867 */ 868 if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) && 869 (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) { 870 printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n", 871 __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]); 872 printf("%s: XAUI has to be defined on 4 lanes\n", __func__); 873 } 874 875 /* 876 * If RXAUI is in use - serdes_lane_in_use_count has to be = 0; 877 * if it is not in use hast be = 2 878 */ 879 if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) && 880 (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) { 881 printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n", 882 __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]); 883 printf("%s: RXAUI has to be defined on 2 lanes\n", __func__); 884 } 885 } 886 887 int hws_serdes_seq_db_init(void) 888 { 889 u8 serdes_rev = hws_ctrl_serdes_rev_get(); 890 891 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n"); 892 893 if (serdes_rev == MV_SERDES_REV_NA) { 894 printf("hws_serdes_seq_db_init: serdes revision number is not supported\n"); 895 return MV_NOT_SUPPORTED; 896 } 897 898 /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */ 899 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr = 900 sata_port0_power_up_params; 901 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size = 902 sizeof(sata_port0_power_up_params) / sizeof(struct op_params); 903 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA; 904 905 /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */ 906 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr = 907 sata_port1_power_up_params; 908 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size = 909 sizeof(sata_port1_power_up_params) / sizeof(struct op_params); 910 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA; 911 912 /* SATA_POWER_UP_SEQ sequence init */ 913 serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr = 914 sata_and_sgmii_power_up_params; 915 serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size = 916 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params); 917 serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA; 918 919 /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */ 920 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr = 921 sata_and_sgmii_speed_config_params; 922 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size = 923 sizeof(sata_and_sgmii_speed_config_params) / 924 sizeof(struct op_params); 925 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 926 927 /* SATA_3_SPEED_CONFIG_SEQ sequence init */ 928 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr = 929 sata_and_sgmii_speed_config_params; 930 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size = 931 sizeof(sata_and_sgmii_speed_config_params) / 932 sizeof(struct op_params); 933 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 934 935 /* SATA_6_SPEED_CONFIG_SEQ sequence init */ 936 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr = 937 sata_and_sgmii_speed_config_params; 938 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size = 939 sizeof(sata_and_sgmii_speed_config_params) / 940 sizeof(struct op_params); 941 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA; 942 943 /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */ 944 if (serdes_rev == MV_SERDES_REV_1_2) { 945 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 946 sata_electrical_config_serdes_rev1_params; 947 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 948 sizeof(sata_electrical_config_serdes_rev1_params) / 949 sizeof(struct op_params); 950 } else { 951 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 952 sata_electrical_config_serdes_rev2_params; 953 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 954 sizeof(sata_electrical_config_serdes_rev2_params) / 955 sizeof(struct op_params); 956 } 957 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA; 958 959 /* SATA_TX_CONFIG_SEQ sequence init */ 960 serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr = 961 sata_and_sgmii_tx_config_params1; 962 serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size = 963 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params); 964 serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA; 965 966 /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */ 967 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr = 968 sata_port0_tx_config_params; 969 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size = 970 sizeof(sata_port0_tx_config_params) / sizeof(struct op_params); 971 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA; 972 973 /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */ 974 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr = 975 sata_port1_tx_config_params; 976 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size = 977 sizeof(sata_port1_tx_config_params) / sizeof(struct op_params); 978 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA; 979 980 /* SATA_TX_CONFIG_SEQ2 sequence init */ 981 if (serdes_rev == MV_SERDES_REV_1_2) { 982 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr = 983 sata_and_sgmii_tx_config_serdes_rev1_params2; 984 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size = 985 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) / 986 sizeof(struct op_params); 987 } else { 988 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr = 989 sata_and_sgmii_tx_config_serdes_rev2_params2; 990 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size = 991 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) / 992 sizeof(struct op_params); 993 } 994 serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA; 995 996 /* SGMII_POWER_UP_SEQ sequence init */ 997 serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr = 998 sata_and_sgmii_power_up_params; 999 serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size = 1000 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params); 1001 serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII; 1002 1003 /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */ 1004 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr = 1005 sata_and_sgmii_speed_config_params; 1006 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size = 1007 sizeof(sata_and_sgmii_speed_config_params) / 1008 sizeof(struct op_params); 1009 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII; 1010 1011 /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */ 1012 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr = 1013 sata_and_sgmii_speed_config_params; 1014 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size = 1015 sizeof(sata_and_sgmii_speed_config_params) / 1016 sizeof(struct op_params); 1017 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125; 1018 1019 /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1020 if (serdes_rev == MV_SERDES_REV_1_2) { 1021 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1022 sgmii_electrical_config_serdes_rev1_params; 1023 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1024 sizeof(sgmii_electrical_config_serdes_rev1_params) / 1025 sizeof(struct op_params); 1026 } else { 1027 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1028 sgmii_electrical_config_serdes_rev2_params; 1029 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1030 sizeof(sgmii_electrical_config_serdes_rev2_params) / 1031 sizeof(struct op_params); 1032 } 1033 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII; 1034 1035 /* SGMII_TX_CONFIG_SEQ sequence init */ 1036 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr = 1037 sata_and_sgmii_tx_config_params1; 1038 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size = 1039 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params); 1040 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII; 1041 1042 /* SGMII_TX_CONFIG_SEQ sequence init */ 1043 if (serdes_rev == MV_SERDES_REV_1_2) { 1044 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr = 1045 sata_and_sgmii_tx_config_serdes_rev1_params2; 1046 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1047 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) / 1048 sizeof(struct op_params); 1049 } else { 1050 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr = 1051 sata_and_sgmii_tx_config_serdes_rev2_params2; 1052 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1053 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) / 1054 sizeof(struct op_params); 1055 } 1056 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII; 1057 1058 /* PEX_POWER_UP_SEQ sequence init */ 1059 if (serdes_rev == MV_SERDES_REV_1_2) { 1060 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr = 1061 pex_and_usb3_power_up_serdes_rev1_params; 1062 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size = 1063 sizeof(pex_and_usb3_power_up_serdes_rev1_params) / 1064 sizeof(struct op_params); 1065 } else { 1066 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr = 1067 pex_and_usb3_power_up_serdes_rev2_params; 1068 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size = 1069 sizeof(pex_and_usb3_power_up_serdes_rev2_params) / 1070 sizeof(struct op_params); 1071 } 1072 serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX; 1073 1074 /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */ 1075 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr = 1076 pex_and_usb3_speed_config_params; 1077 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1078 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1079 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx = 1080 PEXSERDES_SPEED_2_5_GBPS; 1081 1082 /* PEX_5_SPEED_CONFIG_SEQ sequence init */ 1083 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr = 1084 pex_and_usb3_speed_config_params; 1085 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1086 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1087 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx = 1088 PEXSERDES_SPEED_5_GBPS; 1089 1090 /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1091 if (serdes_rev == MV_SERDES_REV_1_2) { 1092 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1093 pex_electrical_config_serdes_rev1_params; 1094 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1095 sizeof(pex_electrical_config_serdes_rev1_params) / 1096 sizeof(struct op_params); 1097 } else { 1098 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1099 pex_electrical_config_serdes_rev2_params; 1100 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1101 sizeof(pex_electrical_config_serdes_rev2_params) / 1102 sizeof(struct op_params); 1103 } 1104 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX; 1105 1106 /* PEX_TX_CONFIG_SEQ1 sequence init */ 1107 serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr = 1108 pex_and_usb3_tx_config_params1; 1109 serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size = 1110 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params); 1111 serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX; 1112 1113 /* PEX_TX_CONFIG_SEQ2 sequence init */ 1114 serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr = 1115 pex_and_usb3_tx_config_params2; 1116 serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size = 1117 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params); 1118 serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX; 1119 1120 /* PEX_TX_CONFIG_SEQ3 sequence init */ 1121 serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr = 1122 pex_and_usb3_tx_config_params3; 1123 serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size = 1124 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params); 1125 serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX; 1126 1127 /* PEX_BY_4_CONFIG_SEQ sequence init */ 1128 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr = 1129 pex_by4_config_params; 1130 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size = 1131 sizeof(pex_by4_config_params) / sizeof(struct op_params); 1132 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX; 1133 1134 /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */ 1135 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr = 1136 pex_config_ref_clock25_m_hz; 1137 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size = 1138 sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params); 1139 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX; 1140 1141 /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */ 1142 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr = 1143 pex_config_ref_clock40_m_hz; 1144 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size = 1145 sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params); 1146 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX; 1147 1148 /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */ 1149 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr = 1150 pex_config_ref_clock100_m_hz; 1151 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size = 1152 sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params); 1153 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX; 1154 1155 /* USB3_POWER_UP_SEQ sequence init */ 1156 if (serdes_rev == MV_SERDES_REV_1_2) { 1157 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr = 1158 pex_and_usb3_power_up_serdes_rev1_params; 1159 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size = 1160 sizeof(pex_and_usb3_power_up_serdes_rev1_params) / 1161 sizeof(struct op_params); 1162 } else { 1163 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr = 1164 pex_and_usb3_power_up_serdes_rev2_params; 1165 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size = 1166 sizeof(pex_and_usb3_power_up_serdes_rev2_params) / 1167 sizeof(struct op_params); 1168 } 1169 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3; 1170 1171 /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */ 1172 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr = 1173 pex_and_usb3_speed_config_params; 1174 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size = 1175 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1176 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx = 1177 USB3SERDES_SPEED_5_GBPS_HOST; 1178 1179 /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */ 1180 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr = 1181 pex_and_usb3_speed_config_params; 1182 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size = 1183 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params); 1184 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx = 1185 USB3SERDES_SPEED_5_GBPS_DEVICE; 1186 1187 /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1188 if (serdes_rev == MV_SERDES_REV_1_2) { 1189 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1190 usb3_electrical_config_serdes_rev1_params; 1191 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1192 sizeof(usb3_electrical_config_serdes_rev1_params) / 1193 sizeof(struct op_params); 1194 } else { 1195 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1196 usb3_electrical_config_serdes_rev2_params; 1197 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1198 sizeof(usb3_electrical_config_serdes_rev2_params) / 1199 sizeof(struct op_params); 1200 } 1201 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3; 1202 1203 /* USB3_TX_CONFIG_SEQ sequence init */ 1204 serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr = 1205 pex_and_usb3_tx_config_params1; 1206 serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size = 1207 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params); 1208 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3; 1209 1210 /* USB3_TX_CONFIG_SEQ sequence init */ 1211 serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr = 1212 pex_and_usb3_tx_config_params2; 1213 serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size = 1214 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params); 1215 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3; 1216 1217 /* USB3_TX_CONFIG_SEQ sequence init */ 1218 serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr = 1219 pex_and_usb3_tx_config_params3; 1220 serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size = 1221 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params); 1222 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3; 1223 1224 /* USB2_POWER_UP_SEQ sequence init */ 1225 serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params; 1226 serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size = 1227 sizeof(usb2_power_up_params) / sizeof(struct op_params); 1228 serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0; 1229 1230 /* USB3_DEVICE_CONFIG_SEQ sequence init */ 1231 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr = 1232 usb3_device_config_params; 1233 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size = 1234 sizeof(usb3_device_config_params) / sizeof(struct op_params); 1235 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */ 1236 1237 /* SERDES_POWER_DOWN_SEQ sequence init */ 1238 serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr = 1239 serdes_power_down_params; 1240 serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size = 1241 sizeof(serdes_power_down_params) / 1242 sizeof(struct op_params); 1243 serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL; 1244 1245 if (serdes_rev == MV_SERDES_REV_2_1) { 1246 /* QSGMII_POWER_UP_SEQ sequence init */ 1247 serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr = 1248 qsgmii_port_power_up_params; 1249 serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size = 1250 sizeof(qsgmii_port_power_up_params) / 1251 sizeof(struct op_params); 1252 serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx = 1253 QSGMII_SEQ_IDX; 1254 1255 /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */ 1256 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr = 1257 qsgmii_port_speed_config_params; 1258 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size = 1259 sizeof(qsgmii_port_speed_config_params) / 1260 sizeof(struct op_params); 1261 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx = 1262 QSGMII_SEQ_IDX; 1263 1264 /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */ 1265 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr = 1266 qsgmii_port_electrical_config_params; 1267 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size = 1268 sizeof(qsgmii_port_electrical_config_params) / 1269 sizeof(struct op_params); 1270 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = 1271 QSGMII_SEQ_IDX; 1272 1273 /* QSGMII_TX_CONFIG_SEQ sequence init */ 1274 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr = 1275 qsgmii_port_tx_config_params1; 1276 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size = 1277 sizeof(qsgmii_port_tx_config_params1) / 1278 sizeof(struct op_params); 1279 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx = 1280 QSGMII_SEQ_IDX; 1281 1282 /* QSGMII_TX_CONFIG_SEQ sequence init */ 1283 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr = 1284 qsgmii_port_tx_config_params2; 1285 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size = 1286 sizeof(qsgmii_port_tx_config_params2) / 1287 sizeof(struct op_params); 1288 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx = 1289 QSGMII_SEQ_IDX; 1290 } 1291 1292 return MV_OK; 1293 } 1294 1295 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, 1296 enum serdes_speed baud_rate) 1297 { 1298 enum serdes_seq seq_id = SERDES_LAST_SEQ; 1299 1300 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n"); 1301 switch (serdes_type) { 1302 case PEX0: 1303 case PEX1: 1304 case PEX2: 1305 case PEX3: 1306 if (baud_rate == SERDES_SPEED_2_5_GBPS) 1307 seq_id = PEX_2_5_SPEED_CONFIG_SEQ; 1308 else if (baud_rate == SERDES_SPEED_5_GBPS) 1309 seq_id = PEX_5_SPEED_CONFIG_SEQ; 1310 break; 1311 case USB3_HOST0: 1312 case USB3_HOST1: 1313 if (baud_rate == SERDES_SPEED_5_GBPS) 1314 seq_id = USB3_HOST_SPEED_CONFIG_SEQ; 1315 break; 1316 case USB3_DEVICE: 1317 if (baud_rate == SERDES_SPEED_5_GBPS) 1318 seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ; 1319 break; 1320 case SATA0: 1321 case SATA1: 1322 case SATA2: 1323 case SATA3: 1324 if (baud_rate == SERDES_SPEED_1_5_GBPS) 1325 seq_id = SATA_1_5_SPEED_CONFIG_SEQ; 1326 else if (baud_rate == SERDES_SPEED_3_GBPS) 1327 seq_id = SATA_3_SPEED_CONFIG_SEQ; 1328 else if (baud_rate == SERDES_SPEED_6_GBPS) 1329 seq_id = SATA_6_SPEED_CONFIG_SEQ; 1330 break; 1331 case SGMII0: 1332 case SGMII1: 1333 case SGMII2: 1334 #ifdef CONFIG_ARMADA_39X 1335 case SGMII3: 1336 #endif 1337 if (baud_rate == SERDES_SPEED_1_25_GBPS) 1338 seq_id = SGMII_1_25_SPEED_CONFIG_SEQ; 1339 else if (baud_rate == SERDES_SPEED_3_125_GBPS) 1340 seq_id = SGMII_3_125_SPEED_CONFIG_SEQ; 1341 break; 1342 case QSGMII: 1343 seq_id = QSGMII_5_SPEED_CONFIG_SEQ; 1344 break; 1345 #ifdef CONFIG_ARMADA_39X 1346 case XAUI: 1347 seq_id = XAUI_3_125_SPEED_CONFIG_SEQ; 1348 break; 1349 case RXAUI: 1350 seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ; 1351 break; 1352 #endif 1353 default: 1354 return SERDES_LAST_SEQ; 1355 } 1356 1357 return seq_id; 1358 } 1359 1360 static void print_topology_details(const struct serdes_map *serdes_map, 1361 u8 count) 1362 { 1363 u32 lane_num; 1364 1365 DEBUG_INIT_S("board SerDes lanes topology details:\n"); 1366 1367 DEBUG_INIT_S(" | Lane # | Speed | Type |\n"); 1368 DEBUG_INIT_S(" --------------------------------\n"); 1369 for (lane_num = 0; lane_num < count; lane_num++) { 1370 if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES) 1371 continue; 1372 DEBUG_INIT_S(" | "); 1373 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1); 1374 DEBUG_INIT_S(" | "); 1375 DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2); 1376 DEBUG_INIT_S(" | "); 1377 DEBUG_INIT_S((char *) 1378 serdes_type_to_string[serdes_map[lane_num]. 1379 serdes_type]); 1380 DEBUG_INIT_S("\t|\n"); 1381 } 1382 DEBUG_INIT_S(" --------------------------------\n"); 1383 } 1384 1385 int hws_pre_serdes_init_config(void) 1386 { 1387 u32 data; 1388 1389 /* 1390 * Configure Core PLL 1391 */ 1392 /* 1393 * set PLL parameters 1394 * bits[2:0] =0x3 (Core-PLL Kdiv) 1395 * bits[20:12]=0x9f (Core-PLL Ndiv) 1396 * bits[24:21]=0x7(Core-PLL VCO Band) 1397 * bits[28:25]=0x1(Core-PLL Rlf) 1398 * bits[31:29]=0x2(Core-PLL charge-pump adjust) 1399 */ 1400 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003); 1401 1402 /* Enable PLL Configuration */ 1403 data = reg_read(CORE_PLL_CONFIG_REG); 1404 data = SET_BIT(data, 9); 1405 reg_write(CORE_PLL_CONFIG_REG, data); 1406 1407 return MV_OK; 1408 } 1409 1410 int serdes_phy_config(void) 1411 { 1412 struct serdes_map *serdes_map; 1413 u8 serdes_count; 1414 1415 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n"); 1416 1417 DEBUG_INIT_S("High speed PHY - Version: "); 1418 DEBUG_INIT_S(SERDES_VERION); 1419 DEBUG_INIT_S("\n"); 1420 1421 /* Init serdes sequences DB */ 1422 if (hws_serdes_seq_init() != MV_OK) { 1423 printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n"); 1424 return MV_FAIL; 1425 } 1426 1427 /* Board topology load */ 1428 DEBUG_INIT_FULL_S 1429 ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n"); 1430 CHECK_STATUS(hws_board_topology_load(&serdes_map, &serdes_count)); 1431 if (serdes_count > hws_serdes_get_max_lane()) { 1432 printf("Error: too many serdes lanes specified by board\n"); 1433 return MV_FAIL; 1434 } 1435 1436 /* print topology */ 1437 print_topology_details(serdes_map, serdes_count); 1438 CHECK_STATUS(hws_pre_serdes_init_config()); 1439 1440 /* Power-Up sequence */ 1441 DEBUG_INIT_FULL_S 1442 ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n"); 1443 1444 CHECK_STATUS(hws_power_up_serdes_lanes(serdes_map, serdes_count)); 1445 1446 DEBUG_INIT_FULL_S 1447 ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n"); 1448 1449 DEBUG_INIT_S(ENDED_OK); 1450 1451 return MV_OK; 1452 } 1453 1454 int serdes_polarity_config(u32 serdes_num, int is_rx) 1455 { 1456 u32 data; 1457 u32 reg_addr; 1458 u8 bit_off = (is_rx) ? 11 : 10; 1459 1460 reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG; 1461 data = reg_read(reg_addr); 1462 data = SET_BIT(data, bit_off); 1463 reg_write(reg_addr, data); 1464 1465 return MV_OK; 1466 } 1467 1468 int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count) 1469 { 1470 u32 serdes_id, serdes_lane_num; 1471 enum ref_clock ref_clock; 1472 enum serdes_type serdes_type; 1473 enum serdes_speed serdes_speed; 1474 enum serdes_mode serdes_mode; 1475 int serdes_rx_polarity_swap; 1476 int serdes_tx_polarity_swap; 1477 int is_pex_enabled = 0; 1478 1479 /* 1480 * is_pex_enabled: 1481 * Flag which indicates that one of the Serdes is of PEX. 1482 * In this case, PEX unit will be initialized after Serdes power-up 1483 */ 1484 1485 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n"); 1486 1487 /* COMMON PHYS SELECTORS register configuration */ 1488 DEBUG_INIT_FULL_S 1489 ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n"); 1490 CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_map, count)); 1491 1492 /* per Serdes Power Up */ 1493 for (serdes_id = 0; serdes_id < count; serdes_id++) { 1494 DEBUG_INIT_FULL_S 1495 ("calling serdes_power_up_ctrl: serdes lane number "); 1496 DEBUG_INIT_FULL_D_10(serdes_lane_num, 1); 1497 DEBUG_INIT_FULL_S("\n"); 1498 1499 serdes_lane_num = hws_get_physical_serdes_num(serdes_id); 1500 serdes_type = serdes_map[serdes_id].serdes_type; 1501 serdes_speed = serdes_map[serdes_id].serdes_speed; 1502 serdes_mode = serdes_map[serdes_id].serdes_mode; 1503 serdes_rx_polarity_swap = serdes_map[serdes_id].swap_rx; 1504 serdes_tx_polarity_swap = serdes_map[serdes_id].swap_tx; 1505 1506 /* serdes lane is not in use */ 1507 if (serdes_type == DEFAULT_SERDES) 1508 continue; 1509 else if (serdes_type <= PEX3) /* PEX type */ 1510 is_pex_enabled = 1; 1511 1512 ref_clock = hws_serdes_get_ref_clock_val(serdes_type); 1513 if (ref_clock == REF_CLOCK_UNSUPPORTED) { 1514 DEBUG_INIT_S 1515 ("hws_power_up_serdes_lanes: unsupported ref clock\n"); 1516 return MV_NOT_SUPPORTED; 1517 } 1518 CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num, 1519 1, 1520 serdes_type, 1521 serdes_speed, 1522 serdes_mode, ref_clock)); 1523 1524 /* RX Polarity config */ 1525 if (serdes_rx_polarity_swap) 1526 CHECK_STATUS(serdes_polarity_config 1527 (serdes_lane_num, 1)); 1528 1529 /* TX Polarity config */ 1530 if (serdes_tx_polarity_swap) 1531 CHECK_STATUS(serdes_polarity_config 1532 (serdes_lane_num, 0)); 1533 } 1534 1535 if (is_pex_enabled) { 1536 /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode. 1537 After finish the Power_up sequence for all lanes, 1538 the lanes should be released from reset state. */ 1539 CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count)); 1540 1541 /* PEX configuration */ 1542 CHECK_STATUS(hws_pex_config(serdes_map, count)); 1543 } 1544 1545 /* USB2 configuration */ 1546 DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n"); 1547 CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ)); 1548 1549 DEBUG_INIT_FULL_S 1550 ("### hws_power_up_serdes_lanes ended successfully ###\n"); 1551 1552 return MV_OK; 1553 } 1554 1555 int ctrl_high_speed_serdes_phy_config(void) 1556 { 1557 return hws_ctrl_high_speed_serdes_phy_config(); 1558 } 1559 1560 static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type) 1561 { 1562 u32 reg_data; 1563 1564 /* WA for A380 Z1 relevant for lanes 3,4,5 only */ 1565 if (serdes_num >= 3) { 1566 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); 1567 /* set delay on pipe - 1568 * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1. 1569 * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0. 1570 * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1. 1571 * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0. 1572 * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1. 1573 * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0. 1574 */ 1575 if (serdes_type == PEX) 1576 reg_data |= 1 << (7 + (serdes_num - 3)); 1577 if (serdes_type == USB3) { 1578 /* USB3 */ 1579 reg_data &= ~(1 << (7 + (serdes_num - 3))); 1580 } 1581 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); 1582 } 1583 1584 return MV_OK; 1585 } 1586 1587 /* 1588 * hws_serdes_pex_ref_clock_satr_get - 1589 * 1590 * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG 1591 * and check: 1592 * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31] 1593 * for PEX#3. 1594 * If bit=0 --> REF_CLOCK_100MHz 1595 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0 1596 * --> REF_CLOCK_25MHz 1597 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1 1598 * --> REF_CLOCK_40MHz 1599 * 1600 * INPUT: serdes_type - Type of Serdes 1601 * 1602 * OUTPUT: pex_satr - Return the REF_CLOCK value: 1603 * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz 1604 * 1605 * RETURNS: MV_OK - for success 1606 * MV_BAD_PARAM - for fail 1607 */ 1608 int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr) 1609 { 1610 u32 data, reg_satr1; 1611 1612 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); 1613 1614 switch (serdes_type) { 1615 case PEX0: 1616 data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1); 1617 break; 1618 case PEX1: 1619 data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1); 1620 break; 1621 case PEX2: 1622 data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1); 1623 break; 1624 case PEX3: 1625 data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1); 1626 break; 1627 default: 1628 printf("%s: Error: SerDes type %d is not supported\n", 1629 __func__, serdes_type); 1630 return MV_BAD_PARAM; 1631 } 1632 1633 *pex_satr = data; 1634 1635 return MV_OK; 1636 } 1637 1638 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type) 1639 { 1640 u32 pex_satr; 1641 enum ref_clock ref_clock; 1642 1643 DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n"); 1644 1645 if (serdes_type >= LAST_SERDES_TYPE) 1646 return REF_CLOCK_UNSUPPORTED; 1647 1648 /* read ref clock from S@R */ 1649 ref_clock = hws_serdes_silicon_ref_clock_get(); 1650 1651 if (serdes_type > PEX3) { 1652 /* for all Serdes types but PCIe */ 1653 return ref_clock; 1654 } 1655 1656 /* for PCIe, need also to check PCIe S@R */ 1657 CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get 1658 (serdes_type, &pex_satr)); 1659 1660 if (pex_satr == 0) { 1661 return REF_CLOCK_100MHZ; 1662 } else if (pex_satr == 1) { 1663 /* value of 1 means we can use ref clock from SoC (as other Serdes types) */ 1664 return ref_clock; 1665 } else { 1666 printf 1667 ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n", 1668 __func__, serdes_type); 1669 return REF_CLOCK_UNSUPPORTED; 1670 } 1671 } 1672 1673 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, 1674 enum serdes_type serdes_type, 1675 enum serdes_speed baud_rate, 1676 enum serdes_mode serdes_mode, enum ref_clock ref_clock) 1677 { 1678 u32 sata_idx, pex_idx, sata_port; 1679 enum serdes_seq speed_seq_id; 1680 u32 reg_data; 1681 int is_pex_by1; 1682 1683 DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n"); 1684 1685 if (serdes_power_up == 1) { /* Serdes power up */ 1686 DEBUG_INIT_FULL_S 1687 ("serdes_power_up_ctrl: executing power up.. "); 1688 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2); 1689 DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2); 1690 1691 DEBUG_INIT_FULL_S("Going access 1"); 1692 1693 /* Getting the Speed Select sequence id */ 1694 speed_seq_id = 1695 serdes_type_and_speed_to_speed_seq(serdes_type, 1696 baud_rate); 1697 if (speed_seq_id == SERDES_LAST_SEQ) { 1698 printf 1699 ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n", 1700 serdes_type, baud_rate); 1701 1702 return MV_BAD_PARAM; 1703 } 1704 1705 /* Executing power up, ref clock set, speed config and TX config */ 1706 switch (serdes_type) { 1707 case PEX0: 1708 case PEX1: 1709 case PEX2: 1710 case PEX3: 1711 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) { 1712 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a 1713 (serdes_num, PEX)); 1714 } 1715 1716 is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) || 1717 (serdes_mode == PEX_END_POINT_X1); 1718 pex_idx = serdes_type - PEX0; 1719 1720 if ((is_pex_by1 == 1) || (serdes_type == PEX0)) { 1721 /* For PEX by 4, init only the PEX 0 */ 1722 reg_data = reg_read(SOC_CONTROL_REG1); 1723 if (is_pex_by1 == 1) 1724 reg_data |= 0x4000; 1725 else 1726 reg_data &= ~0x4000; 1727 reg_write(SOC_CONTROL_REG1, reg_data); 1728 1729 reg_data = 1730 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1731 0x6c)); 1732 reg_data &= ~0x3f0; 1733 if (is_pex_by1 == 1) 1734 reg_data |= 0x10; 1735 else 1736 reg_data |= 0x40; 1737 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), 1738 reg_data); 1739 1740 reg_data = 1741 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1742 0x6c)); 1743 reg_data &= ~0xf; 1744 reg_data |= 0x2; 1745 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), 1746 reg_data); 1747 1748 reg_data = 1749 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + 1750 0x70)); 1751 reg_data &= ~0x40; 1752 reg_data |= 0x40; 1753 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), 1754 reg_data); 1755 } 1756 1757 CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ)); 1758 if (is_pex_by1 == 0) { 1759 /* 1760 * for PEX by 4 - use the PEX index as the 1761 * seq array index 1762 */ 1763 serdes_seq_db[PEX_BY_4_CONFIG_SEQ]. 1764 data_arr_idx = pex_idx; 1765 CHECK_STATUS(mv_seq_exec 1766 (serdes_num, PEX_BY_4_CONFIG_SEQ)); 1767 } 1768 1769 CHECK_STATUS(hws_ref_clock_set 1770 (serdes_num, serdes_type, ref_clock)); 1771 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1772 CHECK_STATUS(mv_seq_exec 1773 (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ)); 1774 1775 if (is_pex_by1 == 1) { 1776 CHECK_STATUS(mv_seq_exec 1777 (serdes_num, PEX_TX_CONFIG_SEQ2)); 1778 CHECK_STATUS(mv_seq_exec 1779 (serdes_num, PEX_TX_CONFIG_SEQ3)); 1780 CHECK_STATUS(mv_seq_exec 1781 (serdes_num, PEX_TX_CONFIG_SEQ1)); 1782 } 1783 udelay(20); 1784 1785 break; 1786 case USB3_HOST0: 1787 case USB3_HOST1: 1788 case USB3_DEVICE: 1789 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) { 1790 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a 1791 (serdes_num, USB3)); 1792 } 1793 CHECK_STATUS(mv_seq_exec 1794 (serdes_num, USB3_POWER_UP_SEQ)); 1795 CHECK_STATUS(hws_ref_clock_set 1796 (serdes_num, serdes_type, ref_clock)); 1797 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1798 if (serdes_type == USB3_DEVICE) { 1799 CHECK_STATUS(mv_seq_exec 1800 (serdes_num, 1801 USB3_DEVICE_CONFIG_SEQ)); 1802 } 1803 CHECK_STATUS(mv_seq_exec 1804 (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ)); 1805 CHECK_STATUS(mv_seq_exec 1806 (serdes_num, USB3_TX_CONFIG_SEQ1)); 1807 CHECK_STATUS(mv_seq_exec 1808 (serdes_num, USB3_TX_CONFIG_SEQ2)); 1809 CHECK_STATUS(mv_seq_exec 1810 (serdes_num, USB3_TX_CONFIG_SEQ3)); 1811 1812 udelay(10000); 1813 break; 1814 case SATA0: 1815 case SATA1: 1816 case SATA2: 1817 case SATA3: 1818 sata_idx = ((serdes_type == SATA0) || 1819 (serdes_type == SATA1)) ? 0 : 1; 1820 sata_port = ((serdes_type == SATA0) || 1821 (serdes_type == SATA2)) ? 0 : 1; 1822 1823 CHECK_STATUS(mv_seq_exec 1824 (sata_idx, (sata_port == 0) ? 1825 SATA_PORT_0_ONLY_POWER_UP_SEQ : 1826 SATA_PORT_1_ONLY_POWER_UP_SEQ)); 1827 CHECK_STATUS(mv_seq_exec 1828 (serdes_num, SATA_POWER_UP_SEQ)); 1829 CHECK_STATUS(hws_ref_clock_set 1830 (serdes_num, serdes_type, ref_clock)); 1831 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1832 CHECK_STATUS(mv_seq_exec 1833 (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ)); 1834 CHECK_STATUS(mv_seq_exec 1835 (serdes_num, SATA_TX_CONFIG_SEQ1)); 1836 CHECK_STATUS(mv_seq_exec 1837 (sata_idx, (sata_port == 0) ? 1838 SATA_PORT_0_ONLY_TX_CONFIG_SEQ : 1839 SATA_PORT_1_ONLY_TX_CONFIG_SEQ)); 1840 CHECK_STATUS(mv_seq_exec 1841 (serdes_num, SATA_TX_CONFIG_SEQ2)); 1842 1843 udelay(10000); 1844 break; 1845 case SGMII0: 1846 case SGMII1: 1847 case SGMII2: 1848 CHECK_STATUS(mv_seq_exec 1849 (serdes_num, SGMII_POWER_UP_SEQ)); 1850 CHECK_STATUS(hws_ref_clock_set 1851 (serdes_num, serdes_type, ref_clock)); 1852 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1853 CHECK_STATUS(mv_seq_exec 1854 (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ)); 1855 CHECK_STATUS(mv_seq_exec 1856 (serdes_num, SGMII_TX_CONFIG_SEQ1)); 1857 CHECK_STATUS(mv_seq_exec 1858 (serdes_num, SGMII_TX_CONFIG_SEQ2)); 1859 1860 /* GBE configuration */ 1861 reg_data = reg_read(GBE_CONFIGURATION_REG); 1862 /* write the SGMII index */ 1863 reg_data |= 0x1 << (serdes_type - SGMII0); 1864 reg_write(GBE_CONFIGURATION_REG, reg_data); 1865 1866 break; 1867 case QSGMII: 1868 if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1) 1869 return MV_NOT_SUPPORTED; 1870 1871 CHECK_STATUS(mv_seq_exec 1872 (serdes_num, QSGMII_POWER_UP_SEQ)); 1873 CHECK_STATUS(hws_ref_clock_set 1874 (serdes_num, serdes_type, ref_clock)); 1875 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id)); 1876 CHECK_STATUS(mv_seq_exec 1877 (serdes_num, 1878 QSGMII_ELECTRICAL_CONFIG_SEQ)); 1879 CHECK_STATUS(mv_seq_exec 1880 (serdes_num, QSGMII_TX_CONFIG_SEQ1)); 1881 CHECK_STATUS(mv_seq_exec 1882 (serdes_num, QSGMII_TX_CONFIG_SEQ2)); 1883 break; 1884 case SGMII3: 1885 case XAUI: 1886 case RXAUI: 1887 CHECK_STATUS(serdes_power_up_ctrl_ext 1888 (serdes_num, serdes_power_up, serdes_type, 1889 baud_rate, serdes_mode, ref_clock)); 1890 break; 1891 default: 1892 DEBUG_INIT_S 1893 ("serdes_power_up_ctrl: bad serdes_type parameter\n"); 1894 return MV_BAD_PARAM; 1895 } 1896 } else { /* Serdes power down */ 1897 DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. "); 1898 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1); 1899 1900 CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ)); 1901 } 1902 1903 DEBUG_INIT_FULL_C( 1904 "serdes_power_up_ctrl ended successfully for serdes ", 1905 serdes_num, 2); 1906 1907 return MV_OK; 1908 } 1909 1910 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count) 1911 { 1912 u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0; 1913 enum serdes_type serdes_type; 1914 enum serdes_mode serdes_mode; 1915 u8 select_bit_off; 1916 int is_pex_x4 = 0; 1917 int updated_topology_print = 0; 1918 1919 DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n"); 1920 DEBUG_INIT_FULL_S 1921 ("Updating the COMMON PHYS SELECTORS register with the serdes types\n"); 1922 1923 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) 1924 select_bit_off = 3; 1925 else 1926 select_bit_off = 4; 1927 1928 /* 1929 * Updating bits 0-17 in the COMMON PHYS SELECTORS register 1930 * according to the serdes types 1931 */ 1932 for (idx = 0; idx < count; idx++) { 1933 serdes_type = serdes_map[idx].serdes_type; 1934 serdes_mode = serdes_map[idx].serdes_mode; 1935 serdes_lane_hw_num = hws_get_physical_serdes_num(idx); 1936 1937 lane_data = 1938 hws_serdes_get_phy_selector_val(serdes_lane_hw_num, 1939 serdes_type); 1940 1941 if (serdes_type == DEFAULT_SERDES) 1942 continue; 1943 1944 if (hws_serdes_topology_verify 1945 (serdes_type, idx, serdes_mode) != MV_OK) { 1946 serdes_map[idx].serdes_type = 1947 DEFAULT_SERDES; 1948 printf("%s: SerDes lane #%d is disabled\n", __func__, 1949 serdes_lane_hw_num); 1950 updated_topology_print = 1; 1951 continue; 1952 } 1953 1954 /* 1955 * Checking if the board topology configuration includes 1956 * PEXx4 - for the next step 1957 */ 1958 if ((serdes_mode == PEX_END_POINT_X4) || 1959 (serdes_mode == PEX_ROOT_COMPLEX_X4)) { 1960 /* update lane data to the 3 next SERDES lanes */ 1961 lane_data = 1962 common_phys_selectors_pex_by4_lanes 1963 [serdes_lane_hw_num]; 1964 if (serdes_type == PEX0) 1965 is_pex_x4 = 1; 1966 } 1967 1968 if (lane_data == NA) { 1969 printf 1970 ("%s: Warning: SerDes lane #%d and type %d are not supported together\n", 1971 __func__, serdes_lane_hw_num, serdes_mode); 1972 serdes_map[idx].serdes_type = DEFAULT_SERDES; 1973 printf("%s: SerDes lane #%d is disabled\n", __func__, 1974 serdes_lane_hw_num); 1975 continue; 1976 } 1977 1978 /* 1979 * Updating the data that will be written to 1980 * COMMON_PHYS_SELECTORS_REG 1981 */ 1982 reg_data |= (lane_data << 1983 (select_bit_off * serdes_lane_hw_num)); 1984 } 1985 1986 /* 1987 * Check that number of used lanes for XAUI and RXAUI 1988 * (if used) is right 1989 */ 1990 hws_serdes_xaui_topology_verify(); 1991 1992 /* Print topology */ 1993 if (updated_topology_print) 1994 print_topology_details(serdes_map, count); 1995 1996 /* 1997 * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS 1998 * register for PEXx4 mode 1999 */ 2000 reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0; 2001 2002 /* Updating the COMMON PHYS SELECTORS register */ 2003 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data); 2004 2005 return MV_OK; 2006 } 2007 2008 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, 2009 enum ref_clock ref_clock) 2010 { 2011 u32 data1 = 0, data2 = 0, data3 = 0, reg_data; 2012 2013 DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n"); 2014 2015 if (hws_is_serdes_active(serdes_num) != 1) { 2016 printf("%s: SerDes lane #%d is not Active\n", __func__, 2017 serdes_num); 2018 return MV_BAD_PARAM; 2019 } 2020 2021 switch (serdes_type) { 2022 case PEX0: 2023 case PEX1: 2024 case PEX2: 2025 case PEX3: 2026 switch (ref_clock) { 2027 case REF_CLOCK_25MHZ: 2028 CHECK_STATUS(mv_seq_exec 2029 (serdes_num, 2030 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ)); 2031 return MV_OK; 2032 case REF_CLOCK_100MHZ: 2033 CHECK_STATUS(mv_seq_exec 2034 (serdes_num, 2035 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ)); 2036 return MV_OK; 2037 #ifdef CONFIG_ARMADA_39X 2038 case REF_CLOCK_40MHZ: 2039 CHECK_STATUS(mv_seq_exec 2040 (serdes_num, 2041 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ)); 2042 return MV_OK; 2043 #endif 2044 default: 2045 printf 2046 ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n", 2047 __func__, ref_clock, serdes_num, serdes_type); 2048 return MV_BAD_PARAM; 2049 } 2050 case USB3_HOST0: 2051 case USB3_HOST1: 2052 case USB3_DEVICE: 2053 if (ref_clock == REF_CLOCK_25MHZ) { 2054 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2; 2055 data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL; 2056 data3 = LANE_CFG4_REG_25MHZ_VAL; 2057 } else if (ref_clock == REF_CLOCK_40MHZ) { 2058 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2059 data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL; 2060 data3 = LANE_CFG4_REG_40MHZ_VAL; 2061 } else { 2062 printf 2063 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2064 serdes_type); 2065 return MV_BAD_PARAM; 2066 } 2067 break; 2068 case SATA0: 2069 case SATA1: 2070 case SATA2: 2071 case SATA3: 2072 case SGMII0: 2073 case SGMII1: 2074 case SGMII2: 2075 case QSGMII: 2076 if (ref_clock == REF_CLOCK_25MHZ) { 2077 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1; 2078 } else if (ref_clock == REF_CLOCK_40MHZ) { 2079 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2080 } else { 2081 printf 2082 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2083 serdes_type); 2084 return MV_BAD_PARAM; 2085 } 2086 break; 2087 #ifdef CONFIG_ARMADA_39X 2088 case SGMII3: 2089 case XAUI: 2090 case RXAUI: 2091 if (ref_clock == REF_CLOCK_25MHZ) { 2092 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1; 2093 } else if (ref_clock == REF_CLOCK_40MHZ) { 2094 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; 2095 } else { 2096 printf 2097 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", 2098 serdes_type); 2099 return MV_BAD_PARAM; 2100 } 2101 break; 2102 #endif 2103 default: 2104 DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n"); 2105 return MV_BAD_PARAM; 2106 } 2107 2108 /* 2109 * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and 2110 * offset 2111 */ 2112 reg_data = reg_read(POWER_AND_PLL_CTRL_REG + 2113 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2114 reg_data &= POWER_AND_PLL_CTRL_REG_MASK; 2115 reg_data |= data1; 2116 reg_write(POWER_AND_PLL_CTRL_REG + 2117 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2118 2119 if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) || 2120 (serdes_type == USB3_DEVICE)) { 2121 reg_data = reg_read(GLOBAL_PM_CTRL + 2122 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2123 reg_data &= GLOBAL_PM_CTRL_REG_MASK; 2124 reg_data |= data2; 2125 reg_write(GLOBAL_PM_CTRL + 2126 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2127 2128 reg_data = reg_read(LANE_CFG4_REG + 2129 SERDES_REGS_LANE_BASE_OFFSET(serdes_num)); 2130 reg_data &= LANE_CFG4_REG_MASK; 2131 reg_data |= data3; 2132 reg_write(LANE_CFG4_REG + 2133 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data); 2134 } 2135 2136 return MV_OK; 2137 } 2138 2139 /* 2140 * hws_pex_tx_config_seq - 2141 * 2142 * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode 2143 * INPUT: serdes_map - The board topology map 2144 * OUTPUT: None 2145 * RETURNS: MV_OK - for success 2146 * MV_BAD_PARAM - for fail 2147 */ 2148 int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count) 2149 { 2150 enum serdes_mode serdes_mode; 2151 u32 serdes_lane_id, serdes_lane_hw_num; 2152 2153 DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n"); 2154 2155 /* 2156 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 2157 * configurations should run by setting each sequence for 2158 * all 4 lanes. 2159 */ 2160 2161 /* relese pipe soft reset for all lanes */ 2162 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2163 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2164 serdes_lane_hw_num = 2165 hws_get_physical_serdes_num(serdes_lane_id); 2166 2167 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2168 (serdes_mode == PEX_END_POINT_X4)) { 2169 CHECK_STATUS(mv_seq_exec 2170 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1)); 2171 } 2172 } 2173 2174 /* set phy soft reset for all lanes */ 2175 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2176 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2177 serdes_lane_hw_num = 2178 hws_get_physical_serdes_num(serdes_lane_id); 2179 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2180 (serdes_mode == PEX_END_POINT_X4)) { 2181 CHECK_STATUS(mv_seq_exec 2182 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2)); 2183 } 2184 } 2185 2186 /* set phy soft reset for all lanes */ 2187 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) { 2188 serdes_mode = serdes_map[serdes_lane_id].serdes_mode; 2189 serdes_lane_hw_num = 2190 hws_get_physical_serdes_num(serdes_lane_id); 2191 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) || 2192 (serdes_mode == PEX_END_POINT_X4)) { 2193 CHECK_STATUS(mv_seq_exec 2194 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3)); 2195 } 2196 } 2197 2198 return MV_OK; 2199 } 2200