1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _CTRL_PEX_H 8 #define _CTRL_PEX_H 9 10 #include "high_speed_env_spec.h" 11 12 /* Sample at Reset */ 13 #define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) 14 15 /* PCI Express Control and Status Registers */ 16 #define MAX_PEX_BUSSES 256 17 18 #define MISC_REGS_OFFSET 0x18200 19 #define MV_MISC_REGS_BASE MISC_REGS_OFFSET 20 #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) 21 22 #define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \ 23 (0x40000 + ((if) - 1) * 0x4000) : \ 24 0x80000) 25 #define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if)) 26 #define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60) 27 #define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90) 28 #define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00) 29 #define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04) 30 #define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64) 31 #define PEX_LINK_CAPABILITY_REG 0x6c 32 #define PEX_LINK_CTRL_STAT_REG 0x70 33 #define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ 34 #define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) 35 #define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ 36 #define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) 37 38 /* PEX_CAPABILITIES_REG fields */ 39 #define PCIE0_ENABLE_OFFS 0 40 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) 41 #define PCIE1_ENABLE_OFFS 1 42 #define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS) 43 #define PCIE2_ENABLE_OFFS 2 44 #define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS) 45 #define PCIE3_ENABLE_OFFS 3 46 #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS) 47 48 /* Controller revision info */ 49 #define PEX_DEVICE_AND_VENDOR_ID 0x000 50 51 /* PCI Express Configuration Address Register */ 52 #define PXCAR_REG_NUM_OFFS 2 53 #define PXCAR_REG_NUM_MAX 0x3f 54 #define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \ 55 PXCAR_REG_NUM_OFFS) 56 #define PXCAR_FUNC_NUM_OFFS 8 57 #define PXCAR_FUNC_NUM_MAX 0x7 58 #define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \ 59 PXCAR_FUNC_NUM_OFFS) 60 #define PXCAR_DEVICE_NUM_OFFS 11 61 #define PXCAR_DEVICE_NUM_MAX 0x1f 62 #define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \ 63 PXCAR_DEVICE_NUM_OFFS) 64 #define PXCAR_BUS_NUM_OFFS 16 65 #define PXCAR_BUS_NUM_MAX 0xff 66 #define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \ 67 PXCAR_BUS_NUM_OFFS) 68 #define PXCAR_EXT_REG_NUM_OFFS 24 69 #define PXCAR_EXT_REG_NUM_MAX 0xf 70 71 #define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8) 72 #define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc) 73 74 #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 75 #define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS) 76 77 #define PXCAR_CONFIG_EN BIT(31) 78 #define PEX_STATUS_AND_COMMAND 0x004 79 #define PXSAC_MABORT BIT(29) /* Recieved Master Abort */ 80 81 int hws_pex_config(const struct serdes_map *serdes_map, u8 count); 82 int pex_local_bus_num_set(u32 pex_if, u32 bus_num); 83 int pex_local_dev_num_set(u32 pex_if, u32 dev_num); 84 u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off); 85 86 void board_pex_config(void); 87 88 #endif 89