1 /* 2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada 3 * 370/XP, Dove, Orion5x and MV78xx0) 4 * 5 * Ported from the Barebox version to U-Boot by: 6 * Stefan Roese <sr@denx.de> 7 * 8 * The Barebox version is: 9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 10 * 11 * based on mbus driver from Linux 12 * (C) Copyright 2008 Marvell Semiconductor 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 * 16 * The Marvell EBU SoCs have a configurable physical address space: 17 * the physical address at which certain devices (PCIe, NOR, NAND, 18 * etc.) sit can be configured. The configuration takes place through 19 * two sets of registers: 20 * 21 * - One to configure the access of the CPU to the devices. Depending 22 * on the families, there are between 8 and 20 configurable windows, 23 * each can be use to create a physical memory window that maps to a 24 * specific device. Devices are identified by a tuple (target, 25 * attribute). 26 * 27 * - One to configure the access to the CPU to the SDRAM. There are 28 * either 2 (for Dove) or 4 (for other families) windows to map the 29 * SDRAM into the physical address space. 30 * 31 * This driver: 32 * 33 * - Reads out the SDRAM address decoding windows at initialization 34 * time, and fills the mbus_dram_info structure with these 35 * informations. The exported function mv_mbus_dram_info() allow 36 * device drivers to get those informations related to the SDRAM 37 * address decoding windows. This is because devices also have their 38 * own windows (configured through registers that are part of each 39 * device register space), and therefore the drivers for Marvell 40 * devices have to configure those device -> SDRAM windows to ensure 41 * that DMA works properly. 42 * 43 * - Provides an API for platform code or device drivers to 44 * dynamically add or remove address decoding windows for the CPU -> 45 * device accesses. This API is mvebu_mbus_add_window_by_id(), 46 * mvebu_mbus_add_window_remap_by_id() and 47 * mvebu_mbus_del_window(). 48 */ 49 50 #include <common.h> 51 #include <asm/errno.h> 52 #include <asm/io.h> 53 #include <asm/arch/cpu.h> 54 #include <asm/arch/soc.h> 55 #include <linux/mbus.h> 56 57 #define BIT(nr) (1UL << (nr)) 58 59 /* DDR target is the same on all platforms */ 60 #define TARGET_DDR 0 61 62 /* CPU Address Decode Windows registers */ 63 #define WIN_CTRL_OFF 0x0000 64 #define WIN_CTRL_ENABLE BIT(0) 65 #define WIN_CTRL_TGT_MASK 0xf0 66 #define WIN_CTRL_TGT_SHIFT 4 67 #define WIN_CTRL_ATTR_MASK 0xff00 68 #define WIN_CTRL_ATTR_SHIFT 8 69 #define WIN_CTRL_SIZE_MASK 0xffff0000 70 #define WIN_CTRL_SIZE_SHIFT 16 71 #define WIN_BASE_OFF 0x0004 72 #define WIN_BASE_LOW 0xffff0000 73 #define WIN_BASE_HIGH 0xf 74 #define WIN_REMAP_LO_OFF 0x0008 75 #define WIN_REMAP_LOW 0xffff0000 76 #define WIN_REMAP_HI_OFF 0x000c 77 78 #define ATTR_HW_COHERENCY (0x1 << 4) 79 80 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 81 #define DDR_BASE_CS_HIGH_MASK 0xf 82 #define DDR_BASE_CS_LOW_MASK 0xff000000 83 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 84 #define DDR_SIZE_ENABLED BIT(0) 85 #define DDR_SIZE_CS_MASK 0x1c 86 #define DDR_SIZE_CS_SHIFT 2 87 #define DDR_SIZE_MASK 0xff000000 88 89 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) 90 91 struct mvebu_mbus_state; 92 93 struct mvebu_mbus_soc_data { 94 unsigned int num_wins; 95 unsigned int num_remappable_wins; 96 unsigned int (*win_cfg_offset)(const int win); 97 void (*setup_cpu_target)(struct mvebu_mbus_state *s); 98 }; 99 100 struct mvebu_mbus_state mbus_state 101 __attribute__ ((section(".data"))); 102 static struct mbus_dram_target_info mbus_dram_info 103 __attribute__ ((section(".data"))); 104 105 /* 106 * Functions to manipulate the address decoding windows 107 */ 108 109 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, 110 int win, int *enabled, u64 *base, 111 u32 *size, u8 *target, u8 *attr, 112 u64 *remap) 113 { 114 void __iomem *addr = mbus->mbuswins_base + 115 mbus->soc->win_cfg_offset(win); 116 u32 basereg = readl(addr + WIN_BASE_OFF); 117 u32 ctrlreg = readl(addr + WIN_CTRL_OFF); 118 119 if (!(ctrlreg & WIN_CTRL_ENABLE)) { 120 *enabled = 0; 121 return; 122 } 123 124 *enabled = 1; 125 *base = ((u64)basereg & WIN_BASE_HIGH) << 32; 126 *base |= (basereg & WIN_BASE_LOW); 127 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; 128 129 if (target) 130 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; 131 132 if (attr) 133 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; 134 135 if (remap) { 136 if (win < mbus->soc->num_remappable_wins) { 137 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF); 138 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF); 139 *remap = ((u64)remap_hi << 32) | remap_low; 140 } else { 141 *remap = 0; 142 } 143 } 144 } 145 146 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, 147 int win) 148 { 149 void __iomem *addr; 150 151 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); 152 153 writel(0, addr + WIN_BASE_OFF); 154 writel(0, addr + WIN_CTRL_OFF); 155 if (win < mbus->soc->num_remappable_wins) { 156 writel(0, addr + WIN_REMAP_LO_OFF); 157 writel(0, addr + WIN_REMAP_HI_OFF); 158 } 159 } 160 161 /* Checks whether the given window number is available */ 162 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, 163 const int win) 164 { 165 void __iomem *addr = mbus->mbuswins_base + 166 mbus->soc->win_cfg_offset(win); 167 u32 ctrl = readl(addr + WIN_CTRL_OFF); 168 return !(ctrl & WIN_CTRL_ENABLE); 169 } 170 171 /* 172 * Checks whether the given (base, base+size) area doesn't overlap an 173 * existing region 174 */ 175 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, 176 phys_addr_t base, size_t size, 177 u8 target, u8 attr) 178 { 179 u64 end = (u64)base + size; 180 int win; 181 182 for (win = 0; win < mbus->soc->num_wins; win++) { 183 u64 wbase, wend; 184 u32 wsize; 185 u8 wtarget, wattr; 186 int enabled; 187 188 mvebu_mbus_read_window(mbus, win, 189 &enabled, &wbase, &wsize, 190 &wtarget, &wattr, NULL); 191 192 if (!enabled) 193 continue; 194 195 wend = wbase + wsize; 196 197 /* 198 * Check if the current window overlaps with the 199 * proposed physical range 200 */ 201 if ((u64)base < wend && end > wbase) 202 return 0; 203 204 /* 205 * Check if target/attribute conflicts 206 */ 207 if (target == wtarget && attr == wattr) 208 return 0; 209 } 210 211 return 1; 212 } 213 214 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, 215 phys_addr_t base, size_t size) 216 { 217 int win; 218 219 for (win = 0; win < mbus->soc->num_wins; win++) { 220 u64 wbase; 221 u32 wsize; 222 int enabled; 223 224 mvebu_mbus_read_window(mbus, win, 225 &enabled, &wbase, &wsize, 226 NULL, NULL, NULL); 227 228 if (!enabled) 229 continue; 230 231 if (base == wbase && size == wsize) 232 return win; 233 } 234 235 return -ENODEV; 236 } 237 238 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, 239 int win, phys_addr_t base, size_t size, 240 phys_addr_t remap, u8 target, 241 u8 attr) 242 { 243 void __iomem *addr = mbus->mbuswins_base + 244 mbus->soc->win_cfg_offset(win); 245 u32 ctrl, remap_addr; 246 247 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | 248 (attr << WIN_CTRL_ATTR_SHIFT) | 249 (target << WIN_CTRL_TGT_SHIFT) | 250 WIN_CTRL_ENABLE; 251 252 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); 253 writel(ctrl, addr + WIN_CTRL_OFF); 254 if (win < mbus->soc->num_remappable_wins) { 255 if (remap == MVEBU_MBUS_NO_REMAP) 256 remap_addr = base; 257 else 258 remap_addr = remap; 259 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF); 260 writel(0, addr + WIN_REMAP_HI_OFF); 261 } 262 263 return 0; 264 } 265 266 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, 267 phys_addr_t base, size_t size, 268 phys_addr_t remap, u8 target, 269 u8 attr) 270 { 271 int win; 272 273 if (remap == MVEBU_MBUS_NO_REMAP) { 274 for (win = mbus->soc->num_remappable_wins; 275 win < mbus->soc->num_wins; win++) 276 if (mvebu_mbus_window_is_free(mbus, win)) 277 return mvebu_mbus_setup_window(mbus, win, base, 278 size, remap, 279 target, attr); 280 } 281 282 283 for (win = 0; win < mbus->soc->num_wins; win++) 284 if (mvebu_mbus_window_is_free(mbus, win)) 285 return mvebu_mbus_setup_window(mbus, win, base, size, 286 remap, target, attr); 287 288 return -ENOMEM; 289 } 290 291 /* 292 * SoC-specific functions and definitions 293 */ 294 295 static unsigned int armada_370_xp_mbus_win_offset(int win) 296 { 297 /* The register layout is a bit annoying and the below code 298 * tries to cope with it. 299 * - At offset 0x0, there are the registers for the first 8 300 * windows, with 4 registers of 32 bits per window (ctrl, 301 * base, remap low, remap high) 302 * - Then at offset 0x80, there is a hole of 0x10 bytes for 303 * the internal registers base address and internal units 304 * sync barrier register. 305 * - Then at offset 0x90, there the registers for 12 306 * windows, with only 2 registers of 32 bits per window 307 * (ctrl, base). 308 */ 309 if (win < 8) 310 return win << 4; 311 else 312 return 0x90 + ((win - 8) << 3); 313 } 314 315 static unsigned int orion5x_mbus_win_offset(int win) 316 { 317 return win << 4; 318 } 319 320 static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) 321 { 322 int i; 323 int cs; 324 325 mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 326 327 for (i = 0, cs = 0; i < 4; i++) { 328 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); 329 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); 330 331 /* 332 * We only take care of entries for which the chip 333 * select is enabled, and that don't have high base 334 * address bits set (devices can only access the first 335 * 32 bits of the memory). 336 */ 337 if ((size & DDR_SIZE_ENABLED) && 338 !(base & DDR_BASE_CS_HIGH_MASK)) { 339 struct mbus_dram_window *w; 340 341 w = &mbus_dram_info.cs[cs++]; 342 w->cs_index = i; 343 w->mbus_attr = 0xf & ~(1 << i); 344 w->base = base & DDR_BASE_CS_LOW_MASK; 345 w->size = (size | ~DDR_SIZE_MASK) + 1; 346 } 347 } 348 mbus_dram_info.num_cs = cs; 349 } 350 351 static const struct mvebu_mbus_soc_data 352 armada_370_xp_mbus_data __maybe_unused = { 353 .num_wins = 20, 354 .num_remappable_wins = 8, 355 .win_cfg_offset = armada_370_xp_mbus_win_offset, 356 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 357 }; 358 359 static const struct mvebu_mbus_soc_data 360 kirkwood_mbus_data __maybe_unused = { 361 .num_wins = 8, 362 .num_remappable_wins = 4, 363 .win_cfg_offset = orion5x_mbus_win_offset, 364 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 365 }; 366 367 /* 368 * Public API of the driver 369 */ 370 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) 371 { 372 return &mbus_dram_info; 373 } 374 375 int mvebu_mbus_add_window_remap_by_id(unsigned int target, 376 unsigned int attribute, 377 phys_addr_t base, size_t size, 378 phys_addr_t remap) 379 { 380 struct mvebu_mbus_state *s = &mbus_state; 381 382 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { 383 printf("Cannot add window '%x:%x', conflicts with another window\n", 384 target, attribute); 385 return -EINVAL; 386 } 387 388 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); 389 } 390 391 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, 392 phys_addr_t base, size_t size) 393 { 394 return mvebu_mbus_add_window_remap_by_id(target, attribute, base, 395 size, MVEBU_MBUS_NO_REMAP); 396 } 397 398 int mvebu_mbus_del_window(phys_addr_t base, size_t size) 399 { 400 int win; 401 402 win = mvebu_mbus_find_window(&mbus_state, base, size); 403 if (win < 0) 404 return win; 405 406 mvebu_mbus_disable_window(&mbus_state, win); 407 return 0; 408 } 409 410 int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, 411 u32 base, u32 size, u8 target, u8 attr) 412 { 413 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { 414 printf("Cannot add window '%04x:%04x', conflicts with another window\n", 415 target, attr); 416 return -EBUSY; 417 } 418 419 /* 420 * In U-Boot we first try to add the mbus window to the remap windows. 421 * If this fails, lets try to add the windows to the non-remap windows. 422 */ 423 if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) { 424 if (mvebu_mbus_alloc_window(mbus, base, size, 425 MVEBU_MBUS_NO_REMAP, target, attr)) 426 return -ENOMEM; 427 } 428 429 return 0; 430 } 431 432 int mvebu_mbus_probe(struct mbus_win windows[], int count) 433 { 434 int win; 435 int ret; 436 int i; 437 438 #if defined(CONFIG_KIRKWOOD) 439 mbus_state.soc = &kirkwood_mbus_data; 440 #endif 441 #if defined(CONFIG_ARMADA_XP) 442 mbus_state.soc = &armada_370_xp_mbus_data; 443 #endif 444 445 mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE; 446 mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE; 447 448 for (win = 0; win < mbus_state.soc->num_wins; win++) 449 mvebu_mbus_disable_window(&mbus_state, win); 450 451 mbus_state.soc->setup_cpu_target(&mbus_state); 452 453 /* Setup statically declared windows in the DT */ 454 for (i = 0; i < count; i++) { 455 u32 base, size; 456 u8 target, attr; 457 458 target = windows[i].target; 459 attr = windows[i].attr; 460 base = windows[i].base; 461 size = windows[i].size; 462 ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr); 463 if (ret < 0) 464 return ret; 465 } 466 467 return 0; 468 } 469