1/*
2 * SPDX-License-Identifier:	GPL-2.0+
3 */
4
5#include <config.h>
6#include <linux/linkage.h>
7
8#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
9ENTRY(save_boot_params)
10	stmfd	sp!, {r0 - r12, lr}	/* @ save registers on stack */
11	ldr	r12, =CONFIG_SPL_BOOTROM_SAVE
12	str	sp, [r12]
13	b	save_boot_params_ret
14ENDPROC(save_boot_params)
15
16ENTRY(return_to_bootrom)
17	ldr	r12, =CONFIG_SPL_BOOTROM_SAVE
18	ldr	sp, [r12]
19	mov	r0, #0x0		/* @ return value: 0x0 NO_ERR */
20	ldmfd	sp!, {r0 - r12, pc}	/* @ restore regs and return */
21ENDPROC(return_to_bootrom)
22#else
23ENTRY(save_boot_params)
24	b	save_boot_params_ret
25ENDPROC(save_boot_params)
26#endif
27
28/*
29 * cache_inv - invalidate Cache line
30 * r0 - dest
31 */
32	.global cache_inv
33	.type  cache_inv, %function
34	cache_inv:
35
36	stmfd   sp!, {r1-r12}
37
38	mcr     p15, 0, r0, c7, c6, 1
39
40	ldmfd   sp!, {r1-r12}
41	bx      lr
42
43
44/*
45 * flush_l1_v6 - l1 cache clean invalidate
46 * r0 - dest
47 */
48	.global flush_l1_v6
49	.type	flush_l1_v6, %function
50	flush_l1_v6:
51
52	stmfd   sp!, {r1-r12}
53
54	mcr     p15, 0, r0, c7, c10, 5	/* @ data memory barrier */
55	mcr     p15, 0, r0, c7, c14, 1	/* @ clean & invalidate D line */
56	mcr     p15, 0, r0, c7, c10, 4	/* @ data sync barrier */
57
58	ldmfd   sp!, {r1-r12}
59	bx      lr
60
61
62/*
63 * flush_l1_v7 - l1 cache clean invalidate
64 * r0 - dest
65 */
66	.global flush_l1_v7
67	.type	flush_l1_v7, %function
68	flush_l1_v7:
69
70	stmfd   sp!, {r1-r12}
71
72	dmb				/* @data memory barrier */
73	mcr     p15, 0, r0, c7, c14, 1	/* @ clean & invalidate D line */
74	dsb				/* @data sync barrier */
75
76	ldmfd   sp!, {r1-r12}
77	bx      lr
78