1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * Header file for the Marvell's Feroceon CPU core.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _MVEBU_SOC_H
12 #define _MVEBU_SOC_H
13 
14 #define SOC_MV78460_ID		0x7846
15 #define SOC_88F6810_ID		0x6810
16 #define SOC_88F6820_ID		0x6820
17 #define SOC_88F6828_ID		0x6828
18 
19 /* A38x revisions */
20 #define MV_88F68XX_Z1_ID	0x0
21 #define MV_88F68XX_A0_ID	0x4
22 
23 /* TCLK Core Clock definition */
24 #ifndef CONFIG_SYS_TCLK
25 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
26 #endif
27 
28 /* Armada XP PLL frequency (used for NAND clock generation) */
29 #define CONFIG_SYS_MVEBU_PLL_CLOCK	2000000000
30 
31 /* SOC specific definations */
32 #define INTREG_BASE		0xd0000000
33 #define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
34 #if defined(CONFIG_SPL_BUILD)
35 /*
36  * On A38x switching the regs base address without running from
37  * SDRAM doesn't seem to work. So let the SPL still use the
38  * default base address and switch to the new address in the
39  * main u-boot later.
40  */
41 #define SOC_REGS_PHY_BASE	0xd0000000
42 #else
43 #define SOC_REGS_PHY_BASE	0xf1000000
44 #endif
45 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
46 
47 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
48 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
49 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
50 #define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
51 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
52 #define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
53 #define MVEBU_UART1_BASE	(MVEBU_REGISTER(0x12100))
54 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
55 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
56 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
57 #define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
58 #define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
59 #define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
60 #define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
61 #define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
62 #define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
63 #define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
64 #define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
65 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
66 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
67 #define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
68 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
69 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
70 #define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
71 #define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
72 #define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
73 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
74 
75 #define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
76 #define MBUS_ERR_PROP_EN	(1 << 8)
77 
78 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
79 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
80 
81 #define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
82 #define NAND_EN			BIT(0)
83 #define NAND_ARBITER_EN		BIT(27)
84 
85 #define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
86 #define GE0_PUP_EN		BIT(0)
87 #define GE1_PUP_EN		BIT(1)
88 #define LCD_PUP_EN		BIT(2)
89 #define NAND_PUP_EN		BIT(4)
90 #define SPI_PUP_EN		BIT(5)
91 
92 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
93 #define NAND_ECC_DIVCKL_RATIO_OFFS	8
94 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
95 
96 #define SDRAM_MAX_CS		4
97 #define SDRAM_ADDR_MASK		0xFF000000
98 
99 /* MVEBU CPU memory windows */
100 #define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
101 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
102 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
103 
104 #endif /* _MVEBU_SOC_H */
105