1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * Header file for the Marvell's Feroceon CPU core.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _MVEBU_SOC_H
12 #define _MVEBU_SOC_H
13 
14 #define SOC_MV78260_ID		0x7826
15 #define SOC_MV78460_ID		0x7846
16 #define SOC_88F6810_ID		0x6810
17 #define SOC_88F6820_ID		0x6820
18 #define SOC_88F6828_ID		0x6828
19 
20 /* A38x revisions */
21 #define MV_88F68XX_Z1_ID	0x0
22 #define MV_88F68XX_A0_ID	0x4
23 
24 /* TCLK Core Clock definition */
25 #ifndef CONFIG_SYS_TCLK
26 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
27 #endif
28 
29 /* Armada XP PLL frequency (used for NAND clock generation) */
30 #define CONFIG_SYS_MVEBU_PLL_CLOCK	2000000000
31 
32 /* SOC specific definations */
33 #define INTREG_BASE		0xd0000000
34 #define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
35 #if defined(CONFIG_SPL_BUILD)
36 /*
37  * The SPL U-Boot version still runs with the default
38  * address for the internal registers, configured by
39  * the BootROM. Only the main U-Boot version uses the
40  * new internal register base address, that also is
41  * required for the Linux kernel.
42  */
43 #define SOC_REGS_PHY_BASE	0xd0000000
44 #else
45 #define SOC_REGS_PHY_BASE	0xf1000000
46 #endif
47 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
48 
49 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
50 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
51 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
52 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
53 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
54 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
55 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
56 #define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
57 #define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
58 #define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
59 #define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
60 #define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
61 #define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
62 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
63 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
64 #define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
65 #define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
66 #define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
67 #define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
68 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
69 
70 #define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
71 #define MBUS_ERR_PROP_EN	(1 << 8)
72 
73 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
74 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
75 
76 #define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
77 #define NAND_EN			BIT(0)
78 #define NAND_ARBITER_EN		BIT(27)
79 
80 #define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
81 #define GE0_PUP_EN		BIT(0)
82 #define GE1_PUP_EN		BIT(1)
83 #define LCD_PUP_EN		BIT(2)
84 #define NAND_PUP_EN		BIT(4)
85 #define SPI_PUP_EN		BIT(5)
86 
87 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
88 #define NAND_ECC_DIVCKL_RATIO_OFFS	8
89 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
90 
91 #define SDRAM_MAX_CS		4
92 #define SDRAM_ADDR_MASK		0xFF000000
93 
94 /* MVEBU CPU memory windows */
95 #define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
96 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
97 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
98 
99 #endif /* _MVEBU_SOC_H */
100