1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * Header file for the Marvell's Feroceon CPU core.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _MVEBU_SOC_H
12 #define _MVEBU_SOC_H
13 
14 #define SOC_MV78230_ID		0x7823
15 #define SOC_MV78260_ID		0x7826
16 #define SOC_MV78460_ID		0x7846
17 #define SOC_88F6720_ID		0x6720
18 #define SOC_88F6810_ID		0x6810
19 #define SOC_88F6820_ID		0x6820
20 #define SOC_88F6828_ID		0x6828
21 #define SOC_98DX3236_ID		0xf410
22 #define SOC_98DX3336_ID		0xf400
23 #define SOC_98DX4251_ID		0xfc00
24 
25 /* A375 revisions */
26 #define MV_88F67XX_A0_ID	0x3
27 
28 /* A38x revisions */
29 #define MV_88F68XX_Z1_ID	0x0
30 #define MV_88F68XX_A0_ID	0x4
31 
32 /* TCLK Core Clock definition */
33 #ifndef CONFIG_SYS_TCLK
34 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
35 #endif
36 
37 /* SOC specific definations */
38 #define INTREG_BASE		0xd0000000
39 #define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
40 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
41 /*
42  * The SPL U-Boot version still runs with the default
43  * address for the internal registers, configured by
44  * the BootROM. Only the main U-Boot version uses the
45  * new internal register base address, that also is
46  * required for the Linux kernel.
47  */
48 #define SOC_REGS_PHY_BASE	0xd0000000
49 #elif defined(CONFIG_ARMADA_8K)
50 #define SOC_REGS_PHY_BASE	0xf0000000
51 #else
52 #define SOC_REGS_PHY_BASE	0xf1000000
53 #endif
54 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
55 
56 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
57 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
58 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
59 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
60 #define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
61 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
62 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
63 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
64 #define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
65 #define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
66 #define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
67 #define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
68 #define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
69 #define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
70 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
71 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
72 #define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
73 #define MVEBU_REG_PCIE0_BASE	(MVEBU_REGISTER(0x80000))
74 #define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
75 #define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
76 #define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
77 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
78 #define MVEBU_LCD_BASE		(MVEBU_REGISTER(0xe0000))
79 #define MVEBU_DFX_BASE		(MVEBU_REGISTER(0xe4000))
80 
81 #define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
82 #define MBUS_ERR_PROP_EN	(1 << 8)
83 
84 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
85 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
86 
87 #define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
88 #define NAND_EN			BIT(0)
89 #define NAND_ARBITER_EN		BIT(27)
90 
91 #define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
92 #define GE0_PUP_EN		BIT(0)
93 #define GE1_PUP_EN		BIT(1)
94 #define LCD_PUP_EN		BIT(2)
95 #define NAND_PUP_EN		BIT(4)
96 #define SPI_PUP_EN		BIT(5)
97 
98 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
99 #define MVEBU_DFX_DIV_CLK_CTRL(i)	(MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
100 #define NAND_ECC_DIVCKL_RATIO_OFFS	8
101 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
102 
103 #define SDRAM_MAX_CS		4
104 #define SDRAM_ADDR_MASK		0xFF000000
105 
106 /* MVEBU CPU memory windows */
107 #define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
108 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
109 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
110 
111 #define COMPHY_REFCLK_ALIGNMENT	(MVEBU_REGISTER(0x182f8))
112 
113 /* BootROM error register (also includes some status infos) */
114 #if defined(CONFIG_ARMADA_38X)
115 #define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
116 #define BOOTROM_ERR_MODE_OFFS	0
117 #define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
118 #else
119 #define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
120 #define BOOTROM_ERR_MODE_OFFS	28
121 #define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
122 #define BOOTROM_ERR_MODE_UART	0x6
123 #endif
124 
125 #if defined(CONFIG_ARMADA_375)
126 /* SAR values for Armada 375 */
127 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0xe8200))
128 #define CONFIG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
129 
130 #define SAR_CPU_FREQ_OFFS	17
131 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
132 
133 #define BOOT_DEV_SEL_OFFS	3
134 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
135 
136 #define BOOT_FROM_UART		0x30
137 #define BOOT_FROM_SPI		0x38
138 #elif defined(CONFIG_ARMADA_38X)
139 /* SAR values for Armada 38x */
140 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18600))
141 
142 #define SAR_CPU_FREQ_OFFS	10
143 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
144 #define SAR_BOOT_DEVICE_OFFS	4
145 #define SAR_BOOT_DEVICE_MASK	(0x1f << SAR_BOOT_DEVICE_OFFS)
146 
147 #define BOOT_DEV_SEL_OFFS	4
148 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
149 
150 #define BOOT_FROM_NAND		0x0A
151 #define BOOT_FROM_UART		0x28
152 #define BOOT_FROM_UART_ALT	0x3f
153 #define BOOT_FROM_SPI		0x32
154 #define BOOT_FROM_MMC		0x30
155 #define BOOT_FROM_MMC_ALT	0x31
156 #else
157 /* SAR values for Armada XP */
158 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
159 #define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))
160 
161 #define SAR_CPU_FREQ_OFFS	21
162 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
163 #define SAR_FFC_FREQ_OFFS	24
164 #define SAR_FFC_FREQ_MASK	(0xf << SAR_FFC_FREQ_OFFS)
165 #define SAR2_CPU_FREQ_OFFS	20
166 #define SAR2_CPU_FREQ_MASK	(0x1 << SAR2_CPU_FREQ_OFFS)
167 #define SAR_BOOT_DEVICE_OFFS	5
168 #define SAR_BOOT_DEVICE_MASK	(0xf << SAR_BOOT_DEVICE_OFFS)
169 
170 #define BOOT_DEV_SEL_OFFS	5
171 #define BOOT_DEV_SEL_MASK	(0xf << BOOT_DEV_SEL_OFFS)
172 
173 #define BOOT_FROM_UART		0x2
174 #define BOOT_FROM_SPI		0x3
175 #endif
176 
177 #endif /* _MVEBU_SOC_H */
178