1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * Header file for the Marvell's Feroceon CPU core. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _MVEBU_SOC_H 12 #define _MVEBU_SOC_H 13 14 #define SOC_MV78230_ID 0x7823 15 #define SOC_MV78260_ID 0x7826 16 #define SOC_MV78460_ID 0x7846 17 #define SOC_88F6720_ID 0x6720 18 #define SOC_88F6810_ID 0x6810 19 #define SOC_88F6820_ID 0x6820 20 #define SOC_88F6828_ID 0x6828 21 22 /* A375 revisions */ 23 #define MV_88F67XX_A0_ID 0x3 24 25 /* A38x revisions */ 26 #define MV_88F68XX_Z1_ID 0x0 27 #define MV_88F68XX_A0_ID 0x4 28 29 /* TCLK Core Clock definition */ 30 #ifndef CONFIG_SYS_TCLK 31 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 32 #endif 33 34 /* Armada XP PLL frequency (used for NAND clock generation) */ 35 #define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000 36 37 /* SOC specific definations */ 38 #define INTREG_BASE 0xd0000000 39 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) 40 #if defined(CONFIG_SPL_BUILD) 41 /* 42 * The SPL U-Boot version still runs with the default 43 * address for the internal registers, configured by 44 * the BootROM. Only the main U-Boot version uses the 45 * new internal register base address, that also is 46 * required for the Linux kernel. 47 */ 48 #define SOC_REGS_PHY_BASE 0xd0000000 49 #else 50 #define SOC_REGS_PHY_BASE 0xf1000000 51 #endif 52 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) 53 54 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) 55 #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) 56 #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE 57 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) 58 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) 59 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) 60 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) 61 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) 62 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) 63 #define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700)) 64 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) 65 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) 66 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) 67 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) 68 #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) 69 #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) 70 #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) 71 #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) 72 #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) 73 #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) 74 #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) 75 76 #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) 77 #define MBUS_ERR_PROP_EN (1 << 8) 78 79 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) 80 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) 81 82 #define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08) 83 #define NAND_EN BIT(0) 84 #define NAND_ARBITER_EN BIT(27) 85 86 #define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c) 87 #define GE0_PUP_EN BIT(0) 88 #define GE1_PUP_EN BIT(1) 89 #define LCD_PUP_EN BIT(2) 90 #define NAND_PUP_EN BIT(4) 91 #define SPI_PUP_EN BIT(5) 92 93 #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) 94 #define NAND_ECC_DIVCKL_RATIO_OFFS 8 95 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) 96 97 #define SDRAM_MAX_CS 4 98 #define SDRAM_ADDR_MASK 0xFF000000 99 100 /* MVEBU CPU memory windows */ 101 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA 102 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE 103 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE 104 105 #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) 106 107 /* BootROM error register (also includes some status infos) */ 108 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) 109 #define BOOTROM_ERR_MODE_OFFS 28 110 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) 111 #define BOOTROM_ERR_MODE_UART 0x6 112 113 #if defined(CONFIG_ARMADA_375) 114 /* SAR values for Armada 375 */ 115 #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) 116 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) 117 118 #define SAR_CPU_FREQ_OFFS 17 119 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 120 121 #define BOOT_DEV_SEL_OFFS 3 122 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 123 124 #define BOOT_FROM_UART 0x30 125 #define BOOT_FROM_SPI 0x38 126 #elif defined(CONFIG_ARMADA_38X) 127 /* SAR values for Armada 38x */ 128 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) 129 130 #define SAR_CPU_FREQ_OFFS 10 131 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 132 #define SAR_BOOT_DEVICE_OFFS 4 133 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) 134 135 #define BOOT_DEV_SEL_OFFS 4 136 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 137 138 #define BOOT_FROM_UART 0x28 139 #define BOOT_FROM_SPI 0x32 140 #define BOOT_FROM_MMC 0x30 141 #define BOOT_FROM_MMC_ALT 0x31 142 #else 143 /* SAR values for Armada XP */ 144 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) 145 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) 146 147 #define SAR_CPU_FREQ_OFFS 21 148 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 149 #define SAR_FFC_FREQ_OFFS 24 150 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) 151 #define SAR2_CPU_FREQ_OFFS 20 152 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) 153 #define SAR_BOOT_DEVICE_OFFS 5 154 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) 155 156 #define BOOT_DEV_SEL_OFFS 5 157 #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) 158 159 #define BOOT_FROM_UART 0x2 160 #define BOOT_FROM_SPI 0x3 161 #endif 162 163 #endif /* _MVEBU_SOC_H */ 164