1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 */ 7 8 #ifndef _MVEBU_CPU_H 9 #define _MVEBU_CPU_H 10 11 #include <asm/system.h> 12 13 #ifndef __ASSEMBLY__ 14 15 #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 16 #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 17 18 enum memory_bank { 19 BANK0, 20 BANK1, 21 BANK2, 22 BANK3 23 }; 24 25 enum cpu_winen { 26 CPU_WIN_DISABLE, 27 CPU_WIN_ENABLE 28 }; 29 30 enum cpu_target { 31 CPU_TARGET_DRAM = 0x0, 32 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 33 CPU_TARGET_ETH23 = 0x3, 34 CPU_TARGET_PCIE02 = 0x4, 35 CPU_TARGET_ETH01 = 0x7, 36 CPU_TARGET_PCIE13 = 0x8, 37 CPU_TARGET_SASRAM = 0x9, 38 CPU_TARGET_SATA01 = 0xa, /* A38X */ 39 CPU_TARGET_NAND = 0xd, 40 CPU_TARGET_SATA23_DFX = 0xe, /* A38X */ 41 }; 42 43 enum cpu_attrib { 44 CPU_ATTR_SASRAM = 0x01, 45 CPU_ATTR_DRAM_CS0 = 0x0e, 46 CPU_ATTR_DRAM_CS1 = 0x0d, 47 CPU_ATTR_DRAM_CS2 = 0x0b, 48 CPU_ATTR_DRAM_CS3 = 0x07, 49 CPU_ATTR_NANDFLASH = 0x2f, 50 CPU_ATTR_SPIFLASH = 0x1e, 51 CPU_ATTR_SPI0_CS0 = 0x1e, 52 CPU_ATTR_SPI0_CS1 = 0x5e, 53 CPU_ATTR_SPI1_CS2 = 0x9a, 54 CPU_ATTR_BOOTROM = 0x1d, 55 CPU_ATTR_PCIE_IO = 0xe0, 56 CPU_ATTR_PCIE_MEM = 0xe8, 57 CPU_ATTR_DEV_CS0 = 0x3e, 58 CPU_ATTR_DEV_CS1 = 0x3d, 59 CPU_ATTR_DEV_CS2 = 0x3b, 60 CPU_ATTR_DEV_CS3 = 0x37, 61 }; 62 63 enum { 64 MVEBU_SOC_AXP, 65 MVEBU_SOC_A375, 66 MVEBU_SOC_A38X, 67 MVEBU_SOC_MSYS, 68 MVEBU_SOC_UNKNOWN, 69 }; 70 71 #define MVEBU_SDRAM_SIZE_MAX 0xc0000000 72 73 /* 74 * Default Device Address MAP BAR values 75 */ 76 #define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX 77 #define MBUS_PCI_MEM_SIZE (128 << 20) 78 #define MBUS_PCI_IO_BASE 0xF1100000 79 #define MBUS_PCI_IO_SIZE (64 << 10) 80 #define MBUS_SPI_BASE 0xF4000000 81 #define MBUS_SPI_SIZE (8 << 20) 82 #define MBUS_BOOTROM_BASE 0xF8000000 83 #define MBUS_BOOTROM_SIZE (8 << 20) 84 85 struct mbus_win { 86 u32 base; 87 u32 size; 88 u8 target; 89 u8 attr; 90 }; 91 92 /* 93 * System registers 94 * Ref: Datasheet sec:A.28 95 */ 96 struct mvebu_system_registers { 97 #if defined(CONFIG_ARMADA_375) 98 u8 pad1[0x54]; 99 #else 100 u8 pad1[0x60]; 101 #endif 102 u32 rstoutn_mask; /* 0x60 */ 103 u32 sys_soft_rst; /* 0x64 */ 104 }; 105 106 /* 107 * GPIO Registers 108 * Ref: Datasheet sec:A.19 109 */ 110 struct kwgpio_registers { 111 u32 dout; 112 u32 oe; 113 u32 blink_en; 114 u32 din_pol; 115 u32 din; 116 u32 irq_cause; 117 u32 irq_mask; 118 u32 irq_level; 119 }; 120 121 struct sar_freq_modes { 122 u8 val; 123 u8 ffc; /* Fabric Frequency Configuration */ 124 u32 p_clk; 125 u32 nb_clk; 126 u32 d_clk; 127 }; 128 129 /* Needed for dynamic (board-specific) mbus configuration */ 130 extern struct mvebu_mbus_state mbus_state; 131 132 /* 133 * functions 134 */ 135 unsigned int mvebu_sdram_bar(enum memory_bank bank); 136 unsigned int mvebu_sdram_bs(enum memory_bank bank); 137 void mvebu_sdram_size_adjust(enum memory_bank bank); 138 int mvebu_mbus_probe(struct mbus_win windows[], int count); 139 int mvebu_soc_family(void); 140 u32 mvebu_get_nand_clock(void); 141 142 void return_to_bootrom(void); 143 144 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 145 146 void get_sar_freq(struct sar_freq_modes *sar_freq); 147 148 /* 149 * Highspeed SERDES PHY config init, ported from bin_hdr 150 * to mainline U-Boot 151 */ 152 int serdes_phy_config(void); 153 154 /* 155 * DDR3 init / training code ported from Marvell bin_hdr. Now 156 * available in mainline U-Boot in: 157 * drivers/ddr/marvell 158 */ 159 int ddr3_init(void); 160 161 struct mvebu_lcd_info { 162 u32 fb_base; 163 int x_res; 164 int y_res; 165 int x_fp; /* frontporch */ 166 int y_fp; 167 int x_bp; /* backporch */ 168 int y_bp; 169 }; 170 171 int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info); 172 173 /* 174 * get_ref_clk 175 * 176 * return: reference clock in MHz (25 or 40) 177 */ 178 u32 get_ref_clk(void); 179 180 #endif /* __ASSEMBLY__ */ 181 #endif /* _MVEBU_CPU_H */ 182