1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef _MVEBU_CPU_H
10 #define _MVEBU_CPU_H
11 
12 #include <asm/system.h>
13 
14 #ifndef __ASSEMBLY__
15 
16 #define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
17 #define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
18 
19 enum memory_bank {
20 	BANK0,
21 	BANK1,
22 	BANK2,
23 	BANK3
24 };
25 
26 enum cpu_winen {
27 	CPU_WIN_DISABLE,
28 	CPU_WIN_ENABLE
29 };
30 
31 enum cpu_target {
32 	CPU_TARGET_DRAM = 0x0,
33 	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
34 	CPU_TARGET_ETH23 = 0x3,
35 	CPU_TARGET_PCIE02 = 0x4,
36 	CPU_TARGET_ETH01 = 0x7,
37 	CPU_TARGET_PCIE13 = 0x8,
38 	CPU_TARGET_SASRAM = 0x9,
39 	CPU_TARGET_NAND = 0xd,
40 };
41 
42 enum cpu_attrib {
43 	CPU_ATTR_SASRAM = 0x01,
44 	CPU_ATTR_DRAM_CS0 = 0x0e,
45 	CPU_ATTR_DRAM_CS1 = 0x0d,
46 	CPU_ATTR_DRAM_CS2 = 0x0b,
47 	CPU_ATTR_DRAM_CS3 = 0x07,
48 	CPU_ATTR_NANDFLASH = 0x2f,
49 	CPU_ATTR_SPIFLASH = 0x1e,
50 	CPU_ATTR_SPI0_CS0 = 0x1e,
51 	CPU_ATTR_SPI0_CS1 = 0x5e,
52 	CPU_ATTR_SPI1_CS2 = 0x9a,
53 	CPU_ATTR_BOOTROM = 0x1d,
54 	CPU_ATTR_PCIE_IO = 0xe0,
55 	CPU_ATTR_PCIE_MEM = 0xe8,
56 	CPU_ATTR_DEV_CS0 = 0x3e,
57 	CPU_ATTR_DEV_CS1 = 0x3d,
58 	CPU_ATTR_DEV_CS2 = 0x3b,
59 	CPU_ATTR_DEV_CS3 = 0x37,
60 };
61 
62 enum {
63 	MVEBU_SOC_AXP,
64 	MVEBU_SOC_A375,
65 	MVEBU_SOC_A38X,
66 	MVEBU_SOC_UNKNOWN,
67 };
68 
69 /*
70  * Default Device Address MAP BAR values
71  */
72 #define MBUS_PCI_MEM_BASE	0xE8000000
73 #define MBUS_PCI_MEM_SIZE	(128 << 20)
74 #define MBUS_PCI_IO_BASE	0xF1100000
75 #define MBUS_PCI_IO_SIZE	(64 << 10)
76 #define MBUS_SPI_BASE		0xF4000000
77 #define MBUS_SPI_SIZE		(8 << 20)
78 #define MBUS_BOOTROM_BASE	0xF8000000
79 #define MBUS_BOOTROM_SIZE	(8 << 20)
80 
81 struct mbus_win {
82 	u32 base;
83 	u32 size;
84 	u8 target;
85 	u8 attr;
86 };
87 
88 /*
89  * System registers
90  * Ref: Datasheet sec:A.28
91  */
92 struct mvebu_system_registers {
93 #if defined(CONFIG_ARMADA_375)
94 	u8 pad1[0x54];
95 #else
96 	u8 pad1[0x60];
97 #endif
98 	u32 rstoutn_mask; /* 0x60 */
99 	u32 sys_soft_rst; /* 0x64 */
100 };
101 
102 /*
103  * GPIO Registers
104  * Ref: Datasheet sec:A.19
105  */
106 struct kwgpio_registers {
107 	u32 dout;
108 	u32 oe;
109 	u32 blink_en;
110 	u32 din_pol;
111 	u32 din;
112 	u32 irq_cause;
113 	u32 irq_mask;
114 	u32 irq_level;
115 };
116 
117 struct sar_freq_modes {
118 	u8 val;
119 	u8 ffc;		/* Fabric Frequency Configuration */
120 	u32 p_clk;
121 	u32 nb_clk;
122 	u32 d_clk;
123 };
124 
125 /* Needed for dynamic (board-specific) mbus configuration */
126 extern struct mvebu_mbus_state mbus_state;
127 
128 /*
129  * functions
130  */
131 unsigned int mvebu_sdram_bar(enum memory_bank bank);
132 unsigned int mvebu_sdram_bs(enum memory_bank bank);
133 void mvebu_sdram_size_adjust(enum memory_bank bank);
134 int mvebu_mbus_probe(struct mbus_win windows[], int count);
135 int mvebu_soc_family(void);
136 u32 mvebu_get_nand_clock(void);
137 
138 void return_to_bootrom(void);
139 
140 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
141 
142 void get_sar_freq(struct sar_freq_modes *sar_freq);
143 
144 /*
145  * Highspeed SERDES PHY config init, ported from bin_hdr
146  * to mainline U-Boot
147  */
148 int serdes_phy_config(void);
149 
150 /*
151  * DDR3 init / training code ported from Marvell bin_hdr. Now
152  * available in mainline U-Boot in:
153  * drivers/ddr/marvell
154  */
155 int ddr3_init(void);
156 
157 struct mvebu_lcd_info {
158 	u32 fb_base;
159 	int x_res;
160 	int y_res;
161 	int x_fp;		/* frontporch */
162 	int y_fp;
163 	int x_bp;		/* backporch */
164 	int y_bp;
165 };
166 
167 int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
168 
169 /*
170  * get_ref_clk
171  *
172  * return: reference clock in MHz (25 or 40)
173  */
174 u32 get_ref_clk(void);
175 
176 #endif /* __ASSEMBLY__ */
177 #endif /* _MVEBU_CPU_H */
178