1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef _MVEBU_CPU_H
10 #define _MVEBU_CPU_H
11 
12 #include <asm/system.h>
13 
14 #ifndef __ASSEMBLY__
15 
16 #define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
17 #define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
18 
19 enum memory_bank {
20 	BANK0,
21 	BANK1,
22 	BANK2,
23 	BANK3
24 };
25 
26 enum cpu_winen {
27 	CPU_WIN_DISABLE,
28 	CPU_WIN_ENABLE
29 };
30 
31 enum cpu_target {
32 	CPU_TARGET_DRAM = 0x0,
33 	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
34 	CPU_TARGET_ETH23 = 0x3,
35 	CPU_TARGET_PCIE02 = 0x4,
36 	CPU_TARGET_ETH01 = 0x7,
37 	CPU_TARGET_PCIE13 = 0x8,
38 	CPU_TARGET_SASRAM = 0x9,
39 	CPU_TARGET_SATA01 = 0xa, /* A38X */
40 	CPU_TARGET_NAND = 0xd,
41 	CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
42 };
43 
44 enum cpu_attrib {
45 	CPU_ATTR_SASRAM = 0x01,
46 	CPU_ATTR_DRAM_CS0 = 0x0e,
47 	CPU_ATTR_DRAM_CS1 = 0x0d,
48 	CPU_ATTR_DRAM_CS2 = 0x0b,
49 	CPU_ATTR_DRAM_CS3 = 0x07,
50 	CPU_ATTR_NANDFLASH = 0x2f,
51 	CPU_ATTR_SPIFLASH = 0x1e,
52 	CPU_ATTR_SPI0_CS0 = 0x1e,
53 	CPU_ATTR_SPI0_CS1 = 0x5e,
54 	CPU_ATTR_SPI1_CS2 = 0x9a,
55 	CPU_ATTR_BOOTROM = 0x1d,
56 	CPU_ATTR_PCIE_IO = 0xe0,
57 	CPU_ATTR_PCIE_MEM = 0xe8,
58 	CPU_ATTR_DEV_CS0 = 0x3e,
59 	CPU_ATTR_DEV_CS1 = 0x3d,
60 	CPU_ATTR_DEV_CS2 = 0x3b,
61 	CPU_ATTR_DEV_CS3 = 0x37,
62 };
63 
64 enum {
65 	MVEBU_SOC_AXP,
66 	MVEBU_SOC_A375,
67 	MVEBU_SOC_A38X,
68 	MVEBU_SOC_UNKNOWN,
69 };
70 
71 /*
72  * Default Device Address MAP BAR values
73  */
74 #define MBUS_PCI_MEM_BASE	0xE8000000
75 #define MBUS_PCI_MEM_SIZE	(128 << 20)
76 #define MBUS_PCI_IO_BASE	0xF1100000
77 #define MBUS_PCI_IO_SIZE	(64 << 10)
78 #define MBUS_SPI_BASE		0xF4000000
79 #define MBUS_SPI_SIZE		(8 << 20)
80 #define MBUS_BOOTROM_BASE	0xF8000000
81 #define MBUS_BOOTROM_SIZE	(8 << 20)
82 
83 struct mbus_win {
84 	u32 base;
85 	u32 size;
86 	u8 target;
87 	u8 attr;
88 };
89 
90 /*
91  * System registers
92  * Ref: Datasheet sec:A.28
93  */
94 struct mvebu_system_registers {
95 #if defined(CONFIG_ARMADA_375)
96 	u8 pad1[0x54];
97 #else
98 	u8 pad1[0x60];
99 #endif
100 	u32 rstoutn_mask; /* 0x60 */
101 	u32 sys_soft_rst; /* 0x64 */
102 };
103 
104 /*
105  * GPIO Registers
106  * Ref: Datasheet sec:A.19
107  */
108 struct kwgpio_registers {
109 	u32 dout;
110 	u32 oe;
111 	u32 blink_en;
112 	u32 din_pol;
113 	u32 din;
114 	u32 irq_cause;
115 	u32 irq_mask;
116 	u32 irq_level;
117 };
118 
119 struct sar_freq_modes {
120 	u8 val;
121 	u8 ffc;		/* Fabric Frequency Configuration */
122 	u32 p_clk;
123 	u32 nb_clk;
124 	u32 d_clk;
125 };
126 
127 /* Needed for dynamic (board-specific) mbus configuration */
128 extern struct mvebu_mbus_state mbus_state;
129 
130 /*
131  * functions
132  */
133 unsigned int mvebu_sdram_bar(enum memory_bank bank);
134 unsigned int mvebu_sdram_bs(enum memory_bank bank);
135 void mvebu_sdram_size_adjust(enum memory_bank bank);
136 int mvebu_mbus_probe(struct mbus_win windows[], int count);
137 int mvebu_soc_family(void);
138 u32 mvebu_get_nand_clock(void);
139 
140 void return_to_bootrom(void);
141 
142 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
143 
144 void get_sar_freq(struct sar_freq_modes *sar_freq);
145 
146 /*
147  * Highspeed SERDES PHY config init, ported from bin_hdr
148  * to mainline U-Boot
149  */
150 int serdes_phy_config(void);
151 
152 /*
153  * DDR3 init / training code ported from Marvell bin_hdr. Now
154  * available in mainline U-Boot in:
155  * drivers/ddr/marvell
156  */
157 int ddr3_init(void);
158 
159 struct mvebu_lcd_info {
160 	u32 fb_base;
161 	int x_res;
162 	int y_res;
163 	int x_fp;		/* frontporch */
164 	int y_fp;
165 	int x_bp;		/* backporch */
166 	int y_bp;
167 };
168 
169 int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
170 
171 /*
172  * get_ref_clk
173  *
174  * return: reference clock in MHz (25 or 40)
175  */
176 u32 get_ref_clk(void);
177 
178 #endif /* __ASSEMBLY__ */
179 #endif /* _MVEBU_CPU_H */
180