1 /* 2 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ahci.h> 9 #include <linux/mbus.h> 10 #include <asm/io.h> 11 #include <asm/pl310.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 #include <sdhci.h> 15 16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 18 19 static struct mbus_win windows[] = { 20 /* SPI */ 21 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 23 24 /* NOR */ 25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 27 }; 28 29 void lowlevel_init(void) 30 { 31 /* 32 * Dummy implementation, we only need LOWLEVEL_INIT 33 * on Armada to configure CP15 in start.S / cpu_init_cp15() 34 */ 35 } 36 37 void reset_cpu(unsigned long ignored) 38 { 39 struct mvebu_system_registers *reg = 40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 41 42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 44 while (1) 45 ; 46 } 47 48 int mvebu_soc_family(void) 49 { 50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 51 52 switch (devid) { 53 case SOC_MV78230_ID: 54 case SOC_MV78260_ID: 55 case SOC_MV78460_ID: 56 return MVEBU_SOC_AXP; 57 58 case SOC_88F6720_ID: 59 return MVEBU_SOC_A375; 60 61 case SOC_88F6810_ID: 62 case SOC_88F6820_ID: 63 case SOC_88F6828_ID: 64 return MVEBU_SOC_A38X; 65 66 case SOC_98DX3236_ID: 67 case SOC_98DX3336_ID: 68 case SOC_98DX4251_ID: 69 return MVEBU_SOC_MSYS; 70 } 71 72 return MVEBU_SOC_UNKNOWN; 73 } 74 75 #if defined(CONFIG_DISPLAY_CPUINFO) 76 77 #if defined(CONFIG_ARMADA_375) 78 /* SAR frequency values for Armada 375 */ 79 static const struct sar_freq_modes sar_freq_tab[] = { 80 { 0, 0x0, 266, 133, 266 }, 81 { 1, 0x0, 333, 167, 167 }, 82 { 2, 0x0, 333, 167, 222 }, 83 { 3, 0x0, 333, 167, 333 }, 84 { 4, 0x0, 400, 200, 200 }, 85 { 5, 0x0, 400, 200, 267 }, 86 { 6, 0x0, 400, 200, 400 }, 87 { 7, 0x0, 500, 250, 250 }, 88 { 8, 0x0, 500, 250, 334 }, 89 { 9, 0x0, 500, 250, 500 }, 90 { 10, 0x0, 533, 267, 267 }, 91 { 11, 0x0, 533, 267, 356 }, 92 { 12, 0x0, 533, 267, 533 }, 93 { 13, 0x0, 600, 300, 300 }, 94 { 14, 0x0, 600, 300, 400 }, 95 { 15, 0x0, 600, 300, 600 }, 96 { 16, 0x0, 666, 333, 333 }, 97 { 17, 0x0, 666, 333, 444 }, 98 { 18, 0x0, 666, 333, 666 }, 99 { 19, 0x0, 800, 400, 267 }, 100 { 20, 0x0, 800, 400, 400 }, 101 { 21, 0x0, 800, 400, 534 }, 102 { 22, 0x0, 900, 450, 300 }, 103 { 23, 0x0, 900, 450, 450 }, 104 { 24, 0x0, 900, 450, 600 }, 105 { 25, 0x0, 1000, 500, 500 }, 106 { 26, 0x0, 1000, 500, 667 }, 107 { 27, 0x0, 1000, 333, 500 }, 108 { 28, 0x0, 400, 400, 400 }, 109 { 29, 0x0, 1100, 550, 550 }, 110 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 111 }; 112 #elif defined(CONFIG_ARMADA_38X) 113 /* SAR frequency values for Armada 38x */ 114 static const struct sar_freq_modes sar_freq_tab[] = { 115 { 0x0, 0x0, 666, 333, 333 }, 116 { 0x2, 0x0, 800, 400, 400 }, 117 { 0x4, 0x0, 1066, 533, 533 }, 118 { 0x6, 0x0, 1200, 600, 600 }, 119 { 0x8, 0x0, 1332, 666, 666 }, 120 { 0xc, 0x0, 1600, 800, 800 }, 121 { 0x10, 0x0, 1866, 933, 933 }, 122 { 0x13, 0x0, 2000, 1000, 933 }, 123 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 124 }; 125 #else 126 /* SAR frequency values for Armada XP */ 127 static const struct sar_freq_modes sar_freq_tab[] = { 128 { 0xa, 0x5, 800, 400, 400 }, 129 { 0x1, 0x5, 1066, 533, 533 }, 130 { 0x2, 0x5, 1200, 600, 600 }, 131 { 0x2, 0x9, 1200, 600, 400 }, 132 { 0x3, 0x5, 1333, 667, 667 }, 133 { 0x4, 0x5, 1500, 750, 750 }, 134 { 0x4, 0x9, 1500, 750, 500 }, 135 { 0xb, 0x9, 1600, 800, 533 }, 136 { 0xb, 0xa, 1600, 800, 640 }, 137 { 0xb, 0x5, 1600, 800, 800 }, 138 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 139 }; 140 #endif 141 142 void get_sar_freq(struct sar_freq_modes *sar_freq) 143 { 144 u32 val; 145 u32 freq; 146 int i; 147 148 #if defined(CONFIG_ARMADA_375) 149 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ 150 #else 151 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ 152 #endif 153 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; 154 #if defined(SAR2_CPU_FREQ_MASK) 155 /* 156 * Shift CPU0 clock frequency select bit from SAR2 register 157 * into correct position 158 */ 159 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) 160 >> SAR2_CPU_FREQ_OFFS) << 3; 161 #endif 162 for (i = 0; sar_freq_tab[i].val != 0xff; i++) { 163 if (sar_freq_tab[i].val == freq) { 164 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) 165 *sar_freq = sar_freq_tab[i]; 166 return; 167 #else 168 int k; 169 u8 ffc; 170 171 ffc = (val & SAR_FFC_FREQ_MASK) >> 172 SAR_FFC_FREQ_OFFS; 173 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { 174 if (sar_freq_tab[k].ffc == ffc) { 175 *sar_freq = sar_freq_tab[k]; 176 return; 177 } 178 } 179 i = k; 180 #endif 181 } 182 } 183 184 /* SAR value not found, return 0 for frequencies */ 185 *sar_freq = sar_freq_tab[i - 1]; 186 } 187 188 int print_cpuinfo(void) 189 { 190 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 191 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 192 struct sar_freq_modes sar_freq; 193 194 puts("SoC: "); 195 196 switch (devid) { 197 case SOC_MV78230_ID: 198 puts("MV78230-"); 199 break; 200 case SOC_MV78260_ID: 201 puts("MV78260-"); 202 break; 203 case SOC_MV78460_ID: 204 puts("MV78460-"); 205 break; 206 case SOC_88F6720_ID: 207 puts("MV88F6720-"); 208 break; 209 case SOC_88F6810_ID: 210 puts("MV88F6810-"); 211 break; 212 case SOC_88F6820_ID: 213 puts("MV88F6820-"); 214 break; 215 case SOC_88F6828_ID: 216 puts("MV88F6828-"); 217 break; 218 case SOC_98DX3236_ID: 219 puts("98DX3236-"); 220 break; 221 case SOC_98DX3336_ID: 222 puts("98DX3336-"); 223 break; 224 case SOC_98DX4251_ID: 225 puts("98DX4251-"); 226 break; 227 default: 228 puts("Unknown-"); 229 break; 230 } 231 232 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 233 switch (revid) { 234 case 1: 235 puts("A0"); 236 break; 237 case 2: 238 puts("B0"); 239 break; 240 default: 241 printf("?? (%x)", revid); 242 break; 243 } 244 } 245 246 if (mvebu_soc_family() == MVEBU_SOC_A375) { 247 switch (revid) { 248 case MV_88F67XX_A0_ID: 249 puts("A0"); 250 break; 251 default: 252 printf("?? (%x)", revid); 253 break; 254 } 255 } 256 257 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 258 switch (revid) { 259 case MV_88F68XX_Z1_ID: 260 puts("Z1"); 261 break; 262 case MV_88F68XX_A0_ID: 263 puts("A0"); 264 break; 265 default: 266 printf("?? (%x)", revid); 267 break; 268 } 269 } 270 271 get_sar_freq(&sar_freq); 272 printf(" at %d MHz\n", sar_freq.p_clk); 273 274 return 0; 275 } 276 #endif /* CONFIG_DISPLAY_CPUINFO */ 277 278 /* 279 * This function initialize Controller DRAM Fastpath windows. 280 * It takes the CS size information from the 0x1500 scratch registers 281 * and sets the correct windows sizes and base addresses accordingly. 282 * 283 * These values are set in the scratch registers by the Marvell 284 * DDR3 training code, which is executed by the BootROM before the 285 * main payload (U-Boot) is executed. This training code is currently 286 * only available in the Marvell U-Boot version. It needs to be 287 * ported to mainline U-Boot SPL at some point. 288 */ 289 static void update_sdram_window_sizes(void) 290 { 291 u64 base = 0; 292 u32 size, temp; 293 int i; 294 295 for (i = 0; i < SDRAM_MAX_CS; i++) { 296 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 297 if (size != 0) { 298 size |= ~(SDRAM_ADDR_MASK); 299 300 /* Set Base Address */ 301 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 303 304 /* 305 * Check if out of max window size and resize 306 * the window 307 */ 308 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 309 ~(SDRAM_ADDR_MASK)) | 1; 310 temp |= (size & SDRAM_ADDR_MASK); 311 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 312 313 base += ((u64)size + 1); 314 } else { 315 /* 316 * Disable window if not used, otherwise this 317 * leads to overlapping enabled windows with 318 * pretty strange results 319 */ 320 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 321 } 322 } 323 } 324 325 void mmu_disable(void) 326 { 327 asm volatile( 328 "mrc p15, 0, r0, c1, c0, 0\n" 329 "bic r0, #1\n" 330 "mcr p15, 0, r0, c1, c0, 0\n"); 331 } 332 333 #ifdef CONFIG_ARCH_CPU_INIT 334 static void set_cbar(u32 addr) 335 { 336 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 337 } 338 339 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 340 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 341 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 342 (((addr) & 0xF) << 6)) 343 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 344 (((reg) & 0xF) << 2)) 345 346 static void setup_usb_phys(void) 347 { 348 int dev; 349 350 /* 351 * USB PLL init 352 */ 353 354 /* Setup PLL frequency */ 355 /* USB REF frequency = 25 MHz */ 356 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 357 358 /* Power up PLL and PHY channel */ 359 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); 360 361 /* Assert VCOCAL_START */ 362 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); 363 364 mdelay(1); 365 366 /* 367 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 368 */ 369 370 for (dev = 0; dev < 3; dev++) { 371 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); 372 373 /* Assert REG_RCAL_START in channel REG 1 */ 374 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 375 udelay(40); 376 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 377 } 378 } 379 380 /* 381 * This function is not called from the SPL U-Boot version 382 */ 383 int arch_cpu_init(void) 384 { 385 struct pl310_regs *const pl310 = 386 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 387 388 /* 389 * Only with disabled MMU its possible to switch the base 390 * register address on Armada 38x. Without this the SDRAM 391 * located at >= 0x4000.0000 is also not accessible, as its 392 * still locked to cache. 393 */ 394 mmu_disable(); 395 396 /* Linux expects the internal registers to be at 0xf1000000 */ 397 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 398 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 399 400 /* 401 * From this stage on, the SoC detection is working. As we have 402 * configured the internal register base to the value used 403 * in the macros / defines in the U-Boot header (soc.h). 404 */ 405 406 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 407 /* 408 * To fully release / unlock this area from cache, we need 409 * to flush all caches and disable the L2 cache. 410 */ 411 icache_disable(); 412 dcache_disable(); 413 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 414 } 415 416 /* 417 * We need to call mvebu_mbus_probe() before calling 418 * update_sdram_window_sizes() as it disables all previously 419 * configured mbus windows and then configures them as 420 * required for U-Boot. Calling update_sdram_window_sizes() 421 * without this configuration will not work, as the internal 422 * registers can't be accessed reliably because of potenial 423 * double mapping. 424 * After updating the SDRAM access windows we need to call 425 * mvebu_mbus_probe() again, as this now correctly configures 426 * the SDRAM areas that are later used by the MVEBU drivers 427 * (e.g. USB, NETA). 428 */ 429 430 /* 431 * First disable all windows 432 */ 433 mvebu_mbus_probe(NULL, 0); 434 435 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 436 /* 437 * Now the SDRAM access windows can be reconfigured using 438 * the information in the SDRAM scratch pad registers 439 */ 440 update_sdram_window_sizes(); 441 } 442 443 /* 444 * Finally the mbus windows can be configured with the 445 * updated SDRAM sizes 446 */ 447 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 448 449 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 450 /* Enable GBE0, GBE1, LCD and NFC PUP */ 451 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 452 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 453 NAND_PUP_EN | SPI_PUP_EN); 454 455 /* Configure USB PLL and PHYs on AXP */ 456 setup_usb_phys(); 457 } 458 459 /* Enable NAND and NAND arbiter */ 460 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 461 462 /* Disable MBUS error propagation */ 463 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 464 465 return 0; 466 } 467 #endif /* CONFIG_ARCH_CPU_INIT */ 468 469 u32 mvebu_get_nand_clock(void) 470 { 471 u32 reg; 472 473 if (mvebu_soc_family() == MVEBU_SOC_A38X) 474 reg = MVEBU_DFX_DIV_CLK_CTRL(1); 475 else 476 reg = MVEBU_CORE_DIV_CLK_CTRL(1); 477 478 return CONFIG_SYS_MVEBU_PLL_CLOCK / 479 ((readl(reg) & 480 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 481 } 482 483 /* 484 * SOC specific misc init 485 */ 486 #if defined(CONFIG_ARCH_MISC_INIT) 487 int arch_misc_init(void) 488 { 489 /* Nothing yet, perhaps we need something here later */ 490 return 0; 491 } 492 #endif /* CONFIG_ARCH_MISC_INIT */ 493 494 #ifdef CONFIG_MMC_SDHCI_MV 495 int board_mmc_init(bd_t *bis) 496 { 497 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 498 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 499 500 return 0; 501 } 502 #endif 503 504 #ifdef CONFIG_SCSI_AHCI_PLAT 505 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 506 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 507 508 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 509 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 510 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 511 512 static void ahci_mvebu_mbus_config(void __iomem *base) 513 { 514 const struct mbus_dram_target_info *dram; 515 int i; 516 517 dram = mvebu_mbus_dram_info(); 518 519 for (i = 0; i < 4; i++) { 520 writel(0, base + AHCI_WINDOW_CTRL(i)); 521 writel(0, base + AHCI_WINDOW_BASE(i)); 522 writel(0, base + AHCI_WINDOW_SIZE(i)); 523 } 524 525 for (i = 0; i < dram->num_cs; i++) { 526 const struct mbus_dram_window *cs = dram->cs + i; 527 528 writel((cs->mbus_attr << 8) | 529 (dram->mbus_dram_target_id << 4) | 1, 530 base + AHCI_WINDOW_CTRL(i)); 531 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 532 writel(((cs->size - 1) & 0xffff0000), 533 base + AHCI_WINDOW_SIZE(i)); 534 } 535 } 536 537 static void ahci_mvebu_regret_option(void __iomem *base) 538 { 539 /* 540 * Enable the regret bit to allow the SATA unit to regret a 541 * request that didn't receive an acknowlegde and avoid a 542 * deadlock 543 */ 544 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 545 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 546 } 547 548 void scsi_init(void) 549 { 550 printf("MVEBU SATA INIT\n"); 551 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 552 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 553 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 554 } 555 #endif 556 557 void enable_caches(void) 558 { 559 /* Avoid problem with e.g. neta ethernet driver */ 560 invalidate_dcache_all(); 561 562 /* 563 * Armada 375 still has some problems with d-cache enabled in the 564 * ethernet driver (mvpp2). So lets keep the d-cache disabled 565 * until this is solved. 566 */ 567 if (mvebu_soc_family() != MVEBU_SOC_A375) { 568 /* Enable D-cache. I-cache is already enabled in start.S */ 569 dcache_enable(); 570 } 571 } 572 573 void v7_outer_cache_enable(void) 574 { 575 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 576 struct pl310_regs *const pl310 = 577 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 578 u32 u; 579 580 /* The L2 cache is already disabled at this point */ 581 582 /* 583 * For Aurora cache in no outer mode, enable via the CP15 584 * coprocessor broadcasting of cache commands to L2. 585 */ 586 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 587 u |= BIT(8); /* Set the FW bit */ 588 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 589 590 isb(); 591 592 /* Enable the L2 cache */ 593 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 594 } 595 } 596 597 void v7_outer_cache_disable(void) 598 { 599 struct pl310_regs *const pl310 = 600 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 601 602 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 603 } 604