1 /* 2 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ahci.h> 9 #include <linux/mbus.h> 10 #include <asm/io.h> 11 #include <asm/pl310.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 #include <sdhci.h> 15 16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 18 19 static struct mbus_win windows[] = { 20 /* SPI */ 21 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 23 24 /* NOR */ 25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 27 }; 28 29 void lowlevel_init(void) 30 { 31 /* 32 * Dummy implementation, we only need LOWLEVEL_INIT 33 * on Armada to configure CP15 in start.S / cpu_init_cp15() 34 */ 35 } 36 37 void reset_cpu(unsigned long ignored) 38 { 39 struct mvebu_system_registers *reg = 40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 41 42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 44 while (1) 45 ; 46 } 47 48 int mvebu_soc_family(void) 49 { 50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 51 52 if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID)) 53 return MVEBU_SOC_AXP; 54 55 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 56 devid == SOC_88F6828_ID) 57 return MVEBU_SOC_A38X; 58 59 return MVEBU_SOC_UNKNOWN; 60 } 61 62 #if defined(CONFIG_DISPLAY_CPUINFO) 63 64 #if defined(CONFIG_ARMADA_38X) 65 /* SAR frequency values for Armada 38x */ 66 static const struct sar_freq_modes sar_freq_tab[] = { 67 { 0x0, 0x0, 666, 333, 333 }, 68 { 0x2, 0x0, 800, 400, 400 }, 69 { 0x4, 0x0, 1066, 533, 533 }, 70 { 0x6, 0x0, 1200, 600, 600 }, 71 { 0x8, 0x0, 1332, 666, 666 }, 72 { 0xc, 0x0, 1600, 800, 800 }, 73 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 74 }; 75 #else 76 /* SAR frequency values for Armada XP */ 77 static const struct sar_freq_modes sar_freq_tab[] = { 78 { 0xa, 0x5, 800, 400, 400 }, 79 { 0x1, 0x5, 1066, 533, 533 }, 80 { 0x2, 0x5, 1200, 600, 600 }, 81 { 0x2, 0x9, 1200, 600, 400 }, 82 { 0x3, 0x5, 1333, 667, 667 }, 83 { 0x4, 0x5, 1500, 750, 750 }, 84 { 0x4, 0x9, 1500, 750, 500 }, 85 { 0xb, 0x9, 1600, 800, 533 }, 86 { 0xb, 0xa, 1600, 800, 640 }, 87 { 0xb, 0x5, 1600, 800, 800 }, 88 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 89 }; 90 #endif 91 92 void get_sar_freq(struct sar_freq_modes *sar_freq) 93 { 94 u32 val; 95 u32 freq; 96 int i; 97 98 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ 99 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; 100 #if !defined(CONFIG_ARMADA_38X) 101 /* 102 * Shift CPU0 clock frequency select bit from SAR2 register 103 * into correct position 104 */ 105 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) 106 >> SAR2_CPU_FREQ_OFFS) << 3; 107 #endif 108 for (i = 0; sar_freq_tab[i].val != 0xff; i++) { 109 if (sar_freq_tab[i].val == freq) { 110 #if defined(CONFIG_ARMADA_38X) 111 *sar_freq = sar_freq_tab[i]; 112 return; 113 #else 114 int k; 115 u8 ffc; 116 117 ffc = (val & SAR_FFC_FREQ_MASK) >> 118 SAR_FFC_FREQ_OFFS; 119 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { 120 if (sar_freq_tab[k].ffc == ffc) { 121 *sar_freq = sar_freq_tab[k]; 122 return; 123 } 124 } 125 i = k; 126 #endif 127 } 128 } 129 130 /* SAR value not found, return 0 for frequencies */ 131 *sar_freq = sar_freq_tab[i - 1]; 132 } 133 134 int print_cpuinfo(void) 135 { 136 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 137 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 138 struct sar_freq_modes sar_freq; 139 140 puts("SoC: "); 141 142 switch (devid) { 143 case SOC_MV78260_ID: 144 puts("MV78260-"); 145 break; 146 case SOC_MV78460_ID: 147 puts("MV78460-"); 148 break; 149 case SOC_88F6810_ID: 150 puts("MV88F6810-"); 151 break; 152 case SOC_88F6820_ID: 153 puts("MV88F6820-"); 154 break; 155 case SOC_88F6828_ID: 156 puts("MV88F6828-"); 157 break; 158 default: 159 puts("Unknown-"); 160 break; 161 } 162 163 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 164 switch (revid) { 165 case 1: 166 puts("A0"); 167 break; 168 case 2: 169 puts("B0"); 170 break; 171 default: 172 printf("?? (%x)", revid); 173 break; 174 } 175 } 176 177 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 178 switch (revid) { 179 case MV_88F68XX_Z1_ID: 180 puts("Z1"); 181 break; 182 case MV_88F68XX_A0_ID: 183 puts("A0"); 184 break; 185 default: 186 printf("?? (%x)", revid); 187 break; 188 } 189 } 190 191 get_sar_freq(&sar_freq); 192 printf(" at %d MHz\n", sar_freq.p_clk); 193 194 return 0; 195 } 196 #endif /* CONFIG_DISPLAY_CPUINFO */ 197 198 /* 199 * This function initialize Controller DRAM Fastpath windows. 200 * It takes the CS size information from the 0x1500 scratch registers 201 * and sets the correct windows sizes and base addresses accordingly. 202 * 203 * These values are set in the scratch registers by the Marvell 204 * DDR3 training code, which is executed by the BootROM before the 205 * main payload (U-Boot) is executed. This training code is currently 206 * only available in the Marvell U-Boot version. It needs to be 207 * ported to mainline U-Boot SPL at some point. 208 */ 209 static void update_sdram_window_sizes(void) 210 { 211 u64 base = 0; 212 u32 size, temp; 213 int i; 214 215 for (i = 0; i < SDRAM_MAX_CS; i++) { 216 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 217 if (size != 0) { 218 size |= ~(SDRAM_ADDR_MASK); 219 220 /* Set Base Address */ 221 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 222 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 223 224 /* 225 * Check if out of max window size and resize 226 * the window 227 */ 228 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 229 ~(SDRAM_ADDR_MASK)) | 1; 230 temp |= (size & SDRAM_ADDR_MASK); 231 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 232 233 base += ((u64)size + 1); 234 } else { 235 /* 236 * Disable window if not used, otherwise this 237 * leads to overlapping enabled windows with 238 * pretty strange results 239 */ 240 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 241 } 242 } 243 } 244 245 void mmu_disable(void) 246 { 247 asm volatile( 248 "mrc p15, 0, r0, c1, c0, 0\n" 249 "bic r0, #1\n" 250 "mcr p15, 0, r0, c1, c0, 0\n"); 251 } 252 253 #ifdef CONFIG_ARCH_CPU_INIT 254 static void set_cbar(u32 addr) 255 { 256 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 257 } 258 259 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 260 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 261 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 262 (((addr) & 0xF) << 6)) 263 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 264 (((reg) & 0xF) << 2)) 265 266 static void setup_usb_phys(void) 267 { 268 int dev; 269 270 /* 271 * USB PLL init 272 */ 273 274 /* Setup PLL frequency */ 275 /* USB REF frequency = 25 MHz */ 276 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 277 278 /* Power up PLL and PHY channel */ 279 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); 280 281 /* Assert VCOCAL_START */ 282 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); 283 284 mdelay(1); 285 286 /* 287 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 288 */ 289 290 for (dev = 0; dev < 3; dev++) { 291 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); 292 293 /* Assert REG_RCAL_START in channel REG 1 */ 294 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 295 udelay(40); 296 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 297 } 298 } 299 300 /* 301 * This function is not called from the SPL U-Boot version 302 */ 303 int arch_cpu_init(void) 304 { 305 struct pl310_regs *const pl310 = 306 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 307 308 /* 309 * Only with disabled MMU its possible to switch the base 310 * register address on Armada 38x. Without this the SDRAM 311 * located at >= 0x4000.0000 is also not accessible, as its 312 * still locked to cache. 313 */ 314 mmu_disable(); 315 316 /* Linux expects the internal registers to be at 0xf1000000 */ 317 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 318 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 319 320 /* 321 * From this stage on, the SoC detection is working. As we have 322 * configured the internal register base to the value used 323 * in the macros / defines in the U-Boot header (soc.h). 324 */ 325 326 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 327 /* 328 * To fully release / unlock this area from cache, we need 329 * to flush all caches and disable the L2 cache. 330 */ 331 icache_disable(); 332 dcache_disable(); 333 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 334 } 335 336 /* 337 * We need to call mvebu_mbus_probe() before calling 338 * update_sdram_window_sizes() as it disables all previously 339 * configured mbus windows and then configures them as 340 * required for U-Boot. Calling update_sdram_window_sizes() 341 * without this configuration will not work, as the internal 342 * registers can't be accessed reliably because of potenial 343 * double mapping. 344 * After updating the SDRAM access windows we need to call 345 * mvebu_mbus_probe() again, as this now correctly configures 346 * the SDRAM areas that are later used by the MVEBU drivers 347 * (e.g. USB, NETA). 348 */ 349 350 /* 351 * First disable all windows 352 */ 353 mvebu_mbus_probe(NULL, 0); 354 355 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 356 /* 357 * Now the SDRAM access windows can be reconfigured using 358 * the information in the SDRAM scratch pad registers 359 */ 360 update_sdram_window_sizes(); 361 } 362 363 /* 364 * Finally the mbus windows can be configured with the 365 * updated SDRAM sizes 366 */ 367 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 368 369 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 370 /* Enable GBE0, GBE1, LCD and NFC PUP */ 371 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 372 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 373 NAND_PUP_EN | SPI_PUP_EN); 374 375 /* Configure USB PLL and PHYs on AXP */ 376 setup_usb_phys(); 377 } 378 379 /* Enable NAND and NAND arbiter */ 380 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 381 382 /* Disable MBUS error propagation */ 383 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 384 385 return 0; 386 } 387 #endif /* CONFIG_ARCH_CPU_INIT */ 388 389 u32 mvebu_get_nand_clock(void) 390 { 391 return CONFIG_SYS_MVEBU_PLL_CLOCK / 392 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & 393 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 394 } 395 396 /* 397 * SOC specific misc init 398 */ 399 #if defined(CONFIG_ARCH_MISC_INIT) 400 int arch_misc_init(void) 401 { 402 /* Nothing yet, perhaps we need something here later */ 403 return 0; 404 } 405 #endif /* CONFIG_ARCH_MISC_INIT */ 406 407 #ifdef CONFIG_MV_SDHCI 408 int board_mmc_init(bd_t *bis) 409 { 410 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 411 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 412 413 return 0; 414 } 415 #endif 416 417 #ifdef CONFIG_SCSI_AHCI_PLAT 418 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 419 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 420 421 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 422 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 423 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 424 425 static void ahci_mvebu_mbus_config(void __iomem *base) 426 { 427 const struct mbus_dram_target_info *dram; 428 int i; 429 430 dram = mvebu_mbus_dram_info(); 431 432 for (i = 0; i < 4; i++) { 433 writel(0, base + AHCI_WINDOW_CTRL(i)); 434 writel(0, base + AHCI_WINDOW_BASE(i)); 435 writel(0, base + AHCI_WINDOW_SIZE(i)); 436 } 437 438 for (i = 0; i < dram->num_cs; i++) { 439 const struct mbus_dram_window *cs = dram->cs + i; 440 441 writel((cs->mbus_attr << 8) | 442 (dram->mbus_dram_target_id << 4) | 1, 443 base + AHCI_WINDOW_CTRL(i)); 444 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 445 writel(((cs->size - 1) & 0xffff0000), 446 base + AHCI_WINDOW_SIZE(i)); 447 } 448 } 449 450 static void ahci_mvebu_regret_option(void __iomem *base) 451 { 452 /* 453 * Enable the regret bit to allow the SATA unit to regret a 454 * request that didn't receive an acknowlegde and avoid a 455 * deadlock 456 */ 457 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 458 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 459 } 460 461 void scsi_init(void) 462 { 463 printf("MVEBU SATA INIT\n"); 464 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 465 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 466 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 467 } 468 #endif 469 470 void enable_caches(void) 471 { 472 /* Avoid problem with e.g. neta ethernet driver */ 473 invalidate_dcache_all(); 474 475 /* Enable D-cache. I-cache is already enabled in start.S */ 476 dcache_enable(); 477 } 478 479 void v7_outer_cache_enable(void) 480 { 481 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 482 struct pl310_regs *const pl310 = 483 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 484 u32 u; 485 486 /* The L2 cache is already disabled at this point */ 487 488 /* 489 * For Aurora cache in no outer mode, enable via the CP15 490 * coprocessor broadcasting of cache commands to L2. 491 */ 492 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 493 u |= BIT(8); /* Set the FW bit */ 494 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 495 496 isb(); 497 498 /* Enable the L2 cache */ 499 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 500 } 501 } 502 503 void v7_outer_cache_disable(void) 504 { 505 struct pl310_regs *const pl310 = 506 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 507 508 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 509 } 510