1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <ahci.h> 10 #include <linux/mbus.h> 11 #include <asm/io.h> 12 #include <asm/pl310.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <sdhci.h> 16 17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 19 20 static struct mbus_win windows[] = { 21 /* SPI */ 22 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 23 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 24 25 /* NOR */ 26 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 27 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 28 }; 29 30 void lowlevel_init(void) 31 { 32 /* 33 * Dummy implementation, we only need LOWLEVEL_INIT 34 * on Armada to configure CP15 in start.S / cpu_init_cp15() 35 */ 36 } 37 38 void reset_cpu(unsigned long ignored) 39 { 40 struct mvebu_system_registers *reg = 41 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 42 43 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 44 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 45 while (1) 46 ; 47 } 48 49 int mvebu_soc_family(void) 50 { 51 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 52 53 if (devid == SOC_MV78460_ID) 54 return MVEBU_SOC_AXP; 55 56 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 57 devid == SOC_88F6828_ID) 58 return MVEBU_SOC_A38X; 59 60 return MVEBU_SOC_UNKNOWN; 61 } 62 63 #if defined(CONFIG_DISPLAY_CPUINFO) 64 int print_cpuinfo(void) 65 { 66 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 67 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 68 69 puts("SoC: "); 70 71 switch (devid) { 72 case SOC_MV78460_ID: 73 puts("MV78460-"); 74 break; 75 case SOC_88F6810_ID: 76 puts("MV88F6810-"); 77 break; 78 case SOC_88F6820_ID: 79 puts("MV88F6820-"); 80 break; 81 case SOC_88F6828_ID: 82 puts("MV88F6828-"); 83 break; 84 default: 85 puts("Unknown-"); 86 break; 87 } 88 89 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 90 switch (revid) { 91 case 1: 92 puts("A0\n"); 93 break; 94 case 2: 95 puts("B0\n"); 96 break; 97 default: 98 printf("?? (%x)\n", revid); 99 break; 100 } 101 } 102 103 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 104 switch (revid) { 105 case MV_88F68XX_Z1_ID: 106 puts("Z1\n"); 107 break; 108 case MV_88F68XX_A0_ID: 109 puts("A0\n"); 110 break; 111 default: 112 printf("?? (%x)\n", revid); 113 break; 114 } 115 } 116 117 return 0; 118 } 119 #endif /* CONFIG_DISPLAY_CPUINFO */ 120 121 /* 122 * This function initialize Controller DRAM Fastpath windows. 123 * It takes the CS size information from the 0x1500 scratch registers 124 * and sets the correct windows sizes and base addresses accordingly. 125 * 126 * These values are set in the scratch registers by the Marvell 127 * DDR3 training code, which is executed by the BootROM before the 128 * main payload (U-Boot) is executed. This training code is currently 129 * only available in the Marvell U-Boot version. It needs to be 130 * ported to mainline U-Boot SPL at some point. 131 */ 132 static void update_sdram_window_sizes(void) 133 { 134 u64 base = 0; 135 u32 size, temp; 136 int i; 137 138 for (i = 0; i < SDRAM_MAX_CS; i++) { 139 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 140 if (size != 0) { 141 size |= ~(SDRAM_ADDR_MASK); 142 143 /* Set Base Address */ 144 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 145 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 146 147 /* 148 * Check if out of max window size and resize 149 * the window 150 */ 151 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 152 ~(SDRAM_ADDR_MASK)) | 1; 153 temp |= (size & SDRAM_ADDR_MASK); 154 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 155 156 base += ((u64)size + 1); 157 } else { 158 /* 159 * Disable window if not used, otherwise this 160 * leads to overlapping enabled windows with 161 * pretty strange results 162 */ 163 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 164 } 165 } 166 } 167 168 void mmu_disable(void) 169 { 170 asm volatile( 171 "mrc p15, 0, r0, c1, c0, 0\n" 172 "bic r0, #1\n" 173 "mcr p15, 0, r0, c1, c0, 0\n"); 174 } 175 176 #ifdef CONFIG_ARCH_CPU_INIT 177 static void set_cbar(u32 addr) 178 { 179 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 180 } 181 182 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 183 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 184 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 185 (((addr) & 0xF) << 6)) 186 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 187 (((reg) & 0xF) << 2)) 188 189 static void setup_usb_phys(void) 190 { 191 int dev; 192 193 /* 194 * USB PLL init 195 */ 196 197 /* Setup PLL frequency */ 198 /* USB REF frequency = 25 MHz */ 199 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 200 201 /* Power up PLL and PHY channel */ 202 clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9)); 203 204 /* Assert VCOCAL_START */ 205 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21)); 206 207 mdelay(1); 208 209 /* 210 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 211 */ 212 213 for (dev = 0; dev < 3; dev++) { 214 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15)); 215 216 /* Assert REG_RCAL_START in channel REG 1 */ 217 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12)); 218 udelay(40); 219 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0); 220 } 221 } 222 223 int arch_cpu_init(void) 224 { 225 #if !defined(CONFIG_SPL_BUILD) 226 struct pl310_regs *const pl310 = 227 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 228 229 /* 230 * Only with disabled MMU its possible to switch the base 231 * register address on Armada 38x. Without this the SDRAM 232 * located at >= 0x4000.0000 is also not accessible, as its 233 * still locked to cache. 234 */ 235 mmu_disable(); 236 #endif 237 238 /* Linux expects the internal registers to be at 0xf1000000 */ 239 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 240 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 241 242 #if !defined(CONFIG_SPL_BUILD) 243 /* 244 * From this stage on, the SoC detection is working. As we have 245 * configured the internal register base to the value used 246 * in the macros / defines in the U-Boot header (soc.h). 247 */ 248 249 /* 250 * To fully release / unlock this area from cache, we need 251 * to flush all caches and disable the L2 cache. 252 */ 253 icache_disable(); 254 dcache_disable(); 255 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 256 #endif 257 258 /* 259 * We need to call mvebu_mbus_probe() before calling 260 * update_sdram_window_sizes() as it disables all previously 261 * configured mbus windows and then configures them as 262 * required for U-Boot. Calling update_sdram_window_sizes() 263 * without this configuration will not work, as the internal 264 * registers can't be accessed reliably because of potenial 265 * double mapping. 266 * After updating the SDRAM access windows we need to call 267 * mvebu_mbus_probe() again, as this now correctly configures 268 * the SDRAM areas that are later used by the MVEBU drivers 269 * (e.g. USB, NETA). 270 */ 271 272 /* 273 * First disable all windows 274 */ 275 mvebu_mbus_probe(NULL, 0); 276 277 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 278 /* 279 * Now the SDRAM access windows can be reconfigured using 280 * the information in the SDRAM scratch pad registers 281 */ 282 update_sdram_window_sizes(); 283 } 284 285 /* 286 * Finally the mbus windows can be configured with the 287 * updated SDRAM sizes 288 */ 289 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 290 291 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 292 /* Enable GBE0, GBE1, LCD and NFC PUP */ 293 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 294 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 295 NAND_PUP_EN | SPI_PUP_EN); 296 297 /* Configure USB PLL and PHYs on AXP */ 298 setup_usb_phys(); 299 } 300 301 /* Enable NAND and NAND arbiter */ 302 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 303 304 /* Disable MBUS error propagation */ 305 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 306 307 return 0; 308 } 309 #endif /* CONFIG_ARCH_CPU_INIT */ 310 311 u32 mvebu_get_nand_clock(void) 312 { 313 return CONFIG_SYS_MVEBU_PLL_CLOCK / 314 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & 315 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 316 } 317 318 /* 319 * SOC specific misc init 320 */ 321 #if defined(CONFIG_ARCH_MISC_INIT) 322 int arch_misc_init(void) 323 { 324 /* Nothing yet, perhaps we need something here later */ 325 return 0; 326 } 327 #endif /* CONFIG_ARCH_MISC_INIT */ 328 329 #ifdef CONFIG_MVNETA 330 int cpu_eth_init(bd_t *bis) 331 { 332 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, 333 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; 334 u8 phy_addr[] = CONFIG_PHY_ADDR; 335 int i; 336 337 /* 338 * Only Armada XP supports all 4 ethernet interfaces. A38x has 339 * slightly different base addresses for its 2-3 interfaces. 340 */ 341 if (mvebu_soc_family() != MVEBU_SOC_AXP) { 342 enet_base[1] = MVEBU_EGIGA2_BASE; 343 enet_base[2] = MVEBU_EGIGA3_BASE; 344 } 345 346 for (i = 0; i < ARRAY_SIZE(phy_addr); i++) 347 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); 348 349 return 0; 350 } 351 #endif 352 353 #ifdef CONFIG_MV_SDHCI 354 int board_mmc_init(bd_t *bis) 355 { 356 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 357 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 358 359 return 0; 360 } 361 #endif 362 363 #ifdef CONFIG_SCSI_AHCI_PLAT 364 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 365 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 366 367 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 368 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 369 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 370 371 static void ahci_mvebu_mbus_config(void __iomem *base) 372 { 373 const struct mbus_dram_target_info *dram; 374 int i; 375 376 dram = mvebu_mbus_dram_info(); 377 378 for (i = 0; i < 4; i++) { 379 writel(0, base + AHCI_WINDOW_CTRL(i)); 380 writel(0, base + AHCI_WINDOW_BASE(i)); 381 writel(0, base + AHCI_WINDOW_SIZE(i)); 382 } 383 384 for (i = 0; i < dram->num_cs; i++) { 385 const struct mbus_dram_window *cs = dram->cs + i; 386 387 writel((cs->mbus_attr << 8) | 388 (dram->mbus_dram_target_id << 4) | 1, 389 base + AHCI_WINDOW_CTRL(i)); 390 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 391 writel(((cs->size - 1) & 0xffff0000), 392 base + AHCI_WINDOW_SIZE(i)); 393 } 394 } 395 396 static void ahci_mvebu_regret_option(void __iomem *base) 397 { 398 /* 399 * Enable the regret bit to allow the SATA unit to regret a 400 * request that didn't receive an acknowlegde and avoid a 401 * deadlock 402 */ 403 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 404 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 405 } 406 407 void scsi_init(void) 408 { 409 printf("MVEBU SATA INIT\n"); 410 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 411 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 412 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 413 } 414 #endif 415 416 #ifndef CONFIG_SYS_DCACHE_OFF 417 void enable_caches(void) 418 { 419 struct pl310_regs *const pl310 = 420 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 421 422 /* First disable L2 cache - may still be enable from BootROM */ 423 if (mvebu_soc_family() == MVEBU_SOC_A38X) 424 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 425 426 /* Avoid problem with e.g. neta ethernet driver */ 427 invalidate_dcache_all(); 428 429 /* Enable D-cache. I-cache is already enabled in start.S */ 430 dcache_enable(); 431 } 432 #endif 433