1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <asm/io.h> 10 #include <asm/pl310.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 15 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 16 17 static struct mbus_win windows[] = { 18 /* PCIE MEM address space */ 19 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, 20 21 /* PCIE IO address space */ 22 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, 23 24 /* SPI */ 25 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 26 CPU_ATTR_SPIFLASH }, 27 28 /* NOR */ 29 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 30 CPU_ATTR_BOOTROM }, 31 }; 32 33 void reset_cpu(unsigned long ignored) 34 { 35 struct mvebu_system_registers *reg = 36 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 37 38 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 39 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 40 while (1) 41 ; 42 } 43 44 int mvebu_soc_family(void) 45 { 46 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 47 48 if (devid == SOC_MV78460_ID) 49 return MVEBU_SOC_AXP; 50 51 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 52 devid == SOC_88F6828_ID) 53 return MVEBU_SOC_A38X; 54 55 return MVEBU_SOC_UNKNOWN; 56 } 57 58 #if defined(CONFIG_DISPLAY_CPUINFO) 59 int print_cpuinfo(void) 60 { 61 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 62 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 63 64 puts("SoC: "); 65 66 switch (devid) { 67 case SOC_MV78460_ID: 68 puts("MV78460-"); 69 break; 70 case SOC_88F6810_ID: 71 puts("MV88F6810-"); 72 break; 73 case SOC_88F6820_ID: 74 puts("MV88F6820-"); 75 break; 76 case SOC_88F6828_ID: 77 puts("MV88F6828-"); 78 break; 79 default: 80 puts("Unknown-"); 81 break; 82 } 83 84 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 85 switch (revid) { 86 case 1: 87 puts("A0\n"); 88 break; 89 case 2: 90 puts("B0\n"); 91 break; 92 default: 93 printf("?? (%x)\n", revid); 94 break; 95 } 96 } 97 98 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 99 switch (revid) { 100 case MV_88F68XX_Z1_ID: 101 puts("Z1\n"); 102 break; 103 case MV_88F68XX_A0_ID: 104 puts("A0\n"); 105 break; 106 default: 107 printf("?? (%x)\n", revid); 108 break; 109 } 110 } 111 112 return 0; 113 } 114 #endif /* CONFIG_DISPLAY_CPUINFO */ 115 116 /* 117 * This function initialize Controller DRAM Fastpath windows. 118 * It takes the CS size information from the 0x1500 scratch registers 119 * and sets the correct windows sizes and base addresses accordingly. 120 * 121 * These values are set in the scratch registers by the Marvell 122 * DDR3 training code, which is executed by the BootROM before the 123 * main payload (U-Boot) is executed. This training code is currently 124 * only available in the Marvell U-Boot version. It needs to be 125 * ported to mainline U-Boot SPL at some point. 126 */ 127 static void update_sdram_window_sizes(void) 128 { 129 u64 base = 0; 130 u32 size, temp; 131 int i; 132 133 for (i = 0; i < SDRAM_MAX_CS; i++) { 134 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 135 if (size != 0) { 136 size |= ~(SDRAM_ADDR_MASK); 137 138 /* Set Base Address */ 139 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 140 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 141 142 /* 143 * Check if out of max window size and resize 144 * the window 145 */ 146 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 147 ~(SDRAM_ADDR_MASK)) | 1; 148 temp |= (size & SDRAM_ADDR_MASK); 149 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 150 151 base += ((u64)size + 1); 152 } else { 153 /* 154 * Disable window if not used, otherwise this 155 * leads to overlapping enabled windows with 156 * pretty strange results 157 */ 158 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 159 } 160 } 161 } 162 163 #ifdef CONFIG_ARCH_CPU_INIT 164 static void set_cbar(u32 addr) 165 { 166 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 167 } 168 169 170 int arch_cpu_init(void) 171 { 172 /* Linux expects the internal registers to be at 0xf1000000 */ 173 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 174 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 175 176 /* 177 * We need to call mvebu_mbus_probe() before calling 178 * update_sdram_window_sizes() as it disables all previously 179 * configured mbus windows and then configures them as 180 * required for U-Boot. Calling update_sdram_window_sizes() 181 * without this configuration will not work, as the internal 182 * registers can't be accessed reliably because of potenial 183 * double mapping. 184 * After updating the SDRAM access windows we need to call 185 * mvebu_mbus_probe() again, as this now correctly configures 186 * the SDRAM areas that are later used by the MVEBU drivers 187 * (e.g. USB, NETA). 188 */ 189 190 /* 191 * First disable all windows 192 */ 193 mvebu_mbus_probe(NULL, 0); 194 195 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 196 /* 197 * Now the SDRAM access windows can be reconfigured using 198 * the information in the SDRAM scratch pad registers 199 */ 200 update_sdram_window_sizes(); 201 } 202 203 /* 204 * Finally the mbus windows can be configured with the 205 * updated SDRAM sizes 206 */ 207 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 208 209 return 0; 210 } 211 #endif /* CONFIG_ARCH_CPU_INIT */ 212 213 /* 214 * SOC specific misc init 215 */ 216 #if defined(CONFIG_ARCH_MISC_INIT) 217 int arch_misc_init(void) 218 { 219 /* Nothing yet, perhaps we need something here later */ 220 return 0; 221 } 222 #endif /* CONFIG_ARCH_MISC_INIT */ 223 224 #ifdef CONFIG_MVNETA 225 int cpu_eth_init(bd_t *bis) 226 { 227 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, 228 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; 229 u8 phy_addr[] = CONFIG_PHY_ADDR; 230 int i; 231 232 /* 233 * Only Armada XP supports all 4 ethernet interfaces. A38x has 234 * slightly different base addresses for its 2-3 interfaces. 235 */ 236 if (mvebu_soc_family() != MVEBU_SOC_AXP) { 237 enet_base[1] = MVEBU_EGIGA2_BASE; 238 enet_base[2] = MVEBU_EGIGA3_BASE; 239 } 240 241 for (i = 0; i < ARRAY_SIZE(phy_addr); i++) 242 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); 243 244 return 0; 245 } 246 #endif 247 248 #ifndef CONFIG_SYS_DCACHE_OFF 249 void enable_caches(void) 250 { 251 struct pl310_regs *const pl310 = 252 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 253 254 /* First disable L2 cache - may still be enable from BootROM */ 255 if (mvebu_soc_family() == MVEBU_SOC_A38X) 256 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 257 258 /* Avoid problem with e.g. neta ethernet driver */ 259 invalidate_dcache_all(); 260 261 /* Enable D-cache. I-cache is already enabled in start.S */ 262 dcache_enable(); 263 } 264 #endif 265