1 /* 2 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ahci.h> 9 #include <linux/mbus.h> 10 #include <asm/io.h> 11 #include <asm/pl310.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 #include <sdhci.h> 15 16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 18 19 static struct mbus_win windows[] = { 20 /* SPI */ 21 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 23 24 /* NOR */ 25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 27 }; 28 29 void lowlevel_init(void) 30 { 31 /* 32 * Dummy implementation, we only need LOWLEVEL_INIT 33 * on Armada to configure CP15 in start.S / cpu_init_cp15() 34 */ 35 } 36 37 void reset_cpu(unsigned long ignored) 38 { 39 struct mvebu_system_registers *reg = 40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 41 42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 44 while (1) 45 ; 46 } 47 48 int mvebu_soc_family(void) 49 { 50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 51 52 switch (devid) { 53 case SOC_MV78230_ID: 54 case SOC_MV78260_ID: 55 case SOC_MV78460_ID: 56 return MVEBU_SOC_AXP; 57 case SOC_88F6810_ID: 58 case SOC_88F6820_ID: 59 case SOC_88F6828_ID: 60 return MVEBU_SOC_A38X; 61 } 62 return MVEBU_SOC_UNKNOWN; 63 } 64 65 #if defined(CONFIG_DISPLAY_CPUINFO) 66 67 #if defined(CONFIG_ARMADA_38X) 68 /* SAR frequency values for Armada 38x */ 69 static const struct sar_freq_modes sar_freq_tab[] = { 70 { 0x0, 0x0, 666, 333, 333 }, 71 { 0x2, 0x0, 800, 400, 400 }, 72 { 0x4, 0x0, 1066, 533, 533 }, 73 { 0x6, 0x0, 1200, 600, 600 }, 74 { 0x8, 0x0, 1332, 666, 666 }, 75 { 0xc, 0x0, 1600, 800, 800 }, 76 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 77 }; 78 #else 79 /* SAR frequency values for Armada XP */ 80 static const struct sar_freq_modes sar_freq_tab[] = { 81 { 0xa, 0x5, 800, 400, 400 }, 82 { 0x1, 0x5, 1066, 533, 533 }, 83 { 0x2, 0x5, 1200, 600, 600 }, 84 { 0x2, 0x9, 1200, 600, 400 }, 85 { 0x3, 0x5, 1333, 667, 667 }, 86 { 0x4, 0x5, 1500, 750, 750 }, 87 { 0x4, 0x9, 1500, 750, 500 }, 88 { 0xb, 0x9, 1600, 800, 533 }, 89 { 0xb, 0xa, 1600, 800, 640 }, 90 { 0xb, 0x5, 1600, 800, 800 }, 91 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 92 }; 93 #endif 94 95 void get_sar_freq(struct sar_freq_modes *sar_freq) 96 { 97 u32 val; 98 u32 freq; 99 int i; 100 101 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ 102 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; 103 #if !defined(CONFIG_ARMADA_38X) 104 /* 105 * Shift CPU0 clock frequency select bit from SAR2 register 106 * into correct position 107 */ 108 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) 109 >> SAR2_CPU_FREQ_OFFS) << 3; 110 #endif 111 for (i = 0; sar_freq_tab[i].val != 0xff; i++) { 112 if (sar_freq_tab[i].val == freq) { 113 #if defined(CONFIG_ARMADA_38X) 114 *sar_freq = sar_freq_tab[i]; 115 return; 116 #else 117 int k; 118 u8 ffc; 119 120 ffc = (val & SAR_FFC_FREQ_MASK) >> 121 SAR_FFC_FREQ_OFFS; 122 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { 123 if (sar_freq_tab[k].ffc == ffc) { 124 *sar_freq = sar_freq_tab[k]; 125 return; 126 } 127 } 128 i = k; 129 #endif 130 } 131 } 132 133 /* SAR value not found, return 0 for frequencies */ 134 *sar_freq = sar_freq_tab[i - 1]; 135 } 136 137 int print_cpuinfo(void) 138 { 139 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 140 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 141 struct sar_freq_modes sar_freq; 142 143 puts("SoC: "); 144 145 switch (devid) { 146 case SOC_MV78230_ID: 147 puts("MV78230-"); 148 break; 149 case SOC_MV78260_ID: 150 puts("MV78260-"); 151 break; 152 case SOC_MV78460_ID: 153 puts("MV78460-"); 154 break; 155 case SOC_88F6810_ID: 156 puts("MV88F6810-"); 157 break; 158 case SOC_88F6820_ID: 159 puts("MV88F6820-"); 160 break; 161 case SOC_88F6828_ID: 162 puts("MV88F6828-"); 163 break; 164 default: 165 puts("Unknown-"); 166 break; 167 } 168 169 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 170 switch (revid) { 171 case 1: 172 puts("A0"); 173 break; 174 case 2: 175 puts("B0"); 176 break; 177 default: 178 printf("?? (%x)", revid); 179 break; 180 } 181 } 182 183 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 184 switch (revid) { 185 case MV_88F68XX_Z1_ID: 186 puts("Z1"); 187 break; 188 case MV_88F68XX_A0_ID: 189 puts("A0"); 190 break; 191 default: 192 printf("?? (%x)", revid); 193 break; 194 } 195 } 196 197 get_sar_freq(&sar_freq); 198 printf(" at %d MHz\n", sar_freq.p_clk); 199 200 return 0; 201 } 202 #endif /* CONFIG_DISPLAY_CPUINFO */ 203 204 /* 205 * This function initialize Controller DRAM Fastpath windows. 206 * It takes the CS size information from the 0x1500 scratch registers 207 * and sets the correct windows sizes and base addresses accordingly. 208 * 209 * These values are set in the scratch registers by the Marvell 210 * DDR3 training code, which is executed by the BootROM before the 211 * main payload (U-Boot) is executed. This training code is currently 212 * only available in the Marvell U-Boot version. It needs to be 213 * ported to mainline U-Boot SPL at some point. 214 */ 215 static void update_sdram_window_sizes(void) 216 { 217 u64 base = 0; 218 u32 size, temp; 219 int i; 220 221 for (i = 0; i < SDRAM_MAX_CS; i++) { 222 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 223 if (size != 0) { 224 size |= ~(SDRAM_ADDR_MASK); 225 226 /* Set Base Address */ 227 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 228 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 229 230 /* 231 * Check if out of max window size and resize 232 * the window 233 */ 234 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 235 ~(SDRAM_ADDR_MASK)) | 1; 236 temp |= (size & SDRAM_ADDR_MASK); 237 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 238 239 base += ((u64)size + 1); 240 } else { 241 /* 242 * Disable window if not used, otherwise this 243 * leads to overlapping enabled windows with 244 * pretty strange results 245 */ 246 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 247 } 248 } 249 } 250 251 void mmu_disable(void) 252 { 253 asm volatile( 254 "mrc p15, 0, r0, c1, c0, 0\n" 255 "bic r0, #1\n" 256 "mcr p15, 0, r0, c1, c0, 0\n"); 257 } 258 259 #ifdef CONFIG_ARCH_CPU_INIT 260 static void set_cbar(u32 addr) 261 { 262 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 263 } 264 265 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 266 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 267 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 268 (((addr) & 0xF) << 6)) 269 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 270 (((reg) & 0xF) << 2)) 271 272 static void setup_usb_phys(void) 273 { 274 int dev; 275 276 /* 277 * USB PLL init 278 */ 279 280 /* Setup PLL frequency */ 281 /* USB REF frequency = 25 MHz */ 282 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 283 284 /* Power up PLL and PHY channel */ 285 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); 286 287 /* Assert VCOCAL_START */ 288 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); 289 290 mdelay(1); 291 292 /* 293 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 294 */ 295 296 for (dev = 0; dev < 3; dev++) { 297 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); 298 299 /* Assert REG_RCAL_START in channel REG 1 */ 300 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 301 udelay(40); 302 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 303 } 304 } 305 306 /* 307 * This function is not called from the SPL U-Boot version 308 */ 309 int arch_cpu_init(void) 310 { 311 struct pl310_regs *const pl310 = 312 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 313 314 /* 315 * Only with disabled MMU its possible to switch the base 316 * register address on Armada 38x. Without this the SDRAM 317 * located at >= 0x4000.0000 is also not accessible, as its 318 * still locked to cache. 319 */ 320 mmu_disable(); 321 322 /* Linux expects the internal registers to be at 0xf1000000 */ 323 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 324 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 325 326 /* 327 * From this stage on, the SoC detection is working. As we have 328 * configured the internal register base to the value used 329 * in the macros / defines in the U-Boot header (soc.h). 330 */ 331 332 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 333 /* 334 * To fully release / unlock this area from cache, we need 335 * to flush all caches and disable the L2 cache. 336 */ 337 icache_disable(); 338 dcache_disable(); 339 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 340 } 341 342 /* 343 * We need to call mvebu_mbus_probe() before calling 344 * update_sdram_window_sizes() as it disables all previously 345 * configured mbus windows and then configures them as 346 * required for U-Boot. Calling update_sdram_window_sizes() 347 * without this configuration will not work, as the internal 348 * registers can't be accessed reliably because of potenial 349 * double mapping. 350 * After updating the SDRAM access windows we need to call 351 * mvebu_mbus_probe() again, as this now correctly configures 352 * the SDRAM areas that are later used by the MVEBU drivers 353 * (e.g. USB, NETA). 354 */ 355 356 /* 357 * First disable all windows 358 */ 359 mvebu_mbus_probe(NULL, 0); 360 361 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 362 /* 363 * Now the SDRAM access windows can be reconfigured using 364 * the information in the SDRAM scratch pad registers 365 */ 366 update_sdram_window_sizes(); 367 } 368 369 /* 370 * Finally the mbus windows can be configured with the 371 * updated SDRAM sizes 372 */ 373 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 374 375 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 376 /* Enable GBE0, GBE1, LCD and NFC PUP */ 377 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 378 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 379 NAND_PUP_EN | SPI_PUP_EN); 380 381 /* Configure USB PLL and PHYs on AXP */ 382 setup_usb_phys(); 383 } 384 385 /* Enable NAND and NAND arbiter */ 386 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 387 388 /* Disable MBUS error propagation */ 389 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 390 391 return 0; 392 } 393 #endif /* CONFIG_ARCH_CPU_INIT */ 394 395 u32 mvebu_get_nand_clock(void) 396 { 397 return CONFIG_SYS_MVEBU_PLL_CLOCK / 398 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & 399 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 400 } 401 402 /* 403 * SOC specific misc init 404 */ 405 #if defined(CONFIG_ARCH_MISC_INIT) 406 int arch_misc_init(void) 407 { 408 /* Nothing yet, perhaps we need something here later */ 409 return 0; 410 } 411 #endif /* CONFIG_ARCH_MISC_INIT */ 412 413 #ifdef CONFIG_MV_SDHCI 414 int board_mmc_init(bd_t *bis) 415 { 416 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 417 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 418 419 return 0; 420 } 421 #endif 422 423 #ifdef CONFIG_SCSI_AHCI_PLAT 424 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 425 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 426 427 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 428 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 429 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 430 431 static void ahci_mvebu_mbus_config(void __iomem *base) 432 { 433 const struct mbus_dram_target_info *dram; 434 int i; 435 436 dram = mvebu_mbus_dram_info(); 437 438 for (i = 0; i < 4; i++) { 439 writel(0, base + AHCI_WINDOW_CTRL(i)); 440 writel(0, base + AHCI_WINDOW_BASE(i)); 441 writel(0, base + AHCI_WINDOW_SIZE(i)); 442 } 443 444 for (i = 0; i < dram->num_cs; i++) { 445 const struct mbus_dram_window *cs = dram->cs + i; 446 447 writel((cs->mbus_attr << 8) | 448 (dram->mbus_dram_target_id << 4) | 1, 449 base + AHCI_WINDOW_CTRL(i)); 450 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 451 writel(((cs->size - 1) & 0xffff0000), 452 base + AHCI_WINDOW_SIZE(i)); 453 } 454 } 455 456 static void ahci_mvebu_regret_option(void __iomem *base) 457 { 458 /* 459 * Enable the regret bit to allow the SATA unit to regret a 460 * request that didn't receive an acknowlegde and avoid a 461 * deadlock 462 */ 463 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 464 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 465 } 466 467 void scsi_init(void) 468 { 469 printf("MVEBU SATA INIT\n"); 470 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 471 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 472 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 473 } 474 #endif 475 476 void enable_caches(void) 477 { 478 /* Avoid problem with e.g. neta ethernet driver */ 479 invalidate_dcache_all(); 480 481 /* Enable D-cache. I-cache is already enabled in start.S */ 482 dcache_enable(); 483 } 484 485 void v7_outer_cache_enable(void) 486 { 487 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 488 struct pl310_regs *const pl310 = 489 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 490 u32 u; 491 492 /* The L2 cache is already disabled at this point */ 493 494 /* 495 * For Aurora cache in no outer mode, enable via the CP15 496 * coprocessor broadcasting of cache commands to L2. 497 */ 498 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 499 u |= BIT(8); /* Set the FW bit */ 500 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 501 502 isb(); 503 504 /* Enable the L2 cache */ 505 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 506 } 507 } 508 509 void v7_outer_cache_disable(void) 510 { 511 struct pl310_regs *const pl310 = 512 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 513 514 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 515 } 516